WO2014049968A1 - Thin-film transistor and method for producing same - Google Patents

Abstract

A thin-film transistor obtained by stacking the following on an insulating substrate in this order: a gate electrode, a gate-insulating film, and a source electrode and a drain electrode which have a gap interposed between one another in the region overlapping the gate electrode when seen from a planar view. The thin-film transistor also has a semiconductor pattern having a region in the gap. Therein: the gap has a first region having a constant interval, and a second region where the interval gradually increases; and the semiconductor pattern is shaped so as to contain the entirety of the region having the constant interval, and a portion of the region where the interval gradually increases.

Description

Thin film transistor and manufacturing method thereof

The present invention relates to a thin film transistor and a manufacturing method thereof, and particularly relates to a thin film transistor suitable for a flexible substrate or a printing method and a manufacturing method thereof.

Based on transistor and integrated circuit technology based on the semiconductor itself, amorphous silicon (a-Si) and polysilicon (poly-Si) thin film transistors (Thin Film Transistor: TFT) are manufactured on a glass substrate. (Non-Patent Document 1). As the TFT, for example, the one shown in FIG. 13 is used (the semiconductor shape is not clearly shown in FIG. 13). Here, the TFT plays a role of a switch. When the TFT is turned on by a selection voltage applied to the gate wiring 2 ′, the signal voltage applied to the source wiring 4 ′ is applied to the pixel electrode 5 ′ connected to the drain 5. Write to. The written voltage is held in a storage capacitor constituted by the pixel electrode 5 ′ / gate insulating film 3 / capacitor electrode 10. The gate insulating film 3 is above the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′, and the source electrode 4, the source wiring 4 ′, the drain electrode 5, the pixel electrode 5 ′, and , Located below the semiconductor pattern (not shown). A voltage is applied to the capacitor electrode 10 from the capacitor wiring 10 ′. Here, in the case of a TFT array, since the functions of the source and the drain vary depending on the polarity of the voltage to be written, the names of the source and the drain cannot be determined by the characteristics of the operation. Therefore, for convenience, one is called a source and the other is called a drain, and the names are unified. In the present invention, the one connected to the wiring is called a source, and the one connected to the pixel electrode is called a drain.

Edited by Shoichi Matsumoto: "Liquid Crystal Display Technology-Active Matrix LCD-" Industrial Books, published in November 1996, p. 55

In recent years, organic semiconductors and oxide semiconductors have appeared, and it has been shown that TFTs can be produced at a low temperature of 200 ° C. or lower, and expectations for flexible displays using plastic substrates are increasing. In addition to the feature of flexibility, it is also expected to be light, hard to break, and thin. Moreover, an inexpensive and large-area display is expected by forming TFTs by printing.

By the way, when a flexible substrate is used or when a printing method is used, the misalignment becomes larger than when a rigid substrate and a photolithography method are used. This is because the flexible substrate has poor positional accuracy of the substrate itself, and the printing method is due to deterioration of positional accuracy due to movement during printing. Further, when the viscosity of the ink is small, there is a problem that the pattern width of semiconductor printing varies due to the flow after printing.

The dimension parameters that most affect the current characteristics of the thin film transistor are the channel length L and the channel width W. A channel is a region in which a current flows in a semiconductor, a channel length L is a length in a current direction, and a channel width W is a width in a direction perpendicular to the current. The channel length L is substantially determined by the distance between the source electrode and the drain electrode, and if the source electrode and the drain electrode are formed by the same printing, there is no influence of misalignment or semiconductor printing. However, the channel width W is greatly affected by misalignment of the semiconductor formation to the source / drain electrodes and the pattern width. For example, in the case of the pattern design shown in FIGS. 14A to 14C, FIG. 14A is as designed, but when the semiconductor pattern 6 is shifted to the right as shown in FIG. 14B, W increases, and the semiconductor is shifted to the left as shown in FIG. 14C. And W become smaller. In the case of the pattern designs shown in FIGS. 15A to 15C, FIG. 15A is as designed, but as the width of the semiconductor pattern 6 increases as shown in FIG. 15B, W increases, and as shown in FIG. 15C, the width of the semiconductor pattern 6 increases. As it becomes smaller, W becomes smaller. W will change, and the current will change proportionally. A broken line indicates a semiconductor edge in the design.

As described above, due to the misalignment of the semiconductor to the source electrode and the drain electrode and the pattern width variation, there is a problem that the channel width varies and the current varies. The change (variation) in current requires a large safety factor (= design current value / required current value) for a liquid crystal display, an electronic paper transistor, and an organic EL scanning transistor, that is, an excessive transistor is provided. . In addition, an organic EL drive transistor causes luminance variations, which deteriorates image quality.

The present invention has been made in view of the state of the related art, and it is an object of the present invention to provide a thin film transistor and a method of manufacturing the same that are less affected by misalignment of semiconductor formation with respect to a source electrode and a drain electrode and variations in pattern width. .

In order to solve the above problems, a first invention includes a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping the gate electrode in plan view on an insulating substrate. A thin film transistor having a semiconductor pattern having a region in the gap, the gap having a first region having a constant interval and a second region having a gradually increasing interval. The thin film transistor is characterized in that the semiconductor pattern has a shape including an entire region having a constant interval and a part of a region in which the interval gradually increases.

A second invention is a matrix-like thin film transistor in which the gate electrode is connected to a gate wiring and the source electrode is connected to a source wiring in the first invention, and the semiconductor pattern is connected to the source wiring. A thin film transistor having a uniform stripe shape along a plurality of thin film transistor semiconductors connected to each other.

According to a third invention, a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping with the gate electrode in plan view are sequentially stacked on an insulating substrate. A thin film transistor having a semiconductor pattern having a region in the gap, wherein the gap has a first region having a constant interval and a second region having a gradually increasing interval, and the semiconductor pattern has the first pattern. The thin film transistor is formed in one region and not necessarily formed in the second region.

A fourth invention is a matrix-like thin film transistor in which the gate electrode is connected to a gate wiring and the source electrode is connected to a source wiring in the third invention, and the semiconductor pattern is connected to the source wiring. The thin film transistor is characterized by a stripe shape extending along a plurality of thin film transistor semiconductors.

According to a fifth aspect of the present invention, a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping with the gate electrode in plan view are sequentially stacked on an insulating substrate. A method of manufacturing a thin film transistor including at least a step and a step of printing a semiconductor pattern having a region in the gap, wherein the gap includes a first region having a constant interval and a second region having a gradually increasing interval. And the semiconductor pattern is printed so as to include the entire first region and a part of the second region.

The sixth invention is the method of manufacturing a thin film transistor according to the fifth invention, wherein the printed pattern of the semiconductor pattern is a uniform width stripe shape along the source wiring.

A seventh invention is the fifth or sixth invention, wherein, among the printed patterns of the semiconductor pattern printed so as to include the whole of the first region and a part of the second region, A method of manufacturing a thin film transistor, wherein a semiconductor printed in a second region is absorbed in the first region.

An eighth invention is the thin film transistor according to any one of the fifth to seventh inventions, wherein an overlap between the gap in the second region and the printed pattern of the semiconductor pattern has an acute angle. It is a manufacturing method.

According to the present invention, it is possible to provide a thin film transistor that is less affected by misalignment of the semiconductor with respect to the source electrode / drain electrode and variations in pattern width, and a method for manufacturing the same.

FIG. 1 shows an embodiment of the present invention and is a plan view showing a first configuration example of a thin film transistor. FIG. 2 shows an embodiment of the present invention and is a plan view showing a second configuration example of the thin film transistor. FIG. 3A shows an embodiment of the present invention, and is a diagram for first explaining the variation reducing effect. FIG. 3B shows the embodiment of the present invention, and is a diagram for explaining the variation reduction effect second. FIG. 4A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG. FIG. 4B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 4C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 4D is a plan view showing a fourth step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 4E is a plan view showing a fifth step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 4F is a plan view showing a sixth step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 5 shows an embodiment of the present invention and is a plan view showing an example of a thin film transistor. FIG. 6A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG. FIG. 6B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 6C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor in FIG. 5. FIG. 7 shows an embodiment of the present invention and is a plan view showing a third configuration example of the thin film transistor. FIG. 8 shows an embodiment of the present invention and is a plan view showing a fourth configuration example of the thin film transistor. FIG. 9A shows an embodiment of the present invention and is a plan view for first explaining the semiconductor flow effect. FIG. 9B shows an embodiment of the present invention and is a plan view for second explanation of the semiconductor flow effect. FIG. 10A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG. FIG. 10B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 10C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 10D is a plan view showing a fourth step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 10E is a plan view showing a fifth step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 10F is a plan view showing a sixth step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 10G is a plan view showing a seventh step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 11 shows an embodiment of the present invention and is a plan view showing an example of a thin film transistor. FIG. 12A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG. 12B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 12C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor of FIG. 12D is a plan view showing a fourth step in the example of the method for manufacturing the thin film transistor of FIG. FIG. 13 shows a conventional technique and is a plan view showing a configuration example of a thin film transistor. FIG. 14A shows the prior art and is a plan view showing a first pattern design example of a thin film transistor. 14B is a plan view showing a first pattern shift in the pattern design of FIG. 14A. FIG. 14C is a plan view showing a second pattern shift in the pattern design of FIG. 14A. FIG. 15A shows the prior art and is a plan view showing a second pattern design example of the thin film transistor. FIG. 15B is a plan view showing a first pattern shift in the pattern design of FIG. 15A. FIG. 15C is a plan view showing a second pattern shift in the pattern design of FIG. 15A.

Embodiments of the present invention will be described in detail below with reference to the drawings. In the drawings used below, the scale is not accurately drawn for easy understanding.

[First embodiment]
Examples of the thin film transistor according to the first embodiment of the present invention are shown in plan views in FIGS. As shown in FIGS. 1, 2, and 5, the thin film transistor according to this embodiment includes a gate electrode 2, a gate wiring 2 ′, a capacitor electrode 10, and a capacitor wiring 10 ′ on an insulating substrate 1. A gate insulating film 3 is formed thereon, and connected to the source electrode 4 and the drain electrode 5, the source wiring 4 ′, and the drain electrode 5 having a gap in a region overlapping with the gate electrode 2 when viewed from above. The thin film transistor has a pixel pattern 5 ′ and a semiconductor pattern 6 having a region in the gap between the source electrode 4 and the drain electrode 5. Further, in the thin film transistor, the gap between the source electrode 4 and the drain electrode 5 has a region having a constant interval and a region in which the interval gradually increases, and the semiconductor pattern 6 has a distance from the entire region having a constant interval. The shape includes a part of a gradually increasing region. The region where the interval is constant may be linear as shown in FIG. 5 or may be a polygonal shape having a rounded corner as shown in FIG. 1 or a curved shape having a rounded corner as shown in FIG. Good. Since the insulating substrate 1 extends over the entire lowermost layer in FIGS. 1, 2, and 5, no boundary line is shown, and this also applies to other drawings. Further, the source wiring 4 ′ indicates a portion connecting each source electrode 4 of the thin film transistor and the source driving circuit output, but the source wiring 4 ′ also serves as the source electrode 4 in the drawing, that is, the source wiring 4 Since a part of 'is the source electrode 4, reference numeral 4 ′ is also written on the source electrode 4.

3A and 3B, the effect of the edge of the semiconductor pattern 6 being in a region where the interval gradually increases will be described. When the edge of the semiconductor pattern 6 is in the portion of the constant interval L as in the conventional case (FIG. 3A), if the edge (solid line) of the semiconductor pattern 6 is shifted by Δx from the design position (broken line), the channel width / channel length is Changes by Δx / L. On the other hand, in the present embodiment (FIG. 3B), the channel width / channel length of the portion where the interval gradually increases is W1 / (L1-L) × ln [{(L1-L) / W2 + L} / L], and the semiconductor pattern Is shifted by Δx, the channel width / channel length changes by Δx / {(L1−L) / W1 × W2 + L}, which is the conventional value L / {(L1−L) / W1 × W2 + L}. It is doubled (when L1> L). Here, L is the interval of the constant interval portion, L1 is the interval at the widened point, W1 is the dimension in the x direction corresponding to the taper, and W2 is the design value from the taper start position to the semiconductor edge. For example, when L = 10 μm, L1 = 30 μm, W1 = 20 μm, and W2 = 10 μm, the amount of change in channel width / channel length is half of that in the prior art. Due to this effect, variations in channel width can be suppressed. In FIG. 1 and FIG. 2, channel width variations due to semiconductor printing misalignment can be reduced. In FIG. 5, it is possible to reduce channel width variations due to semiconductor print pattern width variations. In addition, although the above-mentioned formula is a case where a taper spreads linearly, there is a similar effect even if the taper is not linear, and the present invention is not limited to a linear taper.

4A to 4F and FIGS. 6A to 6C, the method of manufacturing the thin film transistor according to the present embodiment includes the step of forming the gate electrode 2 on the insulating substrate 1, and the gate insulating film 3 thereon. Forming a source electrode 4 and a drain electrode 5 having a gap in a region overlapping the gate electrode 2 when viewed from above, and having a region in the gap between the source electrode 4 and the drain electrode 5 And a step of printing the semiconductor pattern 6 on the thin film transistor, wherein the gap between the source electrode 4 and the drain electrode 5 has a constant interval region and a gradually increasing region. A method of manufacturing a thin film transistor, wherein the semiconductor pattern 6 is printed so as to include an entire region having a constant interval and a part of a region in which the interval gradually increases.

The insulating substrate 1 may be a rigid substrate such as a glass substrate, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), polyetherimide (PEI), polyethersulfone (PES), It may be flexible.

A gate electrode 2 is formed thereon (FIGS. 4A and 6A). Usually, the gate electrode 2 is connected to the gate wiring 2 '. Further, the capacitor electrode 10 may be provided in the same layer and connected to the capacitor wiring 10 ′. As the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′, a metal such as Al, Ag, Cu, Cr, Ni, Mo, Au, and Pt, a conductive oxide such as ITO, carbon, A conductive polymer or the like can be used. As a manufacturing method, ink may be printed and baked, or may be formed by photolithography, etching, and resist peeling after film formation on the entire surface. Alternatively, it may be formed by resist printing / etching / resist stripping after film formation on the entire surface.

Next, the gate insulating film 3 is formed as shown by the shaded pattern in FIGS. 4A and 6A. As the gate insulating film 3, an inorganic material such as SiO ₂ , SiON, or SiN, or an organic material such as polyvinylphenol (PVP) or epoxy can be used. As a manufacturing method, it can be obtained by vacuum film formation such as sputtering or CVD, or coating and baking of a solution.

Further, a source electrode 4 and a drain electrode 5 are formed (FIGS. 4B and 6B). Here, the source electrode 4 and the drain electrode 5 have a gap in a region overlapping the gate electrode 2 when viewed from above, and the gap has a region having a constant interval and a region in which the interval gradually increases. Note that the source electrode 4 is normally connected to the source wiring 4 ′, and the drain electrode 5 is usually connected to the pixel electrode 5 ′. As the source electrode 4 and the drain electrode 5, metals such as Ag, Cu, Cr, Ni, Mo, Au, Pt, and Al, conductive oxides such as ITO, carbon, conductive polymers, and the like can be used. . As a manufacturing method, it may be formed by photolithography, etching, or resist peeling after film formation on the entire surface, but it is desirable to obtain it by printing and baking ink. As the printing method, screen printing, gravure printing, flexographic printing, offset printing and the like are suitable. In particular, gravure printing, flexographic printing, and offset printing can form a pattern of 20 μm or less with good reproducibility.

Then, the semiconductor pattern 6 is formed on the substrate in the state shown in FIG. 4B or 6B. At this time, the semiconductor printed pattern 6 ′ immediately after printing is formed so that the semiconductor pattern 6 includes the entire region having the constant interval and a part of the region in which the interval gradually increases (FIG. 4C, FIG. 6C). The semiconductor pattern 6 may be independent for each transistor or may have a stripe shape connected in a direction parallel to the source wiring 4 ′. Examples of the semiconductor pattern 6 include organic semiconductors such as polythiophene, acene, and allylamine, and oxidation such as In ₂ O ₃ , Ga ₂ O ₃ , ZnO, SnO ₂ , InGaZnO, InGaSnO, and InSnZnO. A physical semiconductor can be used. As the production method, a method of printing and baking the solution by inkjet, dispenser, flexographic printing or the like is suitable.

It should be noted that the semiconductor print pattern 6 'is preferably a simple shape. This is because printing with a simpler shape becomes easier. The most preferred is a uniform stripe shape parallel to the source wiring 4 ′, in which TFT semiconductors arranged in the vertical direction are connected. In this case, the vertical misalignment does not affect the characteristics. Next, a shape in which a rectangle is arranged in each TFT is desirable. In this case, if the vertical misalignment is small, the characteristics are not affected.

By applying appropriate waveforms to the gate wiring 2 ′ and source wiring 4 ′ of the TFT thus fabricated, the potential of the pixel electrode 5 ′ can be controlled, and electronic paper or the like can be displayed.

In some cases, a sealing layer 7 (FIG. 4D) that further covers the semiconductor pattern 6, an interlayer insulating film 8 having an opening A on the pixel electrode 5 ′ (shown with a pattern in FIG. 4E), and through the opening A An upper pixel electrode 9 (FIG. 4F) connected to the pixel electrode 5 ′ can also be provided. When the semiconductor pattern 6 is a stripe, the sealing layer 7 is also preferably a stripe. Further, the semiconductor pattern 6 may be independent and the sealing layer 7 may be a stripe. As the sealing layer 7, an organic material such as a fluororesin, an inorganic material such as SiO ₂ , SiN, or SiON, or a mixture or laminate thereof can be used. As a manufacturing method, a method of photolithography, etching, and resist removal after film formation on the entire surface is possible, but a method of printing and baking the solution by a method such as screen printing is more preferable. The interlayer insulating film 8 is preferably an organic insulating film such as epoxy, and the upper pixel electrode 9 is preferably Ag paste or the like, and any of them may be printed and baked by a method such as screen printing. When the interlayer insulating film 8 and the upper pixel electrode 9 are provided, the potential of the upper pixel electrode 9 can be controlled by applying appropriate waveforms to the gate wiring 2 ′ and the source wiring 4 ′, and display such as electronic paper can be performed. It becomes possible.

[Second Embodiment]
Examples of thin film transistors according to the second embodiment of the present invention are shown in plan views in FIGS. As shown in FIGS. 7, 8, and 11, the thin film transistor according to this embodiment includes a gate electrode 2, a gate wiring 2 ′, a capacitor electrode 10, and a capacitor wiring 10 ′ on an insulating substrate 1. A gate insulating film 3 is provided thereon, and a source electrode 4 and a drain electrode 5, a source wiring 4 ′, and a pixel electrode 5 ′ having a gap in a region overlapping the gate electrode 2 when viewed from above are provided. The semiconductor pattern 6 has a region in the gap between the source electrode 4 and the drain electrode 5. In the thin film transistor, the gap between the source electrode 4 and the drain electrode 5 includes a region having a constant interval and a region in which the interval gradually increases. The semiconductor pattern 6 is formed in a region where the interval is constant, and is not formed in a region where the interval gradually increases. The region where the interval is constant may be linear as shown in FIG. 11, may be a polygonal shape having a rounded corner as shown in FIG. 7, or may be a curved shape having a rounded corner as shown in FIG. Good.

10A to 10G and 12A to 12D, the thin film transistor manufacturing method according to the present embodiment includes a step of forming a gate electrode 2 on an insulating substrate 1, and a gate insulating film 3 thereon. Forming a source electrode 4 and a drain electrode 5 having a gap in a region overlapping the gate electrode 2 when viewed from above, and having a region in the gap between the source electrode 4 and the drain electrode 5 And a step of printing the semiconductor pattern 6 on the thin film transistor, wherein the gap between the source electrode 4 and the drain electrode 5 has a constant interval region and a gradually increasing region. A method of manufacturing a thin film transistor, wherein the printed pattern 6 ′ of the semiconductor is performed so as to include the entire region having a constant interval and a part of the region having a gradually increasing interval.

In the case of the present embodiment, the semiconductor printed in the region where the interval gradually increases as shown in FIG. 9A in the gap between the source electrode 4 and the drain electrode 5 becomes a region where the interval is constant as shown in FIG. 9B. Absorbed. This is a surface tension effect. Further, when the gap between the source electrode 4 and the drain electrode 5 in the region where the distance between the source electrode 4 and the drain electrode 5 gradually increases and the overlapping portion of the semiconductor print pattern 6 ′ has an acute angle, the semiconductor absorption Can be done smoothly.

The difference from the first embodiment is mainly the viscosity of the semiconductor ink. In the first embodiment, since the viscosity of the ink is large, it is difficult for the ink to flow after printing, and the printed pattern 6 ′ becomes the semiconductor pattern 6 almost as it is. On the other hand, in the second embodiment, since the viscosity of the ink is small, the ink flows easily after printing. Due to the surface tension of the semiconductor ink, the semiconductor ink is more stable in the region where the interval is constant (narrow) than the region where the interval increases gradually. Further, since it is more stable that the semiconductor ink is in the vicinity of the source electrode 4 and the drain electrode 5, when the overlapping portion of the gap between the source electrode 4 and the drain electrode 5 and the semiconductor printed pattern 6 ′ has an acute angle, FIG. As described above, since the direction in which the semiconductor ink is attracted to the source electrode 4 or the drain electrode 5 is close to the direction in which the semiconductor ink is attracted to the constant interval region, the action of being absorbed in the constant interval region can be enhanced.

The insulating substrate 1 may be a rigid substrate such as a glass substrate, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), polyetherimide (PEI), polyethersulfone (PES), It may be flexible.

The gate electrode 2 is formed thereon (FIGS. 10A and 12A). Usually, the gate electrode 2 is connected to the gate wiring 2 '. Further, the capacitor electrode 10 may be provided in the same layer and connected to the capacitor wiring 10 ′. As the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′, a metal such as Al, Ag, Cu, Cr, Ni, Mo, Au, and Pt, a conductive oxide such as ITO, carbon, A conductive polymer or the like can be used. As a manufacturing method, ink may be printed and baked, or may be formed by photolithography, etching, and resist peeling after film formation on the entire surface. Alternatively, it may be formed by resist printing / etching / resist stripping after film formation on the entire surface.

Next, the gate insulating film 3 is formed as shown by the shaded pattern in FIGS. 10A and 12A. As the gate insulating film 3, an inorganic material such as SiO ₂ , SiON, or SiN, or an organic material such as polyvinylphenol (PVP) or epoxy can be used. As a manufacturing method, it can be obtained by vacuum film formation such as sputtering or CVD, or coating and baking of a solution.

Further, the source electrode 4 and the drain electrode 5 are formed (FIGS. 10B and 12B). Here, the source electrode 4 and the drain electrode 5 have a gap in a region overlapping with the gate electrode 2 when viewed from above, and the gap has a region having a constant interval and a region in which the interval gradually increases. Note that the source electrode 4 is normally connected to the source wiring 4 ′, and the drain electrode 5 is usually connected to the pixel electrode 5 ′. As the source electrode 4 and the drain electrode 5, metals such as Ag, Cu, Cr, Ni, Mo, Au, Pt, and Al, conductive oxides such as ITO, carbon, conductive polymers, and the like can be used. . As a manufacturing method, it may be formed by photolithography, etching, or resist peeling after film formation on the entire surface, but it is desirable to obtain it by printing and baking ink. As the printing method, screen printing, gravure printing, flexographic printing, offset printing and the like are suitable. In particular, gravure printing, flexographic printing, and offset printing can form a pattern of 20 μm or less with good reproducibility.

Then, a semiconductor printed pattern 6 ′ is formed so as to include the entire region having the constant interval and a part of the region in which the interval gradually increases (FIGS. 10C and 12C). As described above, the printed pattern 6 ′ is absorbed in the region where the distance between the source electrode 4 and the drain electrode 5 is constant (FIGS. 10D and 12D). Examples of the semiconductor pattern 6 include organic semiconductors such as polythiophene, acene, and allylamine, and oxidation such as In ₂ O ₃ , Ga ₂ O ₃ , ZnO, SnO ₂ , InGaZnO, InGaSnO, and InSnZnO. A physical semiconductor can be used. As the production method, a method of printing and baking the solution by inkjet, dispenser, flexographic printing or the like is suitable.

It should be noted that the semiconductor print pattern 6 'is preferably a simple shape. This is because printing with a simpler shape becomes easier. The most preferred is a uniform stripe shape parallel to the source wiring 4 ′, in which TFT semiconductors arranged in the vertical direction are connected. In this case, the vertical misalignment does not affect the characteristics. Next, a shape in which a rectangle is arranged in each TFT is desirable. In this case, if the vertical misalignment is small, the characteristics are not affected.

By applying appropriate waveforms to the gate wiring 2 ′ and source wiring 4 ′ of the TFT thus fabricated, the potential of the pixel electrode 5 ′ can be controlled, and electronic paper or the like can be displayed.

In some cases, the sealing layer 7 (FIG. 10E) further covering the semiconductor pattern 6, the interlayer insulating film 8 (FIG. 10F) having the opening A on the pixel electrode 5 ′, and the pixel electrode 5 ′ are connected through the opening A. It is also possible to provide the upper pixel electrode 9 (FIG. 10G). When the semiconductor pattern 6 is a stripe, the sealing layer 7 is also preferably a stripe. Further, the semiconductor pattern 6 may be independent and the sealing layer 7 may be a stripe. As the sealing layer 7, an organic material such as a fluororesin, an inorganic material such as SiO ₂ , SiN, or SiON, or a mixture or laminate thereof can be used. As a manufacturing method, a method of photolithography, etching, and resist removal after film formation on the entire surface is possible, but a method of printing and baking the solution by a method such as screen printing is more preferable. The interlayer insulating film 8 is preferably an organic insulating film such as epoxy, and the upper pixel electrode 9 is preferably Ag paste or the like, and any of them may be printed and baked by a method such as screen printing. When the interlayer insulating film 8 and the upper pixel electrode 9 are provided, the potential of the upper pixel electrode 9 can be controlled by applying appropriate waveforms to the gate wiring 2 ′ and the source wiring 4 ′, and display such as electronic paper can be performed. It becomes possible.

(Example 1)
An embodiment of the present invention will be described with reference to FIGS. 4A to 4C. The device shown in FIG. 2 was fabricated by the steps of FIGS. 4A to 4C. First, an Al film having a thickness of 50 nm was formed by vapor deposition on the PEN which is the insulating substrate 1, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching (FIG. 4A). Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C., thereby forming 1 μm of polyvinylphenol as the gate insulating film 3 (FIG. 4A). Furthermore, as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′, a pattern was formed by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 4B). Further, a polythiophene solution (viscosity 100 mPa · s) was flexographically printed and baked at 100 ° C., thereby forming a semiconductor layer 6 (FIG. 4C).

When the current variation of the thin film transistor thus fabricated was examined, it was about half of the variation of Comparative Example 1 described later.

(Example 2)
An embodiment of the present invention will be described with reference to FIGS. 6A to 6C. The device shown in FIG. 5 was fabricated by the steps of FIGS. 6A to 6C. First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 was formed by photolithography and wet etching (FIG. 6A). Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3 (FIG. 6A). Furthermore, as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′, a pattern was formed by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 6B). Further, the polythiophene solution (viscosity 100 mPa · s) was flexographically printed and baked at 100 ° C., thereby forming the semiconductor layer 6 (FIG. 6C).

When the current variation of the thin film transistor thus fabricated was examined, it was about half of the variation of Comparative Example 2 described later.

(Example 3)
An embodiment of the present invention will be described with reference to FIGS. 10A to 10D. The element shown in FIG. 8 was fabricated by the steps of FIGS. 10A to 10D. First, an Al film having a thickness of 50 nm was formed on the PEN as the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching (FIG. 10A). Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3 (FIG. 10A). Further, a pattern was formed as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′ by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 10B). Further, a polythiophene solution (viscosity 10 mPa · s) was flexographically printed and baked at 100 ° C. to form the semiconductor layer 6 (FIGS. 10C to 10D).

When the current variation of the thin film transistor thus fabricated was examined, it was about one third of the variation of Comparative Example 1 described later.

Example 4
An embodiment of the present invention will be described with reference to FIGS. 12A to 12D. The device shown in FIG. 11 was fabricated by the steps of FIGS. 12A to 12C. First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 was formed by photolithography and wet etching (FIG. 12A). Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3 (FIG. 12A). Furthermore, as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′, a pattern was formed by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 12B). Further, a polythiophene solution (viscosity 10 mPa · s) was flexographically printed and baked at 100 ° C. to form the semiconductor layer 6 (FIGS. 12C to 12D).

When the current variation of the thin film transistor thus fabricated was examined, it was about one third of the variation of Comparative Example 2 described later.

(Comparative Example 1)
A comparative example will be described with reference to FIGS. 14A to 14C. Aiming at the device shown in FIG. 14A, it was fabricated by a process similar to that shown in FIGS. 4A to 4C. First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching. Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3. Further, a pattern was formed as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′ by performing reverse printing of Ag ink and baking at 180 ° C. Furthermore, a semiconductor layer 6 was formed by flexographic printing a polythiophene solution (viscosity 100 mPa · s) and firing at 100 ° C.

In the thin film transistor thus fabricated, current variations that were thought to be caused by misalignment of the semiconductor pattern (FIGS. 14B and 14C) occurred.

(Comparative Example 2)
A comparative example will be described with reference to FIGS. 15A to 15C. Aiming at the device shown in FIG. 15A, it was fabricated by a process similar to FIGS. 6A to 6C. First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching. Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3. Further, a pattern was formed as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′ by performing reverse printing of Ag ink and baking at 180 ° C. Furthermore, the semiconductor layer 6 was formed by carrying out flexographic printing of the polythiophene solution (viscosity 10 mPa * s), and baking at 100 degreeC.

In the thin film transistor thus fabricated, current variations that appear to be due to variations in the semiconductor pattern width (FIGS. 15B and 15C) occurred.

As can be understood from the above description, the present invention has the following effects. For example, the gap between the source electrode and the drain electrode includes a first region having a constant interval and a second region in which the interval gradually increases. The entire first region and the second region By forming the semiconductor pattern so as to include a part, the influence of the misalignment on the channel width can be reduced. The other is that the semiconductor printed in the second region in the gap between the source electrode and the drain electrode is absorbed by the first region, so that the channel width is substantially determined in the first region. As a result, the effects of misalignment and pattern width variations can be reduced. Since the overlap between the gap between the source electrode and the drain electrode in the second region and the semiconductor print pattern has an acute angle, the movement of the semiconductor becomes smoother.

The present invention can be applied to thin film transistors such as liquid crystal display devices, electronic paper, and organic EL display devices.

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Gate electrode 2 '... Gate wiring 3 ... Gate insulating film 4 ... Source electrode 4' ... Source wiring 5 ... Drain electrode 5 '... Pixel electrode 6 ... Semiconductor pattern 6' ... Semiconductor printed pattern 7 ... Sealing Stop layer 8 ... Interlayer insulating film 9 ... Upper pixel electrode 10 ... Capacitor electrode 10 '... Capacitor wiring

Claims (9)

A gate electrode, a gate insulating film, and a source electrode and a drain electrode having a mutual gap in a region overlapping with the gate electrode in plan view are stacked in order on an insulating substrate, and the region in the gap A thin film transistor having a semiconductor pattern comprising:
The gap includes a first region having a constant interval and a second region having a gradually increasing interval, and the semiconductor pattern includes the entire region having a constant interval and a part of the region having a gradually increasing interval. A thin film transistor having a shape. A thin film transistor in the form of a matrix in which the gate electrode is connected to a gate wiring and the source electrode is connected to the source wiring, wherein the semiconductor pattern has a uniform width stripe shape along the source wiring, and a plurality of thin film transistors 2. The thin film transistor according to claim 1, wherein the semiconductors are connected to each other. A gate electrode, a gate insulating film, and a source electrode and a drain electrode having a mutual gap in a region overlapping with the gate electrode in plan view are stacked in order on an insulating substrate, and the region in the gap A thin film transistor having a semiconductor pattern comprising:
The gap includes a first region having a constant interval and a second region in which the interval gradually increases, and the semiconductor pattern is formed in the first region. A thin film transistor which is not necessarily formed. A thin film transistor having a matrix shape in which the gate electrode is connected to a gate wiring and the source electrode is connected to the source wiring, wherein the semiconductor pattern has a stripe shape along the source wiring, and a plurality of thin film transistor semiconductors The thin film transistor according to claim 3, wherein the thin film transistors are connected. Forming a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping with the gate electrode in plan view on the insulating substrate so as to be sequentially stacked; A method of manufacturing a thin film transistor having at least a step of printing a semiconductor pattern having a region,
The gap includes a first region having a constant interval and a second region having a gradually increasing interval, and printing of the semiconductor pattern is performed between the entire first region and a part of the second region. A method for producing a thin film transistor, characterized by comprising: 6. The method of manufacturing a thin film transistor according to claim 5, wherein the printed pattern of the semiconductor pattern has a uniform width stripe shape along the source wiring. Of the printed pattern of the semiconductor pattern printed so as to include the entire first region and a part of the second region, the semiconductor printed in the second region is the first region. 7. The method for manufacturing a thin film transistor according to claim 5, wherein the thin film transistor is absorbed in the region. 7. The method of manufacturing a thin film transistor according to claim 5, wherein an overlap between the gap in the second region and the printed pattern of the semiconductor pattern has an acute angle. The method of manufacturing a thin film transistor according to claim 7, wherein the gap between the second region and the printed pattern of the semiconductor pattern has an acute angle.

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