WO2014049968A1 - Thin-film transistor and method for producing same - Google Patents

Thin-film transistor and method for producing same Download PDF

Info

Publication number
WO2014049968A1
WO2014049968A1 PCT/JP2013/005126 JP2013005126W WO2014049968A1 WO 2014049968 A1 WO2014049968 A1 WO 2014049968A1 JP 2013005126 W JP2013005126 W JP 2013005126W WO 2014049968 A1 WO2014049968 A1 WO 2014049968A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
thin film
film transistor
electrode
pattern
Prior art date
Application number
PCT/JP2013/005126
Other languages
French (fr)
Japanese (ja)
Inventor
守 石▲崎▼
亮平 松原
Original Assignee
凸版印刷株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 凸版印刷株式会社 filed Critical 凸版印刷株式会社
Publication of WO2014049968A1 publication Critical patent/WO2014049968A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate

Definitions

  • the present invention relates to a thin film transistor and a manufacturing method thereof, and particularly relates to a thin film transistor suitable for a flexible substrate or a printing method and a manufacturing method thereof.
  • amorphous silicon (a-Si) and polysilicon (poly-Si) thin film transistors are manufactured on a glass substrate.
  • Non-Patent Document 1 amorphous silicon (a-Si) and polysilicon (poly-Si) thin film transistors (Thin Film Transistor: TFT) are manufactured on a glass substrate.
  • the TFT for example, the one shown in FIG. 13 is used (the semiconductor shape is not clearly shown in FIG. 13).
  • the TFT plays a role of a switch.
  • the TFT is turned on by a selection voltage applied to the gate wiring 2 ′, the signal voltage applied to the source wiring 4 ′ is applied to the pixel electrode 5 ′ connected to the drain 5. Write to.
  • the written voltage is held in a storage capacitor constituted by the pixel electrode 5 ′ / gate insulating film 3 / capacitor electrode 10.
  • the gate insulating film 3 is above the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′, and the source electrode 4, the source wiring 4 ′, the drain electrode 5, the pixel electrode 5 ′, and , Located below the semiconductor pattern (not shown).
  • a voltage is applied to the capacitor electrode 10 from the capacitor wiring 10 ′.
  • the names of the source and the drain cannot be determined by the characteristics of the operation. Therefore, for convenience, one is called a source and the other is called a drain, and the names are unified.
  • the one connected to the wiring is called a source
  • the one connected to the pixel electrode is called a drain.
  • TFTs can be produced at a low temperature of 200 ° C. or lower, and expectations for flexible displays using plastic substrates are increasing. In addition to the feature of flexibility, it is also expected to be light, hard to break, and thin. Moreover, an inexpensive and large-area display is expected by forming TFTs by printing.
  • the misalignment becomes larger than when a rigid substrate and a photolithography method are used. This is because the flexible substrate has poor positional accuracy of the substrate itself, and the printing method is due to deterioration of positional accuracy due to movement during printing. Further, when the viscosity of the ink is small, there is a problem that the pattern width of semiconductor printing varies due to the flow after printing.
  • the dimension parameters that most affect the current characteristics of the thin film transistor are the channel length L and the channel width W.
  • a channel is a region in which a current flows in a semiconductor
  • a channel length L is a length in a current direction
  • a channel width W is a width in a direction perpendicular to the current.
  • the channel length L is substantially determined by the distance between the source electrode and the drain electrode, and if the source electrode and the drain electrode are formed by the same printing, there is no influence of misalignment or semiconductor printing.
  • the channel width W is greatly affected by misalignment of the semiconductor formation to the source / drain electrodes and the pattern width. For example, in the case of the pattern design shown in FIGS. 14A to 14C, FIG.
  • FIG. 14A is as designed, but when the semiconductor pattern 6 is shifted to the right as shown in FIG. 14B, W increases, and the semiconductor is shifted to the left as shown in FIG. 14C. And W become smaller.
  • FIG. 15A is as designed, but as the width of the semiconductor pattern 6 increases as shown in FIG. 15B, W increases, and as shown in FIG. 15C, the width of the semiconductor pattern 6 increases. As it becomes smaller, W becomes smaller. W will change, and the current will change proportionally.
  • a broken line indicates a semiconductor edge in the design.
  • the present invention has been made in view of the state of the related art, and it is an object of the present invention to provide a thin film transistor and a method of manufacturing the same that are less affected by misalignment of semiconductor formation with respect to a source electrode and a drain electrode and variations in pattern width. .
  • a first invention includes a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping the gate electrode in plan view on an insulating substrate.
  • a thin film transistor having a semiconductor pattern having a region in the gap, the gap having a first region having a constant interval and a second region having a gradually increasing interval.
  • the thin film transistor is characterized in that the semiconductor pattern has a shape including an entire region having a constant interval and a part of a region in which the interval gradually increases.
  • a second invention is a matrix-like thin film transistor in which the gate electrode is connected to a gate wiring and the source electrode is connected to a source wiring in the first invention, and the semiconductor pattern is connected to the source wiring.
  • a thin film transistor having a uniform stripe shape along a plurality of thin film transistor semiconductors connected to each other.
  • a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping with the gate electrode in plan view are sequentially stacked on an insulating substrate.
  • the thin film transistor is formed in one region and not necessarily formed in the second region.
  • a fourth invention is a matrix-like thin film transistor in which the gate electrode is connected to a gate wiring and the source electrode is connected to a source wiring in the third invention, and the semiconductor pattern is connected to the source wiring.
  • the thin film transistor is characterized by a stripe shape extending along a plurality of thin film transistor semiconductors.
  • a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping with the gate electrode in plan view are sequentially stacked on an insulating substrate.
  • a method of manufacturing a thin film transistor including at least a step and a step of printing a semiconductor pattern having a region in the gap, wherein the gap includes a first region having a constant interval and a second region having a gradually increasing interval. And the semiconductor pattern is printed so as to include the entire first region and a part of the second region.
  • the sixth invention is the method of manufacturing a thin film transistor according to the fifth invention, wherein the printed pattern of the semiconductor pattern is a uniform width stripe shape along the source wiring.
  • a seventh invention is the fifth or sixth invention, wherein, among the printed patterns of the semiconductor pattern printed so as to include the whole of the first region and a part of the second region, A method of manufacturing a thin film transistor, wherein a semiconductor printed in a second region is absorbed in the first region.
  • An eighth invention is the thin film transistor according to any one of the fifth to seventh inventions, wherein an overlap between the gap in the second region and the printed pattern of the semiconductor pattern has an acute angle. It is a manufacturing method.
  • the present invention it is possible to provide a thin film transistor that is less affected by misalignment of the semiconductor with respect to the source electrode / drain electrode and variations in pattern width, and a method for manufacturing the same.
  • FIG. 1 shows an embodiment of the present invention and is a plan view showing a first configuration example of a thin film transistor.
  • FIG. 2 shows an embodiment of the present invention and is a plan view showing a second configuration example of the thin film transistor.
  • FIG. 3A shows an embodiment of the present invention, and is a diagram for first explaining the variation reducing effect.
  • FIG. 3B shows the embodiment of the present invention, and is a diagram for explaining the variation reduction effect second.
  • FIG. 4A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG.
  • FIG. 4B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 4A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG.
  • FIG. 4B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 4A is a plan view showing a
  • FIG. 4C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 4D is a plan view showing a fourth step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 4E is a plan view showing a fifth step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 4F is a plan view showing a sixth step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 5 shows an embodiment of the present invention and is a plan view showing an example of a thin film transistor.
  • FIG. 6A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG. FIG.
  • FIG. 6B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 6C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor in FIG. 5.
  • FIG. 7 shows an embodiment of the present invention and is a plan view showing a third configuration example of the thin film transistor.
  • FIG. 8 shows an embodiment of the present invention and is a plan view showing a fourth configuration example of the thin film transistor.
  • FIG. 9A shows an embodiment of the present invention and is a plan view for first explaining the semiconductor flow effect.
  • FIG. 9B shows an embodiment of the present invention and is a plan view for second explanation of the semiconductor flow effect.
  • FIG. 10A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG.
  • FIG. 10B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 10C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 10D is a plan view showing a fourth step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 10E is a plan view showing a fifth step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 10F is a plan view showing a sixth step in the example of the method for manufacturing the thin film transistor of FIG. FIG.
  • FIG. 10G is a plan view showing a seventh step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 11 shows an embodiment of the present invention and is a plan view showing an example of a thin film transistor.
  • FIG. 12A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG. 12B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 12C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor of FIG. 12D is a plan view showing a fourth step in the example of the method for manufacturing the thin film transistor of FIG.
  • FIG. 13 shows a conventional technique and is a plan view showing a configuration example of a thin film transistor.
  • FIG. 14A shows the prior art and is a plan view showing a first pattern design example of a thin film transistor.
  • 14B is a plan view showing a first pattern shift in the pattern design of FIG. 14A.
  • FIG. 14C is a plan view showing a second pattern shift in the pattern design of FIG. 14A.
  • FIG. 15A shows the prior art and is a plan view showing a second pattern design example of the thin film transistor.
  • FIG. 15B is a plan view showing a first pattern shift in the pattern design of FIG. 15A.
  • FIG. 15C is a plan view showing a second pattern shift in the pattern design of FIG. 15A.
  • the thin film transistor according to this embodiment includes a gate electrode 2, a gate wiring 2 ′, a capacitor electrode 10, and a capacitor wiring 10 ′ on an insulating substrate 1.
  • a gate insulating film 3 is formed thereon, and connected to the source electrode 4 and the drain electrode 5, the source wiring 4 ′, and the drain electrode 5 having a gap in a region overlapping with the gate electrode 2 when viewed from above.
  • the thin film transistor has a pixel pattern 5 ′ and a semiconductor pattern 6 having a region in the gap between the source electrode 4 and the drain electrode 5.
  • the gap between the source electrode 4 and the drain electrode 5 has a region having a constant interval and a region in which the interval gradually increases, and the semiconductor pattern 6 has a distance from the entire region having a constant interval.
  • the shape includes a part of a gradually increasing region.
  • the region where the interval is constant may be linear as shown in FIG. 5 or may be a polygonal shape having a rounded corner as shown in FIG. 1 or a curved shape having a rounded corner as shown in FIG. Good. Since the insulating substrate 1 extends over the entire lowermost layer in FIGS. 1, 2, and 5, no boundary line is shown, and this also applies to other drawings.
  • the source wiring 4 ′ indicates a portion connecting each source electrode 4 of the thin film transistor and the source driving circuit output, but the source wiring 4 ′ also serves as the source electrode 4 in the drawing, that is, the source wiring 4 Since a part of 'is the source electrode 4, reference numeral 4 ′ is also written on the source electrode 4.
  • the channel width / channel length of the portion where the interval gradually increases is W1 / (L1-L) ⁇ ln [ ⁇ (L1-L) / W2 + L ⁇ / L], and the semiconductor pattern Is shifted by ⁇ x, the channel width / channel length changes by ⁇ x / ⁇ (L1 ⁇ L) / W1 ⁇ W2 + L ⁇ , which is the conventional value L / ⁇ (L1 ⁇ L) / W1 ⁇ W2 + L ⁇ . It is doubled (when L1> L).
  • L is the interval of the constant interval portion
  • L1 is the interval at the widened point
  • W1 is the dimension in the x direction corresponding to the taper
  • W2 is the design value from the taper start position to the semiconductor edge.
  • L 10 ⁇ m
  • L1 30 ⁇ m
  • W1 20 ⁇ m
  • W2 10 ⁇ m
  • the amount of change in channel width / channel length is half of that in the prior art. Due to this effect, variations in channel width can be suppressed.
  • FIG. 1 and FIG. 2 channel width variations due to semiconductor printing misalignment can be reduced.
  • FIG. 5 it is possible to reduce channel width variations due to semiconductor print pattern width variations.
  • the above-mentioned formula is a case where a taper spreads linearly, there is a similar effect even if the taper is not linear, and the present invention is not limited to a linear taper.
  • the method of manufacturing the thin film transistor according to the present embodiment includes the step of forming the gate electrode 2 on the insulating substrate 1, and the gate insulating film 3 thereon. Forming a source electrode 4 and a drain electrode 5 having a gap in a region overlapping the gate electrode 2 when viewed from above, and having a region in the gap between the source electrode 4 and the drain electrode 5 And a step of printing the semiconductor pattern 6 on the thin film transistor, wherein the gap between the source electrode 4 and the drain electrode 5 has a constant interval region and a gradually increasing region.
  • the insulating substrate 1 may be a rigid substrate such as a glass substrate, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), polyetherimide (PEI), polyethersulfone (PES), It may be flexible.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PI polyimide
  • PEI polyetherimide
  • PES polyethersulfone
  • a gate electrode 2 is formed thereon (FIGS. 4A and 6A). Usually, the gate electrode 2 is connected to the gate wiring 2 '. Further, the capacitor electrode 10 may be provided in the same layer and connected to the capacitor wiring 10 ′.
  • a metal such as Al, Ag, Cu, Cr, Ni, Mo, Au, and Pt, a conductive oxide such as ITO, carbon, A conductive polymer or the like can be used.
  • ink may be printed and baked, or may be formed by photolithography, etching, and resist peeling after film formation on the entire surface. Alternatively, it may be formed by resist printing / etching / resist stripping after film formation on the entire surface.
  • the gate insulating film 3 is formed as shown by the shaded pattern in FIGS. 4A and 6A.
  • an inorganic material such as SiO 2 , SiON, or SiN, or an organic material such as polyvinylphenol (PVP) or epoxy can be used.
  • PVP polyvinylphenol
  • a source electrode 4 and a drain electrode 5 are formed (FIGS. 4B and 6B).
  • the source electrode 4 and the drain electrode 5 have a gap in a region overlapping the gate electrode 2 when viewed from above, and the gap has a region having a constant interval and a region in which the interval gradually increases.
  • the source electrode 4 is normally connected to the source wiring 4 ′, and the drain electrode 5 is usually connected to the pixel electrode 5 ′.
  • metals such as Ag, Cu, Cr, Ni, Mo, Au, Pt, and Al, conductive oxides such as ITO, carbon, conductive polymers, and the like can be used. .
  • a manufacturing method it may be formed by photolithography, etching, or resist peeling after film formation on the entire surface, but it is desirable to obtain it by printing and baking ink.
  • the printing method screen printing, gravure printing, flexographic printing, offset printing and the like are suitable. In particular, gravure printing, flexographic printing, and offset printing can form a pattern of 20 ⁇ m or less with good reproducibility.
  • the semiconductor pattern 6 is formed on the substrate in the state shown in FIG. 4B or 6B.
  • the semiconductor printed pattern 6 ′ immediately after printing is formed so that the semiconductor pattern 6 includes the entire region having the constant interval and a part of the region in which the interval gradually increases (FIG. 4C, FIG. 6C).
  • the semiconductor pattern 6 may be independent for each transistor or may have a stripe shape connected in a direction parallel to the source wiring 4 ′.
  • Examples of the semiconductor pattern 6 include organic semiconductors such as polythiophene, acene, and allylamine, and oxidation such as In 2 O 3 , Ga 2 O 3 , ZnO, SnO 2 , InGaZnO, InGaSnO, and InSnZnO.
  • a physical semiconductor can be used.
  • As the production method a method of printing and baking the solution by inkjet, dispenser, flexographic printing or the like is suitable.
  • the semiconductor print pattern 6 ' is preferably a simple shape. This is because printing with a simpler shape becomes easier.
  • the most preferred is a uniform stripe shape parallel to the source wiring 4 ′, in which TFT semiconductors arranged in the vertical direction are connected. In this case, the vertical misalignment does not affect the characteristics.
  • a shape in which a rectangle is arranged in each TFT is desirable. In this case, if the vertical misalignment is small, the characteristics are not affected.
  • the potential of the pixel electrode 5 ′ can be controlled, and electronic paper or the like can be displayed.
  • a sealing layer 7 (FIG. 4D) that further covers the semiconductor pattern 6, an interlayer insulating film 8 having an opening A on the pixel electrode 5 ′ (shown with a pattern in FIG. 4E), and through the opening A
  • An upper pixel electrode 9 (FIG. 4F) connected to the pixel electrode 5 ′
  • the sealing layer 7 is also preferably a stripe.
  • the semiconductor pattern 6 may be independent and the sealing layer 7 may be a stripe.
  • an organic material such as a fluororesin, an inorganic material such as SiO 2 , SiN, or SiON, or a mixture or laminate thereof can be used.
  • the interlayer insulating film 8 is preferably an organic insulating film such as epoxy
  • the upper pixel electrode 9 is preferably Ag paste or the like, and any of them may be printed and baked by a method such as screen printing.
  • the potential of the upper pixel electrode 9 can be controlled by applying appropriate waveforms to the gate wiring 2 ′ and the source wiring 4 ′, and display such as electronic paper can be performed. It becomes possible.
  • the thin film transistor according to this embodiment includes a gate electrode 2, a gate wiring 2 ′, a capacitor electrode 10, and a capacitor wiring 10 ′ on an insulating substrate 1.
  • a gate insulating film 3 is provided thereon, and a source electrode 4 and a drain electrode 5, a source wiring 4 ′, and a pixel electrode 5 ′ having a gap in a region overlapping the gate electrode 2 when viewed from above are provided.
  • the semiconductor pattern 6 has a region in the gap between the source electrode 4 and the drain electrode 5.
  • the gap between the source electrode 4 and the drain electrode 5 includes a region having a constant interval and a region in which the interval gradually increases.
  • the semiconductor pattern 6 is formed in a region where the interval is constant, and is not formed in a region where the interval gradually increases.
  • the region where the interval is constant may be linear as shown in FIG. 11, may be a polygonal shape having a rounded corner as shown in FIG. 7, or may be a curved shape having a rounded corner as shown in FIG. Good.
  • the thin film transistor manufacturing method includes a step of forming a gate electrode 2 on an insulating substrate 1, and a gate insulating film 3 thereon. Forming a source electrode 4 and a drain electrode 5 having a gap in a region overlapping the gate electrode 2 when viewed from above, and having a region in the gap between the source electrode 4 and the drain electrode 5 And a step of printing the semiconductor pattern 6 on the thin film transistor, wherein the gap between the source electrode 4 and the drain electrode 5 has a constant interval region and a gradually increasing region.
  • the semiconductor printed in the region where the interval gradually increases as shown in FIG. 9A in the gap between the source electrode 4 and the drain electrode 5 becomes a region where the interval is constant as shown in FIG. 9B. Absorbed. This is a surface tension effect. Further, when the gap between the source electrode 4 and the drain electrode 5 in the region where the distance between the source electrode 4 and the drain electrode 5 gradually increases and the overlapping portion of the semiconductor print pattern 6 ′ has an acute angle, the semiconductor absorption Can be done smoothly.
  • the difference from the first embodiment is mainly the viscosity of the semiconductor ink.
  • the viscosity of the ink since the viscosity of the ink is large, it is difficult for the ink to flow after printing, and the printed pattern 6 ′ becomes the semiconductor pattern 6 almost as it is.
  • the second embodiment since the viscosity of the ink is small, the ink flows easily after printing. Due to the surface tension of the semiconductor ink, the semiconductor ink is more stable in the region where the interval is constant (narrow) than the region where the interval increases gradually.
  • FIG. 1 since it is more stable that the semiconductor ink is in the vicinity of the source electrode 4 and the drain electrode 5, when the overlapping portion of the gap between the source electrode 4 and the drain electrode 5 and the semiconductor printed pattern 6 ′ has an acute angle, FIG. As described above, since the direction in which the semiconductor ink is attracted to the source electrode 4 or the drain electrode 5 is close to the direction in which the semiconductor ink is attracted to the constant interval region, the action of being absorbed in the constant interval region can be enhanced.
  • the insulating substrate 1 may be a rigid substrate such as a glass substrate, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), polyetherimide (PEI), polyethersulfone (PES), It may be flexible.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PI polyimide
  • PEI polyetherimide
  • PES polyethersulfone
  • the gate electrode 2 is formed thereon (FIGS. 10A and 12A). Usually, the gate electrode 2 is connected to the gate wiring 2 '. Further, the capacitor electrode 10 may be provided in the same layer and connected to the capacitor wiring 10 ′.
  • a metal such as Al, Ag, Cu, Cr, Ni, Mo, Au, and Pt, a conductive oxide such as ITO, carbon, A conductive polymer or the like can be used.
  • ink may be printed and baked, or may be formed by photolithography, etching, and resist peeling after film formation on the entire surface. Alternatively, it may be formed by resist printing / etching / resist stripping after film formation on the entire surface.
  • the gate insulating film 3 is formed as shown by the shaded pattern in FIGS. 10A and 12A.
  • an inorganic material such as SiO 2 , SiON, or SiN, or an organic material such as polyvinylphenol (PVP) or epoxy can be used.
  • PVP polyvinylphenol
  • the source electrode 4 and the drain electrode 5 are formed (FIGS. 10B and 12B).
  • the source electrode 4 and the drain electrode 5 have a gap in a region overlapping with the gate electrode 2 when viewed from above, and the gap has a region having a constant interval and a region in which the interval gradually increases.
  • the source electrode 4 is normally connected to the source wiring 4 ′, and the drain electrode 5 is usually connected to the pixel electrode 5 ′.
  • metals such as Ag, Cu, Cr, Ni, Mo, Au, Pt, and Al, conductive oxides such as ITO, carbon, conductive polymers, and the like can be used. .
  • a manufacturing method it may be formed by photolithography, etching, or resist peeling after film formation on the entire surface, but it is desirable to obtain it by printing and baking ink.
  • the printing method screen printing, gravure printing, flexographic printing, offset printing and the like are suitable. In particular, gravure printing, flexographic printing, and offset printing can form a pattern of 20 ⁇ m or less with good reproducibility.
  • a semiconductor printed pattern 6 ′ is formed so as to include the entire region having the constant interval and a part of the region in which the interval gradually increases (FIGS. 10C and 12C).
  • the printed pattern 6 ′ is absorbed in the region where the distance between the source electrode 4 and the drain electrode 5 is constant (FIGS. 10D and 12D).
  • the semiconductor pattern 6 include organic semiconductors such as polythiophene, acene, and allylamine, and oxidation such as In 2 O 3 , Ga 2 O 3 , ZnO, SnO 2 , InGaZnO, InGaSnO, and InSnZnO.
  • a physical semiconductor can be used.
  • a method of printing and baking the solution by inkjet, dispenser, flexographic printing or the like is suitable.
  • the semiconductor print pattern 6 ' is preferably a simple shape. This is because printing with a simpler shape becomes easier.
  • the most preferred is a uniform stripe shape parallel to the source wiring 4 ′, in which TFT semiconductors arranged in the vertical direction are connected. In this case, the vertical misalignment does not affect the characteristics.
  • a shape in which a rectangle is arranged in each TFT is desirable. In this case, if the vertical misalignment is small, the characteristics are not affected.
  • the potential of the pixel electrode 5 ′ can be controlled, and electronic paper or the like can be displayed.
  • the sealing layer 7 (FIG. 10E) further covering the semiconductor pattern 6, the interlayer insulating film 8 (FIG. 10F) having the opening A on the pixel electrode 5 ′, and the pixel electrode 5 ′ are connected through the opening A. It is also possible to provide the upper pixel electrode 9 (FIG. 10G).
  • the sealing layer 7 is also preferably a stripe. Further, the semiconductor pattern 6 may be independent and the sealing layer 7 may be a stripe.
  • an organic material such as a fluororesin, an inorganic material such as SiO 2 , SiN, or SiON, or a mixture or laminate thereof can be used.
  • the interlayer insulating film 8 is preferably an organic insulating film such as epoxy
  • the upper pixel electrode 9 is preferably Ag paste or the like, and any of them may be printed and baked by a method such as screen printing.
  • the potential of the upper pixel electrode 9 can be controlled by applying appropriate waveforms to the gate wiring 2 ′ and the source wiring 4 ′, and display such as electronic paper can be performed. It becomes possible.
  • Example 1 An embodiment of the present invention will be described with reference to FIGS. 4A to 4C.
  • the device shown in FIG. 2 was fabricated by the steps of FIGS. 4A to 4C.
  • a polyvinylphenol solution was spin-coated and baked at 150 ° C., thereby forming 1 ⁇ m of polyvinylphenol as the gate insulating film 3 (FIG. 4A).
  • a pattern was formed by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 4B). Further, a polythiophene solution (viscosity 100 mPa ⁇ s) was flexographically printed and baked at 100 ° C., thereby forming a semiconductor layer 6 (FIG. 4C).
  • Example 2 An embodiment of the present invention will be described with reference to FIGS. 6A to 6C.
  • the device shown in FIG. 5 was fabricated by the steps of FIGS. 6A to 6C.
  • a pattern was formed by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 6B). Further, the polythiophene solution (viscosity 100 mPa ⁇ s) was flexographically printed and baked at 100 ° C., thereby forming the semiconductor layer 6 (FIG. 6C).
  • Example 3 An embodiment of the present invention will be described with reference to FIGS. 10A to 10D.
  • the element shown in FIG. 8 was fabricated by the steps of FIGS. 10A to 10D.
  • a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 ⁇ m of polyvinylphenol as the gate insulating film 3 (FIG. 10A).
  • a pattern was formed as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′ by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 10B). Further, a polythiophene solution (viscosity 10 mPa ⁇ s) was flexographically printed and baked at 100 ° C. to form the semiconductor layer 6 (FIGS. 10C to 10D).
  • Example 4 An embodiment of the present invention will be described with reference to FIGS. 12A to 12D.
  • the device shown in FIG. 11 was fabricated by the steps of FIGS. 12A to 12C.
  • a pattern was formed by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 12B). Further, a polythiophene solution (viscosity 10 mPa ⁇ s) was flexographically printed and baked at 100 ° C. to form the semiconductor layer 6 (FIGS. 12C to 12D).
  • FIGS. 14A to 14C A comparative example will be described with reference to FIGS. 14A to 14C. Aiming at the device shown in FIG. 14A, it was fabricated by a process similar to that shown in FIGS. 4A to 4C. First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching. Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 ⁇ m of polyvinylphenol as the gate insulating film 3.
  • a pattern was formed as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′ by performing reverse printing of Ag ink and baking at 180 ° C. Furthermore, a semiconductor layer 6 was formed by flexographic printing a polythiophene solution (viscosity 100 mPa ⁇ s) and firing at 100 ° C.
  • FIGS. 15A to 15C A comparative example will be described with reference to FIGS. 15A to 15C. Aiming at the device shown in FIG. 15A, it was fabricated by a process similar to FIGS. 6A to 6C. First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching. Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 ⁇ m of polyvinylphenol as the gate insulating film 3.
  • a pattern was formed as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′ by performing reverse printing of Ag ink and baking at 180 ° C. Furthermore, the semiconductor layer 6 was formed by carrying out flexographic printing of the polythiophene solution (viscosity 10 mPa * s), and baking at 100 degreeC.
  • the gap between the source electrode and the drain electrode includes a first region having a constant interval and a second region in which the interval gradually increases.
  • the entire first region and the second region By forming the semiconductor pattern so as to include a part, the influence of the misalignment on the channel width can be reduced.
  • the other is that the semiconductor printed in the second region in the gap between the source electrode and the drain electrode is absorbed by the first region, so that the channel width is substantially determined in the first region.
  • the effects of misalignment and pattern width variations can be reduced. Since the overlap between the gap between the source electrode and the drain electrode in the second region and the semiconductor print pattern has an acute angle, the movement of the semiconductor becomes smoother.
  • the present invention can be applied to thin film transistors such as liquid crystal display devices, electronic paper, and organic EL display devices.

Abstract

A thin-film transistor obtained by stacking the following on an insulating substrate in this order: a gate electrode, a gate-insulating film, and a source electrode and a drain electrode which have a gap interposed between one another in the region overlapping the gate electrode when seen from a planar view. The thin-film transistor also has a semiconductor pattern having a region in the gap. Therein: the gap has a first region having a constant interval, and a second region where the interval gradually increases; and the semiconductor pattern is shaped so as to contain the entirety of the region having the constant interval, and a portion of the region where the interval gradually increases.

Description

薄膜トランジスタおよびその製造方法Thin film transistor and manufacturing method thereof
　本発明は、薄膜トランジスタおよびその製造方法に関し、特に、フレキシブル基板や印刷法に適した薄膜トランジスタおよびその製造方法に係る。 The present invention relates to a thin film transistor and a manufacturing method thereof, and particularly relates to a thin film transistor suitable for a flexible substrate or a printing method and a manufacturing method thereof.
　半導体自体を基板としたトランジスタや集積回路技術を基礎として、ガラス基板上にアモルファスシリコン（ａ-Ｓｉ）やポリシリコン（ｐｏｌｙ-Ｓｉ）の薄膜トランジスタ（Thin Film Transistor：ＴＦＴ）が製造され、液晶ディスプレイなどに応用されている（非特許文献１）。ＴＦＴとしては、例えば図１３のようなものが用いられている（図１３では半導体形状は、明示されていない）。ここでＴＦＴはスイッチの役割を果たしており、ゲート配線２’に与えられた選択電圧によってＴＦＴをオンにした時に、ソース配線４’に与えられた信号電圧をドレイン５に接続された画素電極５’に書き込む。書き込まれた電圧は、画素電極５’／ゲート絶縁膜３／キャパシタ電極１０によって構成される蓄積キャパシタに保持される。ゲート絶縁膜３は、ゲート電極２、ゲート配線２’、キャパシタ電極１０、および、キャパシタ配線１０’よりも上層にあり、ソース電極４、ソース配線４’、ドレイン電極５、画素電極５’、および、図示しない半導体パターンよりも下層にある。キャパシタ電極１０にはキャパシタ配線１０’から電圧が印加される。ここで、ＴＦＴアレイの場合、ソースおよびドレインの働きは書き込む電圧の極性によって変わるため、動作の特徴でソースおよびドレインの名称を決められない。そこで、便宜的に一方をソース、他方をドレインと、呼び方を統一しておく。本発明では、配線に接続されている方をソース、画素電極に接続されている方をドレインと呼ぶ。 Based on transistor and integrated circuit technology based on the semiconductor itself, amorphous silicon (a-Si) and polysilicon (poly-Si) thin film transistors (Thin Film Transistor: TFT) are manufactured on a glass substrate. (Non-Patent Document 1). As the TFT, for example, the one shown in FIG. 13 is used (the semiconductor shape is not clearly shown in FIG. 13). Here, the TFT plays a role of a switch. When the TFT is turned on by a selection voltage applied to the gate wiring 2 ′, the signal voltage applied to the source wiring 4 ′ is applied to the pixel electrode 5 ′ connected to the drain 5. Write to. The written voltage is held in a storage capacitor constituted by the pixel electrode 5 ′ / gate insulating film 3 / capacitor electrode 10. The gate insulating film 3 is above the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′, and the source electrode 4, the source wiring 4 ′, the drain electrode 5, the pixel electrode 5 ′, and , Located below the semiconductor pattern (not shown). A voltage is applied to the capacitor electrode 10 from the capacitor wiring 10 ′. Here, in the case of a TFT array, since the functions of the source and the drain vary depending on the polarity of the voltage to be written, the names of the source and the drain cannot be determined by the characteristics of the operation. Therefore, for convenience, one is called a source and the other is called a drain, and the names are unified. In the present invention, the one connected to the wiring is called a source, and the one connected to the pixel electrode is called a drain.
　近年、有機半導体や酸化物半導体が登場し、２００℃以下の低温でＴＦＴを作製できることが示され、プラスチック基板を用いたフレキシブルディスプレイへの期待が高まっている。フレキシブルという特長以外に、軽量、壊れにくい、薄型化できるというメリットも期待されている。また、印刷によってＴＦＴを形成することにより、安価で大面積なディスプレイが期待されている。 In recent years, organic semiconductors and oxide semiconductors have appeared, and it has been shown that TFTs can be produced at a low temperature of 200 ° C. or lower, and expectations for flexible displays using plastic substrates are increasing. In addition to the feature of flexibility, it is also expected to be light, hard to break, and thin. Moreover, an inexpensive and large-area display is expected by forming TFTs by printing.
　ところで、フレキシブル基板を用いた場合や印刷法を用いた場合、リジッド基板およびフォトリソ法を用いた場合に比べてアライメントずれが大きくなる。フレキシブル基板は、基板自体の位置精度が悪いため、印刷法は、印刷時の移動による位置精度悪化のためである。また、インクの粘度が小さい場合、印刷後の流動により、半導体印刷のパターン幅がばらつくという問題があった。 By the way, when a flexible substrate is used or when a printing method is used, the misalignment becomes larger than when a rigid substrate and a photolithography method are used. This is because the flexible substrate has poor positional accuracy of the substrate itself, and the printing method is due to deterioration of positional accuracy due to movement during printing. Further, when the viscosity of the ink is small, there is a problem that the pattern width of semiconductor printing varies due to the flow after printing.
　薄膜トランジスタの電流特性に最も影響する寸法パラメータは、チャネル長Ｌとチャネル幅Ｗである。チャネルは半導体中を電流が流れる領域、チャネル長Ｌは電流方向の長さ、チャネル幅Ｗは電流に垂直な方向の幅である。チャネル長Ｌはソース電極・ドレイン電極間距離でほぼ決まり、ソース電極・ドレイン電極を同一印刷で形成すればアライメントずれや半導体印刷の影響はない。しかしチャネル幅Ｗはソース電極・ドレイン電極への半導体形成のアライメントずれやパターン幅の影響が大きい。例えば図１４Ａ～図１４Ｃに示すパターンデザインの場合、図１４Ａが設計通りであるが、図１４Ｂのように半導体パターン６が右にずれるとＷが大きくなり、図１４Ｃのように半導体が左にずれるとＷが小さくなる。図１５Ａ～図１５Ｃに示すパターンデザインの場合、図１５Ａが設計通りであるが、図１５Ｂのように半導体パターン６の幅が大きくなるとＷが大きくなり、図１５Ｃのように半導体パターン６の幅が小さくなるとＷが小さくなる。Ｗが変化することになり、それに比例して電流が変化する。なお、破線は設計での半導体縁を示している。 The dimension parameters that most affect the current characteristics of the thin film transistor are the channel length L and the channel width W. A channel is a region in which a current flows in a semiconductor, a channel length L is a length in a current direction, and a channel width W is a width in a direction perpendicular to the current. The channel length L is substantially determined by the distance between the source electrode and the drain electrode, and if the source electrode and the drain electrode are formed by the same printing, there is no influence of misalignment or semiconductor printing. However, the channel width W is greatly affected by misalignment of the semiconductor formation to the source / drain electrodes and the pattern width. For example, in the case of the pattern design shown in FIGS. 14A to 14C, FIG. 14A is as designed, but when the semiconductor pattern 6 is shifted to the right as shown in FIG. 14B, W increases, and the semiconductor is shifted to the left as shown in FIG. 14C. And W become smaller. In the case of the pattern designs shown in FIGS. 15A to 15C, FIG. 15A is as designed, but as the width of the semiconductor pattern 6 increases as shown in FIG. 15B, W increases, and as shown in FIG. 15C, the width of the semiconductor pattern 6 increases. As it becomes smaller, W becomes smaller. W will change, and the current will change proportionally. A broken line indicates a semiconductor edge in the design.
　このように、ソース電極・ドレイン電極への半導体のアライメントずれやパターン幅ばらつきに起因して、チャネル幅のばらつきが発生し、電流のばらつきを引き起こすという問題があった。電流の変化（ばらつき）は、液晶ディスプレイや電子ペーパーのトランジスタ、有機ＥＬの走査トランジスタでは安全係数（＝設計電流値／必要電流値）を大きくする必要が生じ、即ち過大なトランジスタを設けることになる。また、有機ＥＬの駆動トランジスタでは輝度ばらつきを生じ、画質を悪化させる。 As described above, due to the misalignment of the semiconductor to the source electrode and the drain electrode and the pattern width variation, there is a problem that the channel width varies and the current varies. The change (variation) in current requires a large safety factor (= design current value / required current value) for a liquid crystal display, an electronic paper transistor, and an organic EL scanning transistor, that is, an excessive transistor is provided. . In addition, an organic EL drive transistor causes luminance variations, which deteriorates image quality.
　本発明は、係る従来技術の状況に鑑みてなされたもので、ソース電極・ドレイン電極に対する半導体形成のアライメントずれやパターン幅ばらつきの影響が小さい、薄膜トランジスタおよびその製造方法を提供することを課題とする。 The present invention has been made in view of the state of the related art, and it is an object of the present invention to provide a thin film transistor and a method of manufacturing the same that are less affected by misalignment of semiconductor formation with respect to a source electrode and a drain electrode and variations in pattern width. .
　上記課題を解決するための、第１の発明は、絶縁基板上に、ゲート電極と、ゲート絶縁膜と、平面視で前記ゲート電極と重なる領域に互いの間隙を有するソース電極およびドレイン電極とを、順に積層されるように有し、前記間隙に領域を有する半導体パターンを有する薄膜トランジスタであって、前記間隙が、間隔が一定の第１の領域と間隔が漸増する第２の領域とを有し、前記半導体パターンが、間隔が一定の領域の全体と間隔が漸増する領域の一部とを含む形状であることを特徴とする薄膜トランジスタである。 In order to solve the above problems, a first invention includes a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping the gate electrode in plan view on an insulating substrate. A thin film transistor having a semiconductor pattern having a region in the gap, the gap having a first region having a constant interval and a second region having a gradually increasing interval. The thin film transistor is characterized in that the semiconductor pattern has a shape including an entire region having a constant interval and a part of a region in which the interval gradually increases.
　第２の発明は、第１の発明において、前記ゲート電極がゲート配線に接続され、前記ソース電極がソース配線に接続された、マトリクス状の薄膜トランジスタであって、前記半導体パターンが、前記ソース配線に沿った等幅ストライプ形状であり、複数の薄膜トランジスタの半導体がつながって成ることを特徴とする薄膜トランジスタである。 A second invention is a matrix-like thin film transistor in which the gate electrode is connected to a gate wiring and the source electrode is connected to a source wiring in the first invention, and the semiconductor pattern is connected to the source wiring. A thin film transistor having a uniform stripe shape along a plurality of thin film transistor semiconductors connected to each other.
　第３の発明は、絶縁基板上に、ゲート電極と、ゲート絶縁膜と、平面視で前記ゲート電極と重なる領域に互いの間隙を有するソース電極およびドレイン電極とを、順に積層されるように有し、前記間隙に領域を有する半導体パターンを有する薄膜トランジスタであって、前記間隙が、間隔が一定の第１の領域と間隔が漸増する第２の領域とを有し、前記半導体パターンが、前記第１の領域には形成されており、前記第２の領域には必ずしも形成されていないことを特徴とする薄膜トランジスタである。 According to a third invention, a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping with the gate electrode in plan view are sequentially stacked on an insulating substrate. A thin film transistor having a semiconductor pattern having a region in the gap, wherein the gap has a first region having a constant interval and a second region having a gradually increasing interval, and the semiconductor pattern has the first pattern. The thin film transistor is formed in one region and not necessarily formed in the second region.
　第４の発明は、第３の発明において、前記ゲート電極がゲート配線に接続され、前記ソース電極がソース配線に接続された、マトリクス状の薄膜トランジスタであって、前記半導体パターンが、前記ソース配線に沿ったストライプ形状であり、複数の薄膜トランジスタの半導体がつながって成ることを特徴とする薄膜トランジスタである。 A fourth invention is a matrix-like thin film transistor in which the gate electrode is connected to a gate wiring and the source electrode is connected to a source wiring in the third invention, and the semiconductor pattern is connected to the source wiring. The thin film transistor is characterized by a stripe shape extending along a plurality of thin film transistor semiconductors.
　第５の発明は、絶縁基板上に、ゲート電極と、ゲート絶縁膜と、平面視で前記ゲート電極と重なる領域に互いの間隙を有するソース電極およびドレイン電極とを、順に積層するように形成する工程と、前記間隙に領域を有する半導体パターンを印刷する工程とを少なくとも有する薄膜トランジスタの製造方法であって、前記間隙が、間隔が一定の第１の領域と間隔が漸増する第２の領域とを有し、前記半導体パターンの印刷を、前記第１の領域の全体と前記第２の領域の一部とを含むように行うことを特徴とする薄膜トランジスタの製造方法である。 According to a fifth aspect of the present invention, a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping with the gate electrode in plan view are sequentially stacked on an insulating substrate. A method of manufacturing a thin film transistor including at least a step and a step of printing a semiconductor pattern having a region in the gap, wherein the gap includes a first region having a constant interval and a second region having a gradually increasing interval. And the semiconductor pattern is printed so as to include the entire first region and a part of the second region.
　第６の発明は、第５の発明において、前記半導体パターンの印刷パターンが、ソース配線に沿った等幅ストライプ形状であることを特徴とする薄膜トランジスタの製造方法である。 The sixth invention is the method of manufacturing a thin film transistor according to the fifth invention, wherein the printed pattern of the semiconductor pattern is a uniform width stripe shape along the source wiring.
　第７の発明は、第５または第６の発明において、前記第１の領域の全体と前記第２の領域の一部とを含むように印刷された前記半導体パターンの前記印刷パターンのうち、前記第２の領域に印刷された半導体が、前記第１の領域に吸収されることを特徴とする薄膜トランジスタの製造方法である。 A seventh invention is the fifth or sixth invention, wherein, among the printed patterns of the semiconductor pattern printed so as to include the whole of the first region and a part of the second region, A method of manufacturing a thin film transistor, wherein a semiconductor printed in a second region is absorbed in the first region.
　第８の発明は、第５～第７のいずれかの発明において、前記第２の領域の前記間隙と、前記半導体パターンの前記印刷パターンとの重なりが、鋭角を有することを特徴とする薄膜トランジスタの製造方法である。 An eighth invention is the thin film transistor according to any one of the fifth to seventh inventions, wherein an overlap between the gap in the second region and the printed pattern of the semiconductor pattern has an acute angle. It is a manufacturing method.
　本発明によれば、ソース電極・ドレイン電極に対する半導体のアライメントずれやパターン幅ばらつきの影響が小さい薄膜トランジスタおよびその製造方法を提供できる。 According to the present invention, it is possible to provide a thin film transistor that is less affected by misalignment of the semiconductor with respect to the source electrode / drain electrode and variations in pattern width, and a method for manufacturing the same.
図１は、本発明の実施形態を示すものであり、薄膜トランジスタの第１の構成例を示す平面図である。FIG. 1 shows an embodiment of the present invention and is a plan view showing a first configuration example of a thin film transistor. 図２は、本発明の実施形態を示すものであり、薄膜トランジスタの第２の構成例を示す平面図である。FIG. 2 shows an embodiment of the present invention and is a plan view showing a second configuration example of the thin film transistor. 図３Ａは、本発明の実施形態を示すものであり、ばらつき低減効果について第１の説明をする図である。FIG. 3A shows an embodiment of the present invention, and is a diagram for first explaining the variation reducing effect. 図３Ｂは、本発明の実施形態を示すものであり、ばらつき低減効果について第２の説明をする図である。FIG. 3B shows the embodiment of the present invention, and is a diagram for explaining the variation reduction effect second. 図４Ａは、図２の薄膜トランジスタの製造方法の一例について第１の工程を示す平面図である。FIG. 4A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG. 図４Ｂは、図２の薄膜トランジスタの製造方法の一例について第２の工程を示す平面図である。FIG. 4B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG. 図４Ｃは、図２の薄膜トランジスタの製造方法の一例について第３の工程を示す平面図である。FIG. 4C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor of FIG. 図４Ｄは、図２の薄膜トランジスタの製造方法の一例について第４の工程を示す平面図である。FIG. 4D is a plan view showing a fourth step in the example of the method for manufacturing the thin film transistor of FIG. 図４Ｅは、図２の薄膜トランジスタの製造方法の一例について第５の工程を示す平面図である。FIG. 4E is a plan view showing a fifth step in the example of the method for manufacturing the thin film transistor of FIG. 図４Ｆは、図２の薄膜トランジスタの製造方法の一例について第６の工程を示す平面図である。FIG. 4F is a plan view showing a sixth step in the example of the method for manufacturing the thin film transistor of FIG. 図５は、本発明の実施形態を示すものであり、薄膜トランジスタの一例を示す平面図である。FIG. 5 shows an embodiment of the present invention and is a plan view showing an example of a thin film transistor. 図６Ａは、図５の薄膜トランジスタの製造方法の一例について第１の工程を示す平面図である。FIG. 6A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG. 図６Ｂは、図５の薄膜トランジスタの製造方法の一例について第２の工程を示す平面図である。FIG. 6B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG. 図６Ｃは、図５の薄膜トランジスタの製造方法の一例について第３の工程を示す平面図である。FIG. 6C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor in FIG. 5. 図７は、本発明の実施形態を示すものであり、薄膜トランジスタの第３の構成例を示す平面図である。FIG. 7 shows an embodiment of the present invention and is a plan view showing a third configuration example of the thin film transistor. 図８は、本発明の実施形態を示すものであり、薄膜トランジスタの第４の構成例を示す平面図である。FIG. 8 shows an embodiment of the present invention and is a plan view showing a fourth configuration example of the thin film transistor. 図９Ａは、本発明の実施形態を示すものであり、半導体流動効果について第１の説明をする平面図である。FIG. 9A shows an embodiment of the present invention and is a plan view for first explaining the semiconductor flow effect. 図９Ｂは、本発明の実施形態を示すものであり、半導体流動効果について第２の説明をする平面図である。FIG. 9B shows an embodiment of the present invention and is a plan view for second explanation of the semiconductor flow effect. 図１０Ａは、図８の薄膜トランジスタの製造方法の一例について第１の工程を示す平面図である。FIG. 10A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG. 図１０Ｂは、図８の薄膜トランジスタの製造方法の一例について第２の工程を示す平面図である。FIG. 10B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG. 図１０Ｃは、図８の薄膜トランジスタの製造方法の一例について第３の工程を示す平面図である。FIG. 10C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor of FIG. 図１０Ｄは、図８の薄膜トランジスタの製造方法の一例について第４の工程を示す平面図である。FIG. 10D is a plan view showing a fourth step in the example of the method for manufacturing the thin film transistor of FIG. 図１０Ｅは、図８の薄膜トランジスタの製造方法の一例について第５の工程を示す平面図である。FIG. 10E is a plan view showing a fifth step in the example of the method for manufacturing the thin film transistor of FIG. 図１０Ｆは、図８の薄膜トランジスタの製造方法の一例について第６の工程を示す平面図である。FIG. 10F is a plan view showing a sixth step in the example of the method for manufacturing the thin film transistor of FIG. 図１０Ｇは、図８の薄膜トランジスタの製造方法の一例について第７の工程を示す平面図である。FIG. 10G is a plan view showing a seventh step in the example of the method for manufacturing the thin film transistor of FIG. 図１１は、本発明の実施形態を示すものであり、薄膜トランジスタの一例を示す平面図である。FIG. 11 shows an embodiment of the present invention and is a plan view showing an example of a thin film transistor. 図１２Ａは、図１１の薄膜トランジスタの製造方法の一例について第１の工程を示す平面図である。FIG. 12A is a plan view showing a first step in an example of a method for manufacturing the thin film transistor of FIG. 図１２Ｂは、図１１の薄膜トランジスタの製造方法の一例について第２の工程を示す平面図である。12B is a plan view showing a second step in the example of the method for manufacturing the thin film transistor of FIG. 図１２Ｃは、図１１の薄膜トランジスタの製造方法の一例について第３の工程を示す平面図である。FIG. 12C is a plan view showing a third step in the example of the method for manufacturing the thin film transistor of FIG. 図１２Ｄは、図１１の薄膜トランジスタの製造方法の一例について第４の工程を示す平面図である。12D is a plan view showing a fourth step in the example of the method for manufacturing the thin film transistor of FIG. 図１３は、従来技術を示すものであり、薄膜トランジスタの構成例を示す平面図である。FIG. 13 shows a conventional technique and is a plan view showing a configuration example of a thin film transistor. 図１４Ａは、従来技術を示すものであり、薄膜トランジスタの第１のパターンデザイン例を示す平面図である。FIG. 14A shows the prior art and is a plan view showing a first pattern design example of a thin film transistor. 図１４Ｂは、図１４Ａのパターンデザインにおける第１のパターンずれを示す平面図である。14B is a plan view showing a first pattern shift in the pattern design of FIG. 14A. 図１４Ｃは、図１４Ａのパターンデザインにおける第２のパターンずれを示す平面図である。FIG. 14C is a plan view showing a second pattern shift in the pattern design of FIG. 14A. 図１５Ａは、従来技術を示すものであり、薄膜トランジスタの第２のパターンデザイン例を示す平面図である。FIG. 15A shows the prior art and is a plan view showing a second pattern design example of the thin film transistor. 図１５Ｂは、図１５Ａのパターンデザインにおける第１のパターンずれを示す平面図である。FIG. 15B is a plan view showing a first pattern shift in the pattern design of FIG. 15A. 図１５Ｃは、図１５Ａのパターンデザインにおける第２のパターンずれを示す平面図である。FIG. 15C is a plan view showing a second pattern shift in the pattern design of FIG. 15A.
　本発明の実施の形態について、以下に図面を使用して詳細に説明する。なお、以下に使用する図面では、説明を判り易くするために縮尺は正確には描かれていない。 Embodiments of the present invention will be described in detail below with reference to the drawings. In the drawings used below, the scale is not accurately drawn for easy understanding.
[第１の実施形態]
　本発明の第１の実施形態に係る薄膜トランジスタの例を、図１、図２、図５に平面図で示す。図１、図２、図５に示すように、本実施形態に係る薄膜トランジスタは、絶縁基板１上に、ゲート電極２、ゲート配線２’、キャパシタ電極１０、および、キャパシタ配線１０’を有し、その上にゲート絶縁膜３を有し、その上に、上から見て前記ゲート電極２と重なる領域に間隙を有するソース電極４・ドレイン電極５、ソース配線４’、および、ドレイン電極５に接続された画素電極５’を有し、該ソース電極４とドレイン電極５との間隙に領域を有するような半導体パターン６を有する薄膜トランジスタである。また、当該薄膜トランジスタにおいて、該ソース電極４とドレイン電極５との間隙が、間隔が一定の領域と間隔が漸増する領域とを有し、半導体パターン６が、間隔が一定の領域の全体と間隔が漸増する領域の一部とを含む形状である。当該間隔が一定の領域は、図５のように直線状でもよいし、図１のように角ばったコーナ部を有する多角形状でもよいし、図２のように丸まったコーナ部を有する曲線形状でもよい。なお、絶縁基板１は図１、図２、図５において最下層の全体に広がっているため、特に境界線は示しておらず、このことは他の図においても同様とする。また、ソース配線４’は、薄膜トランジスタの各ソース電極４とソース駆動回路出力とを接続する部分を指しているが、図面上ではソース配線４’がソース電極４を兼ねている、即ちソース配線４’の一部がソース電極４となっているため、ソース電極４に符号４’を併記した。 [First embodiment]
Examples of the thin film transistor according to the first embodiment of the present invention are shown in plan views in FIGS. As shown in FIGS. 1, 2, and 5, the thin film transistor according to this embodiment includes a gate electrode 2, a gate wiring 2 ′, a capacitor electrode 10, and a capacitor wiring 10 ′ on an insulating substrate 1. A gate insulating film 3 is formed thereon, and connected to the source electrode 4 and the drain electrode 5, the source wiring 4 ′, and the drain electrode 5 having a gap in a region overlapping with the gate electrode 2 when viewed from above. The thin film transistor has a pixel pattern 5 ′ and a semiconductor pattern 6 having a region in the gap between the source electrode 4 and the drain electrode 5. Further, in the thin film transistor, the gap between the source electrode 4 and the drain electrode 5 has a region having a constant interval and a region in which the interval gradually increases, and the semiconductor pattern 6 has a distance from the entire region having a constant interval. The shape includes a part of a gradually increasing region. The region where the interval is constant may be linear as shown in FIG. 5 or may be a polygonal shape having a rounded corner as shown in FIG. 1 or a curved shape having a rounded corner as shown in FIG. Good. Since the insulating substrate 1 extends over the entire lowermost layer in FIGS. 1, 2, and 5, no boundary line is shown, and this also applies to other drawings. Further, the source wiring 4 ′ indicates a portion connecting each source electrode 4 of the thin film transistor and the source driving circuit output, but the source wiring 4 ′ also serves as the source electrode 4 in the drawing, that is, the source wiring 4 Since a part of 'is the source electrode 4, reference numeral 4 ′ is also written on the source electrode 4.
　図３Ａおよび図３Ｂを用いて、半導体パターン６の縁が、間隔が漸増する領域にある効果について説明する。従来のように半導体パターン６の縁が間隔一定値Ｌの部分にある場合（図３Ａ）、半導体パターン６の縁（実線）が設計位置（破線）よりΔｘだけずれると、チャネル幅／チャネル長はΔｘ／Ｌだけ変化する。一方、本実施形態（図３Ｂ）の場合、間隔が漸増する部分のチャネル幅／チャネル長はＷ１／（Ｌ１－Ｌ）×ｌｎ［｛（Ｌ１－Ｌ）／Ｗ２＋Ｌ｝／Ｌ］となり、半導体パターンの縁がΔｘずれると、チャネル幅／チャネル長はΔｘ／｛（Ｌ１－Ｌ）／Ｗ１×Ｗ２＋Ｌ｝だけ変化するが、この値は従来値のＬ／｛（Ｌ１－Ｌ）／Ｗ１×Ｗ２＋Ｌ｝倍に小さくなっている（Ｌ１＞Ｌの場合）。ただし、Ｌは間隔一定部の間隔、Ｌ１は広がった先での間隔、Ｗ１はテーパーに対応するｘ方向寸法、Ｗ２はテーパー開始位置から半導体縁までの設計値である。例えばＬ＝１０μｍ、Ｌ１＝３０μｍ、Ｗ１＝２０μｍ、Ｗ２＝１０μｍの場合、チャネル幅／チャネル長の変化量は従来の半分になる。この効果により、チャネル幅のばらつきを小さく抑えられる。図１および図２では、半導体印刷のアライメントずれに起因するチャネル幅ばらつきを低減できる。図５では、半導体印刷のパターン幅ばらつきに起因するチャネル幅ばらつきを低減できる。なお、上述の式はテーパーが直線状に広がった場合であるが、テーパーが直線状でなくても類似の効果があり、本発明は直線状のテーパーに限定するものではない。 3A and 3B, the effect of the edge of the semiconductor pattern 6 being in a region where the interval gradually increases will be described. When the edge of the semiconductor pattern 6 is in the portion of the constant interval L as in the conventional case (FIG. 3A), if the edge (solid line) of the semiconductor pattern 6 is shifted by Δx from the design position (broken line), the channel width / channel length is Changes by Δx / L. On the other hand, in the present embodiment (FIG. 3B), the channel width / channel length of the portion where the interval gradually increases is W1 / (L1-L) × ln [{(L1-L) / W2 + L} / L], and the semiconductor pattern Is shifted by Δx, the channel width / channel length changes by Δx / {(L1−L) / W1 × W2 + L}, which is the conventional value L / {(L1−L) / W1 × W2 + L}. It is doubled (when L1> L). Here, L is the interval of the constant interval portion, L1 is the interval at the widened point, W1 is the dimension in the x direction corresponding to the taper, and W2 is the design value from the taper start position to the semiconductor edge. For example, when L = 10 μm, L1 = 30 μm, W1 = 20 μm, and W2 = 10 μm, the amount of change in channel width / channel length is half of that in the prior art. Due to this effect, variations in channel width can be suppressed. In FIG. 1 and FIG. 2, channel width variations due to semiconductor printing misalignment can be reduced. In FIG. 5, it is possible to reduce channel width variations due to semiconductor print pattern width variations. In addition, although the above-mentioned formula is a case where a taper spreads linearly, there is a similar effect even if the taper is not linear, and the present invention is not limited to a linear taper.
　また、図４Ａ～図４Ｆ、図６Ａ～図６Ｃに示すように本実施形態に係る薄膜トランジスタの製造方法は、絶縁基板１上に、ゲート電極２を形成する工程と、その上にゲート絶縁膜３を形成する工程と、上から見て前記ゲート電極２と重なる領域に間隙を有するソース電極４・ドレイン電極５を形成する工程と、該ソース電極４とドレイン電極５との間隙に領域を有するように半導体パターン６を印刷する工程と、を少なくとも有する薄膜トランジスタの製造方法であって、該ソース電極４とドレイン電極５との間隙が、間隔が一定の領域と間隔が漸増する領域とを有し、半導体パターン６の印刷を、間隔が一定の領域の全体と間隔が漸増する領域の一部とを含むように行うことを特徴とする薄膜トランジスタの製造方法である。 4A to 4F and FIGS. 6A to 6C, the method of manufacturing the thin film transistor according to the present embodiment includes the step of forming the gate electrode 2 on the insulating substrate 1, and the gate insulating film 3 thereon. Forming a source electrode 4 and a drain electrode 5 having a gap in a region overlapping the gate electrode 2 when viewed from above, and having a region in the gap between the source electrode 4 and the drain electrode 5 And a step of printing the semiconductor pattern 6 on the thin film transistor, wherein the gap between the source electrode 4 and the drain electrode 5 has a constant interval region and a gradually increasing region. A method of manufacturing a thin film transistor, wherein the semiconductor pattern 6 is printed so as to include an entire region having a constant interval and a part of a region in which the interval gradually increases.
　絶縁基板１としては、ガラス基板のようなリジッドなものでもよいし、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレンナフタレート（ＰＥＮ）、ポリイミド（ＰＩ）、ポリエーテルイミド（ＰＥＩ）、ポリエーテルスルホン（ＰＥＳ）、等のフレキシブルなものでもよい。 The insulating substrate 1 may be a rigid substrate such as a glass substrate, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), polyetherimide (PEI), polyethersulfone (PES), It may be flexible.
　その上に、ゲート電極２を形成する（図４Ａ、図６Ａ）。通常、ゲート電極２はゲート配線２’に接続されている。また、同一層にキャパシタ電極１０を有し、それがキャパシタ配線１０’に接続されていてもよい。ゲート電極２、ゲート配線２’、キャパシタ電極１０、キャパシタ配線１０’としては、Ａｌ、Ａｇ、Ｃｕ、Ｃｒ、Ｎｉ、Ｍｏ、Ａｕ、Ｐｔ等の金属や、ＩＴＯ等の導電性酸化物、カーボン、導電性高分子等を用いることができる。製法としては、インクを印刷・焼成してもよいし、全面成膜後にフォトリソ・エッチング・レジスト剥離によって形成してもよい。あるいは、全面成膜後にレジスト印刷・エッチング・レジスト剥離によって形成してもよい。 A gate electrode 2 is formed thereon (FIGS. 4A and 6A). Usually, the gate electrode 2 is connected to the gate wiring 2 '. Further, the capacitor electrode 10 may be provided in the same layer and connected to the capacitor wiring 10 ′. As the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′, a metal such as Al, Ag, Cu, Cr, Ni, Mo, Au, and Pt, a conductive oxide such as ITO, carbon, A conductive polymer or the like can be used. As a manufacturing method, ink may be printed and baked, or may be formed by photolithography, etching, and resist peeling after film formation on the entire surface. Alternatively, it may be formed by resist printing / etching / resist stripping after film formation on the entire surface.
　次に、図４Ａ、図６Ａに網掛け模様で示すようにゲート絶縁膜３を形成する。ゲート絶縁膜３としては、ＳｉＯ２、ＳｉＯＮ、ＳｉＮ等の無機物や、ポリビニルフェノール（ＰＶＰ）、エポキシ等の有機物を用いることができる。製法としては、スパッタ、ＣＶＤ等の真空成膜や、溶液の塗布・焼成によって得られる。 Next, the gate insulating film 3 is formed as shown by the shaded pattern in FIGS. 4A and 6A. As the gate insulating film 3, an inorganic material such as SiO 2 , SiON, or SiN, or an organic material such as polyvinylphenol (PVP) or epoxy can be used. As a manufacturing method, it can be obtained by vacuum film formation such as sputtering or CVD, or coating and baking of a solution.
　さらに、ソース電極４・ドレイン電極５を形成する（図４Ｂ、図６Ｂ）。ここでソース電極４・ドレイン電極５は、上から見て前記ゲート電極２と重なる領域に間隙を有し、その間隙は、間隔が一定の領域と、間隔が漸増する領域を有する。なお、ソース電極４は通常、ソース配線４’に接続され、ドレイン電極５は通常、画素電極５’に接続されている。ソース電極４・ドレイン電極５としては、Ａｇ、Ｃｕ、Ｃｒ、Ｎｉ、Ｍｏ、Ａｕ、Ｐｔ、Ａｌ等の金属や、ＩＴＯ等の導電性酸化物、カーボン、導電性高分子等を用いることができる。製法としては、全面成膜後にフォトリソ・エッチング・レジスト剥離によって形成してもよいが、インクを印刷・焼成して得ることが望ましい。印刷方法としては、スクリーン印刷、グラビア印刷、フレキソ印刷、オフセット印刷等が好適である。特にグラビア印刷、フレキソ印刷、オフセット印刷は、２０μｍ以下のパターンを再現性よく形成することができる。 Further, a source electrode 4 and a drain electrode 5 are formed (FIGS. 4B and 6B). Here, the source electrode 4 and the drain electrode 5 have a gap in a region overlapping the gate electrode 2 when viewed from above, and the gap has a region having a constant interval and a region in which the interval gradually increases. Note that the source electrode 4 is normally connected to the source wiring 4 ′, and the drain electrode 5 is usually connected to the pixel electrode 5 ′. As the source electrode 4 and the drain electrode 5, metals such as Ag, Cu, Cr, Ni, Mo, Au, Pt, and Al, conductive oxides such as ITO, carbon, conductive polymers, and the like can be used. . As a manufacturing method, it may be formed by photolithography, etching, or resist peeling after film formation on the entire surface, but it is desirable to obtain it by printing and baking ink. As the printing method, screen printing, gravure printing, flexographic printing, offset printing and the like are suitable. In particular, gravure printing, flexographic printing, and offset printing can form a pattern of 20 μm or less with good reproducibility.
　そして、図４Ｂまたは図６Ｂの状態の基板上に半導体パターン６を形成する。このとき、半導体パターン６が、前記間隔が一定の領域の全体と、前記間隔が漸増する領域の一部とを含むように、印刷直後の半導体の印刷パターン６’を形成する（図４Ｃ、図６Ｃ）。半導体パターン６は、各トランジスタごとに独立していてもよいし、ソース配線４’に平行な方向につながったストライプ状でもよい。半導体パターン６としては、ポリチオフェン系、アセン系、アリルアミン系などの有機半導体や、Ｉｎ２Ｏ３系、Ｇａ２Ｏ３系、ＺｎＯ系、ＳｎＯ２系、ＩｎＧａＺｎＯ系、ＩｎＧａＳｎＯ系、ＩｎＳｎＺｎＯ系などの酸化物半導体を用いることができる。製法としては、溶液をインクジェット、ディスペンサ、フレキソ印刷等で印刷・焼成する方法が好適である。 Then, the semiconductor pattern 6 is formed on the substrate in the state shown in FIG. 4B or 6B. At this time, the semiconductor printed pattern 6 ′ immediately after printing is formed so that the semiconductor pattern 6 includes the entire region having the constant interval and a part of the region in which the interval gradually increases (FIG. 4C, FIG. 6C). The semiconductor pattern 6 may be independent for each transistor or may have a stripe shape connected in a direction parallel to the source wiring 4 ′. Examples of the semiconductor pattern 6 include organic semiconductors such as polythiophene, acene, and allylamine, and oxidation such as In 2 O 3 , Ga 2 O 3 , ZnO, SnO 2 , InGaZnO, InGaSnO, and InSnZnO. A physical semiconductor can be used. As the production method, a method of printing and baking the solution by inkjet, dispenser, flexographic printing or the like is suitable.
　なお、半導体の印刷パターン６’は単純な形状が望ましい。単純な形状ほど、印刷が容易になるからである。最も好ましいのはソース配線４’に平行な等幅ストライプ形状であり、縦方向に並ぶＴＦＴの半導体がつながった形状である。この場合、縦方向のアライメントずれは特性に影響しない。次に望ましいのは、長方形を各ＴＦＴに配置した形状である。この場合、縦方向のアライメントずれが小さければ特性に影響しない。 It should be noted that the semiconductor print pattern 6 'is preferably a simple shape. This is because printing with a simpler shape becomes easier. The most preferred is a uniform stripe shape parallel to the source wiring 4 ′, in which TFT semiconductors arranged in the vertical direction are connected. In this case, the vertical misalignment does not affect the characteristics. Next, a shape in which a rectangle is arranged in each TFT is desirable. In this case, if the vertical misalignment is small, the characteristics are not affected.
　こうして作製したＴＦＴのゲート配線２’およびソース配線４’に適切な波形を与えることにより、画素電極５’の電位を制御でき、電子ペーパー等の表示を行うことが可能となる。 By applying appropriate waveforms to the gate wiring 2 ′ and source wiring 4 ′ of the TFT thus fabricated, the potential of the pixel electrode 5 ′ can be controlled, and electronic paper or the like can be displayed.
　場合によっては、さらに半導体パターン６を覆う封止層７（図４Ｄ）や、画素電極５’上に開口Ａを有する層間絶縁膜８（図４Ｅに模様を施して示す）や、該開口Ａを通じて画素電極５’に接続された上部画素電極９（図４Ｆ）を設けることもできる。半導体パターン６がストライプの場合、封止層７もストライプが望ましい。また、半導体パターン６が独立であって、封止層７がストライプでもよい。封止層７としては、フッ素樹脂などの有機物や、ＳｉＯ２、ＳｉＮ、ＳｉＯＮ等の無機物、あるいはそれらの混合物、積層物などを使用することができる。製法としては、全面に成膜後、フォトリソ・エッチング・レジスト除去による方法も可能であるが、溶液をスクリーン印刷等の方法で印刷・焼成する方法がより好適である。層間絶縁膜８としてはエポキシ等の有機絶縁膜が好適であり、上部画素電極９としてはＡｇペースト等が好適であり、いずれもスクリーン印刷等の方法で印刷・焼成するのがよい。層間絶縁膜８および上部画素電極９を有する場合、ゲート配線２’およびソース配線４’に適切な波形を与えることにより、上部画素電極９の電位を制御でき、電子ペーパー等の表示を行うことが可能となる。 In some cases, a sealing layer 7 (FIG. 4D) that further covers the semiconductor pattern 6, an interlayer insulating film 8 having an opening A on the pixel electrode 5 ′ (shown with a pattern in FIG. 4E), and through the opening A An upper pixel electrode 9 (FIG. 4F) connected to the pixel electrode 5 ′ can also be provided. When the semiconductor pattern 6 is a stripe, the sealing layer 7 is also preferably a stripe. Further, the semiconductor pattern 6 may be independent and the sealing layer 7 may be a stripe. As the sealing layer 7, an organic material such as a fluororesin, an inorganic material such as SiO 2 , SiN, or SiON, or a mixture or laminate thereof can be used. As a manufacturing method, a method of photolithography, etching, and resist removal after film formation on the entire surface is possible, but a method of printing and baking the solution by a method such as screen printing is more preferable. The interlayer insulating film 8 is preferably an organic insulating film such as epoxy, and the upper pixel electrode 9 is preferably Ag paste or the like, and any of them may be printed and baked by a method such as screen printing. When the interlayer insulating film 8 and the upper pixel electrode 9 are provided, the potential of the upper pixel electrode 9 can be controlled by applying appropriate waveforms to the gate wiring 2 ′ and the source wiring 4 ′, and display such as electronic paper can be performed. It becomes possible.
[第２の実施形態]
　本発明の第２の実施形態に係る薄膜トランジスタの例を、図７、図８、図１１に平面図で示す。図７、図８、図１１に示すように本実施形態に係る薄膜トランジスタは、絶縁基板１上に、ゲート電極２、ゲート配線２’、キャパシタ電極１０、および、キャパシタ配線１０’を有し、その上にゲート絶縁膜３を有し、その上に、上から見て前記ゲート電極２と重なる領域に間隙を有するソース電極４・ドレイン電極５、ソース配線４’、および、画素電極５’を有し、該ソース電極４とドレイン電極５との間隙に領域を有するような半導体パターン６を有する。また、当該薄膜トランジスタにおいて、該ソース電極４とドレイン電極５との間隙が、間隔が一定の領域と間隔が漸増する領域とを有している。半導体パターン６は、当該間隔が一定の領域には形成されており、間隔が漸増する領域には形成されていない。当該間隔が一定の領域は、図１１のように直線状でもよいし、図７のように角ばったコーナ部を有する多角形状でもよいし、図８のように丸まったコーナ部を有する曲線形状でもよい。 [Second Embodiment]
Examples of thin film transistors according to the second embodiment of the present invention are shown in plan views in FIGS. As shown in FIGS. 7, 8, and 11, the thin film transistor according to this embodiment includes a gate electrode 2, a gate wiring 2 ′, a capacitor electrode 10, and a capacitor wiring 10 ′ on an insulating substrate 1. A gate insulating film 3 is provided thereon, and a source electrode 4 and a drain electrode 5, a source wiring 4 ′, and a pixel electrode 5 ′ having a gap in a region overlapping the gate electrode 2 when viewed from above are provided. The semiconductor pattern 6 has a region in the gap between the source electrode 4 and the drain electrode 5. In the thin film transistor, the gap between the source electrode 4 and the drain electrode 5 includes a region having a constant interval and a region in which the interval gradually increases. The semiconductor pattern 6 is formed in a region where the interval is constant, and is not formed in a region where the interval gradually increases. The region where the interval is constant may be linear as shown in FIG. 11, may be a polygonal shape having a rounded corner as shown in FIG. 7, or may be a curved shape having a rounded corner as shown in FIG. Good.
　また、図１０Ａ～図１０Ｇ、図１２Ａ～図１２Ｄに示すように本実施形態に係る薄膜トランジスタの製造方法は、絶縁基板１上に、ゲート電極２を形成する工程と、その上にゲート絶縁膜３を形成する工程と、上から見て前記ゲート電極２と重なる領域に間隙を有するソース電極４・ドレイン電極５を形成する工程と、該ソース電極４とドレイン電極５との間隙に領域を有するように半導体パターン６を印刷する工程と、を少なくとも有する薄膜トランジスタの製造方法であって、該ソース電極４とドレイン電極５との間隙が、間隔が一定の領域と間隔が漸増する領域とを有し、半導体の印刷パターン６’を、間隔が一定の領域の全体と間隔が漸増する領域の一部とを含むように行うことを特徴とする薄膜トランジスタの製造方法である。 10A to 10G and 12A to 12D, the thin film transistor manufacturing method according to the present embodiment includes a step of forming a gate electrode 2 on an insulating substrate 1, and a gate insulating film 3 thereon. Forming a source electrode 4 and a drain electrode 5 having a gap in a region overlapping the gate electrode 2 when viewed from above, and having a region in the gap between the source electrode 4 and the drain electrode 5 And a step of printing the semiconductor pattern 6 on the thin film transistor, wherein the gap between the source electrode 4 and the drain electrode 5 has a constant interval region and a gradually increasing region. A method of manufacturing a thin film transistor, wherein the printed pattern 6 ′ of the semiconductor is performed so as to include the entire region having a constant interval and a part of the region having a gradually increasing interval.
　本実施形態の場合、上記ソース電極４とドレイン電極５との間隙のうち、図９Ａに示すような間隔が漸増する領域に印刷された半導体が、図９Ｂに示すように間隔が一定の領域に吸収される。これは、表面張力の効果である。また、上記ソース電極４とドレイン電極５との間隔が漸増する領域のソース電極４とドレイン電極５との間隙と、半導体の印刷パターン６’との重なり部が、鋭角を有する場合、半導体の吸収がスムーズに行える。 In the case of the present embodiment, the semiconductor printed in the region where the interval gradually increases as shown in FIG. 9A in the gap between the source electrode 4 and the drain electrode 5 becomes a region where the interval is constant as shown in FIG. 9B. Absorbed. This is a surface tension effect. Further, when the gap between the source electrode 4 and the drain electrode 5 in the region where the distance between the source electrode 4 and the drain electrode 5 gradually increases and the overlapping portion of the semiconductor print pattern 6 ′ has an acute angle, the semiconductor absorption Can be done smoothly.
　第１の実施形態との違いは、主に半導体インクの粘性が効いている。第１の実施形態では、インクの粘性が大きいために印刷後のインクの流動が起こりにくく、印刷パターン６’がほぼそのまま半導体パターン６となる。一方、第２の実施形態では、インクの粘性が小さいために印刷後のインクの流動が起こり易い。半導体インクの表面張力により、半導体インクは間隔が漸増する領域よりも間隔が一定の（狭い）領域にある方が安定である。また、半導体インクがソース電極４およびドレイン電極５の近傍にある方が安定なため、ソース電極４とドレイン電極５との間隙と半導体印刷パターン６’との重なり部が鋭角を有する場合、図９Ａのように、半導体インクがソース電極４またはドレイン電極５に引き付けられる方向と、半導体インクが間隔一定領域に引き付けられる方向が近いので、間隔一定領域に吸収される作用を強めることができる。 The difference from the first embodiment is mainly the viscosity of the semiconductor ink. In the first embodiment, since the viscosity of the ink is large, it is difficult for the ink to flow after printing, and the printed pattern 6 ′ becomes the semiconductor pattern 6 almost as it is. On the other hand, in the second embodiment, since the viscosity of the ink is small, the ink flows easily after printing. Due to the surface tension of the semiconductor ink, the semiconductor ink is more stable in the region where the interval is constant (narrow) than the region where the interval increases gradually. Further, since it is more stable that the semiconductor ink is in the vicinity of the source electrode 4 and the drain electrode 5, when the overlapping portion of the gap between the source electrode 4 and the drain electrode 5 and the semiconductor printed pattern 6 ′ has an acute angle, FIG. As described above, since the direction in which the semiconductor ink is attracted to the source electrode 4 or the drain electrode 5 is close to the direction in which the semiconductor ink is attracted to the constant interval region, the action of being absorbed in the constant interval region can be enhanced.
　絶縁基板１としては、ガラス基板のようなリジッドなものでもよいし、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレンナフタレート（ＰＥＮ）、ポリイミド（ＰＩ）、ポリエーテルイミド（ＰＥＩ）、ポリエーテルスルホン（ＰＥＳ）、等のフレキシブルなものでもよい。 The insulating substrate 1 may be a rigid substrate such as a glass substrate, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), polyetherimide (PEI), polyethersulfone (PES), It may be flexible.
　その上に、ゲート電極２を形成する（図１０Ａ、図１２Ａ）。通常、ゲート電極２はゲート配線２’に接続されている。また、同一層にキャパシタ電極１０を有し、それがキャパシタ配線１０’に接続されていてもよい。ゲート電極２、ゲート配線２’、キャパシタ電極１０、キャパシタ配線１０’としては、Ａｌ、Ａｇ、Ｃｕ、Ｃｒ、Ｎｉ、Ｍｏ、Ａｕ、Ｐｔ等の金属や、ＩＴＯ等の導電性酸化物、カーボン、導電性高分子等を用いることができる。製法としては、インクを印刷・焼成してもよいし、全面成膜後にフォトリソ・エッチング・レジスト剥離によって形成してもよい。あるいは、全面成膜後にレジスト印刷・エッチング・レジスト剥離によって形成してもよい。 The gate electrode 2 is formed thereon (FIGS. 10A and 12A). Usually, the gate electrode 2 is connected to the gate wiring 2 '. Further, the capacitor electrode 10 may be provided in the same layer and connected to the capacitor wiring 10 ′. As the gate electrode 2, the gate wiring 2 ′, the capacitor electrode 10, and the capacitor wiring 10 ′, a metal such as Al, Ag, Cu, Cr, Ni, Mo, Au, and Pt, a conductive oxide such as ITO, carbon, A conductive polymer or the like can be used. As a manufacturing method, ink may be printed and baked, or may be formed by photolithography, etching, and resist peeling after film formation on the entire surface. Alternatively, it may be formed by resist printing / etching / resist stripping after film formation on the entire surface.
　次に、図１０Ａ、図１２Ａに網掛け模様で示すようにゲート絶縁膜３を形成する。ゲート絶縁膜３としては、ＳｉＯ２、ＳｉＯＮ、ＳｉＮ等の無機物や、ポリビニルフェノール（ＰＶＰ）、エポキシ等の有機物を用いることができる。製法としては、スパッタ、ＣＶＤ等の真空成膜や、溶液の塗布・焼成によって得られる。 Next, the gate insulating film 3 is formed as shown by the shaded pattern in FIGS. 10A and 12A. As the gate insulating film 3, an inorganic material such as SiO 2 , SiON, or SiN, or an organic material such as polyvinylphenol (PVP) or epoxy can be used. As a manufacturing method, it can be obtained by vacuum film formation such as sputtering or CVD, or coating and baking of a solution.
　さらに、ソース電極４・ドレイン電極５を形成する（図１０Ｂ、図１２Ｂ）。ここでソース電極４・ドレイン電極５は、上から見て前記ゲート電極２と重なる領域に間隙を有し、その間隙は、間隔が一定の領域と、間隔が漸増する領域とを有する。なお、ソース電極４は通常、ソース配線４’に接続され、ドレイン電極５は通常、画素電極５’に接続されている。ソース電極４・ドレイン電極５としては、Ａｇ、Ｃｕ、Ｃｒ、Ｎｉ、Ｍｏ、Ａｕ、Ｐｔ、Ａｌ等の金属や、ＩＴＯ等の導電性酸化物、カーボン、導電性高分子等を用いることができる。製法としては、全面成膜後にフォトリソ・エッチング・レジスト剥離によって形成してもよいが、インクを印刷・焼成して得ることが望ましい。印刷方法としては、スクリーン印刷、グラビア印刷、フレキソ印刷、オフセット印刷等が好適である。特にグラビア印刷、フレキソ印刷、オフセット印刷は、２０μｍ以下のパターンを再現性よく形成することができる。 Further, the source electrode 4 and the drain electrode 5 are formed (FIGS. 10B and 12B). Here, the source electrode 4 and the drain electrode 5 have a gap in a region overlapping with the gate electrode 2 when viewed from above, and the gap has a region having a constant interval and a region in which the interval gradually increases. Note that the source electrode 4 is normally connected to the source wiring 4 ′, and the drain electrode 5 is usually connected to the pixel electrode 5 ′. As the source electrode 4 and the drain electrode 5, metals such as Ag, Cu, Cr, Ni, Mo, Au, Pt, and Al, conductive oxides such as ITO, carbon, conductive polymers, and the like can be used. . As a manufacturing method, it may be formed by photolithography, etching, or resist peeling after film formation on the entire surface, but it is desirable to obtain it by printing and baking ink. As the printing method, screen printing, gravure printing, flexographic printing, offset printing and the like are suitable. In particular, gravure printing, flexographic printing, and offset printing can form a pattern of 20 μm or less with good reproducibility.
　そして、前記間隔が一定の領域の全体と、前記間隔が漸増する領域の一部とを含むように、半導体の印刷パターン６’を形成する（図１０Ｃ、図１２Ｃ）。印刷パターン６’は、前述のように、ソース電極４とドレイン電極５との間隔一定の領域に吸収される（図１０Ｄ、図１２Ｄ）。半導体パターン６としては、ポリチオフェン系、アセン系、アリルアミン系などの有機半導体や、Ｉｎ２Ｏ３系、Ｇａ２Ｏ３系、ＺｎＯ系、ＳｎＯ２系、ＩｎＧａＺｎＯ系、ＩｎＧａＳｎＯ系、ＩｎＳｎＺｎＯ系などの酸化物半導体を用いることができる。製法としては、溶液をインクジェット、ディスペンサ、フレキソ印刷等で印刷・焼成する方法が好適である。 Then, a semiconductor printed pattern 6 ′ is formed so as to include the entire region having the constant interval and a part of the region in which the interval gradually increases (FIGS. 10C and 12C). As described above, the printed pattern 6 ′ is absorbed in the region where the distance between the source electrode 4 and the drain electrode 5 is constant (FIGS. 10D and 12D). Examples of the semiconductor pattern 6 include organic semiconductors such as polythiophene, acene, and allylamine, and oxidation such as In 2 O 3 , Ga 2 O 3 , ZnO, SnO 2 , InGaZnO, InGaSnO, and InSnZnO. A physical semiconductor can be used. As the production method, a method of printing and baking the solution by inkjet, dispenser, flexographic printing or the like is suitable.
　なお、半導体の印刷パターン６’は単純な形状が望ましい。単純な形状ほど、印刷が容易になるからである。最も好ましいのはソース配線４’に平行な等幅ストライプ形状であり、縦方向に並ぶＴＦＴの半導体がつながった形状である。この場合、縦方向のアライメントずれは特性に影響しない。次に望ましいのは、長方形を各ＴＦＴに配置した形状である。この場合、縦方向のアライメントずれが小さければ特性に影響しない。 It should be noted that the semiconductor print pattern 6 'is preferably a simple shape. This is because printing with a simpler shape becomes easier. The most preferred is a uniform stripe shape parallel to the source wiring 4 ′, in which TFT semiconductors arranged in the vertical direction are connected. In this case, the vertical misalignment does not affect the characteristics. Next, a shape in which a rectangle is arranged in each TFT is desirable. In this case, if the vertical misalignment is small, the characteristics are not affected.
　こうして作製したＴＦＴのゲート配線２’およびソース配線４’に適切な波形を与えることにより、画素電極５’の電位を制御でき、電子ペーパー等の表示を行うことが可能となる。 By applying appropriate waveforms to the gate wiring 2 ′ and source wiring 4 ′ of the TFT thus fabricated, the potential of the pixel electrode 5 ′ can be controlled, and electronic paper or the like can be displayed.
　場合によっては、さらに半導体パターン６を覆う封止層７（図１０Ｅ）や、画素電極５’上に開口Ａを有する層間絶縁膜８（図１０Ｆ）や、該開口Ａを通じて画素電極５’に接続された上部画素電極９（図１０Ｇ）を設けることもできる。半導体パターン６がストライプの場合、封止層７もストライプが望ましい。また、半導体パターン６が独立であって、封止層７がストライプでもよい。封止層７としては、フッ素樹脂などの有機物や、ＳｉＯ２、ＳｉＮ、ＳｉＯＮ等の無機物、あるいはそれらの混合物、積層物などを使用することができる。製法としては、全面に成膜後、フォトリソ・エッチング・レジスト除去による方法も可能であるが、溶液をスクリーン印刷等の方法で印刷・焼成する方法がより好適である。層間絶縁膜８としてはエポキシ等の有機絶縁膜が好適であり、上部画素電極９としてはＡｇペースト等が好適であり、いずれもスクリーン印刷等の方法で印刷・焼成するのがよい。層間絶縁膜８および上部画素電極９を有する場合、ゲート配線２’およびソース配線４’に適切な波形を与えることにより、上部画素電極９の電位を制御でき、電子ペーパー等の表示を行うことが可能となる。 In some cases, the sealing layer 7 (FIG. 10E) further covering the semiconductor pattern 6, the interlayer insulating film 8 (FIG. 10F) having the opening A on the pixel electrode 5 ′, and the pixel electrode 5 ′ are connected through the opening A. It is also possible to provide the upper pixel electrode 9 (FIG. 10G). When the semiconductor pattern 6 is a stripe, the sealing layer 7 is also preferably a stripe. Further, the semiconductor pattern 6 may be independent and the sealing layer 7 may be a stripe. As the sealing layer 7, an organic material such as a fluororesin, an inorganic material such as SiO 2 , SiN, or SiON, or a mixture or laminate thereof can be used. As a manufacturing method, a method of photolithography, etching, and resist removal after film formation on the entire surface is possible, but a method of printing and baking the solution by a method such as screen printing is more preferable. The interlayer insulating film 8 is preferably an organic insulating film such as epoxy, and the upper pixel electrode 9 is preferably Ag paste or the like, and any of them may be printed and baked by a method such as screen printing. When the interlayer insulating film 8 and the upper pixel electrode 9 are provided, the potential of the upper pixel electrode 9 can be controlled by applying appropriate waveforms to the gate wiring 2 ′ and the source wiring 4 ′, and display such as electronic paper can be performed. It becomes possible.
（実施例１）
　本発明の実施例について、図４Ａ～図４Ｃを用いて説明する。図２に示す素子を、図４Ａ～図４Ｃの工程によって作製した。まず初めに、絶縁基板１であるＰＥＮ上に、蒸着によってＡｌを５０ｎｍ成膜し、フォトリソおよびウェットエッチによってゲート電極２、キャパシタ電極１０を形成した（図４Ａ）。次に、ポリビニルフェノール溶液をスピンコートし、１５０℃で焼成することにより、ゲート絶縁膜３としてポリビニルフェノールを１μｍ形成した（図４Ａ）。さらに、ソース電極４、ソース配線４’、ドレイン電極５、画素電極５’として、Ａｇインクを反転印刷し１８０℃で焼成することによってパターンを形成した（図４Ｂ）。さらに、ポリチオフェン溶液（粘度１００ｍＰａ・ｓ）をフレキソ印刷し、１００℃で焼成することにより、半導体層６を形成した（図４Ｃ）。 (Example 1)
An embodiment of the present invention will be described with reference to FIGS. 4A to 4C. The device shown in FIG. 2 was fabricated by the steps of FIGS. 4A to 4C. First, an Al film having a thickness of 50 nm was formed by vapor deposition on the PEN which is the insulating substrate 1, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching (FIG. 4A). Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C., thereby forming 1 μm of polyvinylphenol as the gate insulating film 3 (FIG. 4A). Furthermore, as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′, a pattern was formed by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 4B). Further, a polythiophene solution (viscosity 100 mPa · s) was flexographically printed and baked at 100 ° C., thereby forming a semiconductor layer 6 (FIG. 4C).
　こうして作製した薄膜トランジスタの電流ばらつきを調べたところ、後述する比較例１のばらつきの約半分になった。 When the current variation of the thin film transistor thus fabricated was examined, it was about half of the variation of Comparative Example 1 described later.
（実施例２）
　本発明の実施例について、図６Ａ～図６Ｃを用いて説明する。図５に示す素子を、図６Ａ～図６Ｃの工程によって作製した。まず初めに、絶縁基板１であるＰＥＮ上に、蒸着によってＡｌを５０ｎｍ成膜し、フォトリソおよびウェットエッチによってゲート電極２を形成した（図６Ａ）。次に、ポリビニルフェノール溶液をスピンコートし、１５０℃で焼成することにより、ゲート絶縁膜３としてポリビニルフェノールを１μｍ形成した（図６Ａ）。さらに、ソース電極４、ソース配線４’、ドレイン電極５、画素電極５’として、Ａｇインクを反転印刷し１８０℃で焼成することによってパターンを形成した（図６Ｂ）。さらに、ポリチオフェン溶液（粘度１００ｍＰａ・ｓ）をフレキソ印刷し、１００℃で焼成することにより、半導体層６を形成した（図６Ｃ）。 (Example 2)
An embodiment of the present invention will be described with reference to FIGS. 6A to 6C. The device shown in FIG. 5 was fabricated by the steps of FIGS. 6A to 6C. First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 was formed by photolithography and wet etching (FIG. 6A). Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3 (FIG. 6A). Furthermore, as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′, a pattern was formed by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 6B). Further, the polythiophene solution (viscosity 100 mPa · s) was flexographically printed and baked at 100 ° C., thereby forming the semiconductor layer 6 (FIG. 6C).
　こうして作製した薄膜トランジスタの電流ばらつきを調べたところ、後述する比較例２のばらつきの約半分になった。 When the current variation of the thin film transistor thus fabricated was examined, it was about half of the variation of Comparative Example 2 described later.
（実施例３）
　本発明の実施例について、図１０Ａ～図１０Ｄを用いて説明する。図８に示す素子を、図１０Ａ～図１０Ｄの工程によって作製した。まず初めに、絶縁基板１であるＰＥＮ上に、蒸着によってＡｌを５０ｎｍ成膜し、フォトリソおよびウェットエッチによってゲート電極２、キャパシタ電極１０を形成した（図１０Ａ）。次に、ポリビニルフェノール溶液をスピンコートし、１５０℃で焼成することにより、ゲート絶縁膜３としてポリビニルフェノールを１μｍ形成した（図１０Ａ）。さらに、ソース電極４、ソース配線４’、ドレイン電極５、画素電極５’として、Ａｇインクを反転印刷し１８０℃で焼成することによってパターンを形成した（図１０Ｂ）。さらに、ポリチオフェン溶液（粘度１０ｍＰａ・ｓ）をフレキソ印刷し、１００℃で焼成することにより、半導体層６を形成した（図１０Ｃ～図１０Ｄ）。 (Example 3)
An embodiment of the present invention will be described with reference to FIGS. 10A to 10D. The element shown in FIG. 8 was fabricated by the steps of FIGS. 10A to 10D. First, an Al film having a thickness of 50 nm was formed on the PEN as the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching (FIG. 10A). Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3 (FIG. 10A). Further, a pattern was formed as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′ by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 10B). Further, a polythiophene solution (viscosity 10 mPa · s) was flexographically printed and baked at 100 ° C. to form the semiconductor layer 6 (FIGS. 10C to 10D).
　こうして作製した薄膜トランジスタの電流ばらつきを調べたところ、後述する比較例１のばらつきの約３分の１になった。 When the current variation of the thin film transistor thus fabricated was examined, it was about one third of the variation of Comparative Example 1 described later.
（実施例４）
　本発明の実施例について、図１２Ａ～図１２Ｄを用いて説明する。図１１に示す素子を、図１２Ａ～図１２Ｃの工程によって作製した。まず初めに、絶縁基板１であるＰＥＮ上に、蒸着によってＡｌを５０ｎｍ成膜し、フォトリソおよびウェットエッチによってゲート電極２を形成した（図１２Ａ）。次に、ポリビニルフェノール溶液をスピンコートし、１５０℃で焼成することにより、ゲート絶縁膜３としてポリビニルフェノールを１μｍ形成した（図１２Ａ）。さらに、ソース電極４、ソース配線４’、ドレイン電極５、画素電極５’として、Ａｇインクを反転印刷し１８０℃で焼成することによってパターンを形成した（図１２Ｂ）。さらに、ポリチオフェン溶液（粘度１０ｍＰａ・ｓ）をフレキソ印刷し、１００℃で焼成することにより、半導体層６を形成した（図１２Ｃ～図１２Ｄ）。 Example 4
An embodiment of the present invention will be described with reference to FIGS. 12A to 12D. The device shown in FIG. 11 was fabricated by the steps of FIGS. 12A to 12C. First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 was formed by photolithography and wet etching (FIG. 12A). Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3 (FIG. 12A). Furthermore, as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′, a pattern was formed by performing reverse printing of Ag ink and baking at 180 ° C. (FIG. 12B). Further, a polythiophene solution (viscosity 10 mPa · s) was flexographically printed and baked at 100 ° C. to form the semiconductor layer 6 (FIGS. 12C to 12D).
　こうして作製した薄膜トランジスタの電流ばらつきを調べたところ、後述する比較例２のばらつきの約３分の１になった。 When the current variation of the thin film transistor thus fabricated was examined, it was about one third of the variation of Comparative Example 2 described later.
（比較例１）
　比較例について、図１４Ａ～図１４Ｃを用いて説明する。図１４Ａに示す素子を目指して、図４Ａ～図４Ｃと類似の工程によって作製した。まず初めに、絶縁基板１であるＰＥＮ上に、蒸着によってＡｌを５０ｎｍ成膜し、フォトリソおよびウェットエッチによってゲート電極２、キャパシタ電極１０を形成した。次に、ポリビニルフェノール溶液をスピンコートし、１５０℃で焼成することにより、ゲート絶縁膜３としてポリビニルフェノールを１μｍ形成した。さらに、ソース電極４、ソース配線４’、ドレイン電極５、画素電極５’として、Ａｇインクを反転印刷し１８０℃で焼成することによってパターンを形成した。さらに、ポリチオフェン溶液（粘度１００ｍＰａ・ｓ）をフレキソ印刷し、１００℃で焼成することにより、半導体層６を形成した。 (Comparative Example 1)
A comparative example will be described with reference to FIGS. 14A to 14C. Aiming at the device shown in FIG. 14A, it was fabricated by a process similar to that shown in FIGS. 4A to 4C. First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching. Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3. Further, a pattern was formed as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′ by performing reverse printing of Ag ink and baking at 180 ° C. Furthermore, a semiconductor layer 6 was formed by flexographic printing a polythiophene solution (viscosity 100 mPa · s) and firing at 100 ° C.
　こうして作製した薄膜トランジスタには、半導体パターンの位置ずれ（図１４Ｂ、図１４Ｃ）によると思われる電流ばらつきが発生した。 In the thin film transistor thus fabricated, current variations that were thought to be caused by misalignment of the semiconductor pattern (FIGS. 14B and 14C) occurred.
（比較例２）
　比較例について、図１５Ａ～図１５Ｃを用いて説明する。図１５Ａに示す素子を目指して、図６Ａ～図６Ｃと類似の工程によって作製した。まず初めに、絶縁基板１であるＰＥＮ上に、蒸着によってＡｌを５０ｎｍ成膜し、フォトリソおよびウェットエッチによってゲート電極２、キャパシタ電極１０を形成した。次に、ポリビニルフェノール溶液をスピンコートし、１５０℃で焼成することにより、ゲート絶縁膜３としてポリビニルフェノールを１μｍ形成した。さらに、ソース電極４、ソース配線４’、ドレイン電極５、画素電極５’として、Ａｇインクを反転印刷し１８０℃で焼成することによってパターンを形成した。さらに、ポリチオフェン溶液（粘度１０ｍＰａ・ｓ）をフレキソ印刷し、１００℃で焼成することにより、半導体層６を形成した。 (Comparative Example 2)
A comparative example will be described with reference to FIGS. 15A to 15C. Aiming at the device shown in FIG. 15A, it was fabricated by a process similar to FIGS. 6A to 6C. First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching. Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3. Further, a pattern was formed as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 5 ′ by performing reverse printing of Ag ink and baking at 180 ° C. Furthermore, the semiconductor layer 6 was formed by carrying out flexographic printing of the polythiophene solution (viscosity 10 mPa * s), and baking at 100 degreeC.
　こうして作製した薄膜トランジスタには、半導体パターン幅のばらつき（図１５Ｂ、図１５Ｃ）によると思われる電流ばらつきが発生した。 In the thin film transistor thus fabricated, current variations that appear to be due to variations in the semiconductor pattern width (FIGS. 15B and 15C) occurred.
　以上の説明から理解できるように、本発明には、以下の効果がある。１つには、ソース電極とドレイン電極との間隙が、間隔が一定の第１の領域と間隔が漸増する第２の領域とを有し、第１の領域の全体と、第２の領域の一部とを含むように半導体パターンを形成することにより、アライメントずれがチャネル幅に与える影響を小さくできる。もう１つには、ソース電極とドレイン電極との間隙のうち、第２の領域に印刷された半導体が、第１の領域に吸収されることによって、チャネル幅が第１の領域でほぼ決定されるようになり、アライメントずれやパターン幅ばらつきの影響を小さくできる。第２の領域に存在する部分のソース電極とドレイン電極との間隙と半導体印刷パターンとの重なりが鋭角を有することにより、半導体の移動がよりスムーズになる。 As can be understood from the above description, the present invention has the following effects. For example, the gap between the source electrode and the drain electrode includes a first region having a constant interval and a second region in which the interval gradually increases. The entire first region and the second region By forming the semiconductor pattern so as to include a part, the influence of the misalignment on the channel width can be reduced. The other is that the semiconductor printed in the second region in the gap between the source electrode and the drain electrode is absorbed by the first region, so that the channel width is substantially determined in the first region. As a result, the effects of misalignment and pattern width variations can be reduced. Since the overlap between the gap between the source electrode and the drain electrode in the second region and the semiconductor print pattern has an acute angle, the movement of the semiconductor becomes smoother.
　本発明は、液晶表示装置、電子ペーパー、有機ＥＬ表示装置等の薄膜トランジスタに適用可能である。 The present invention can be applied to thin film transistors such as liquid crystal display devices, electronic paper, and organic EL display devices.
１　　…　絶縁基板
２　　…　ゲート電極
２’　…　ゲート配線
３　　…　ゲート絶縁膜
４　　…　ソース電極
４’　…　ソース配線
５　　…　ドレイン電極
５’　…　画素電極
６　　…　半導体パターン
６’　…　半導体の印刷パターン
７　　…　封止層
８　　…　層間絶縁膜
９　　…　上部画素電極
１０　　…　キャパシタ電極
１０’　…　キャパシタ配線 DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Gate electrode 2 '... Gate wiring 3 ... Gate insulating film 4 ... Source electrode 4' ... Source wiring 5 ... Drain electrode 5 '... Pixel electrode 6 ... Semiconductor pattern 6' ... Semiconductor printed pattern 7 ... Sealing Stop layer 8 ... Interlayer insulating film 9 ... Upper pixel electrode 10 ... Capacitor electrode 10 '... Capacitor wiring

Claims (9)

  1. 　絶縁基板上に、ゲート電極と、ゲート絶縁膜と、平面視で前記ゲート電極と重なる領域に互いの間隙を有するソース電極およびドレイン電極とを、順に積層されるように有し、前記間隙に領域を有する半導体パターンを有する薄膜トランジスタであって、
    　前記間隙が、間隔が一定の第１の領域と間隔が漸増する第２の領域とを有し、前記半導体パターンが、間隔が一定の領域の全体と間隔が漸増する領域の一部とを含む形状であることを特徴とする薄膜トランジスタ。     A gate electrode, a gate insulating film, and a source electrode and a drain electrode having a mutual gap in a region overlapping with the gate electrode in plan view are stacked in order on an insulating substrate, and the region in the gap A thin film transistor having a semiconductor pattern comprising:
    The gap includes a first region having a constant interval and a second region having a gradually increasing interval, and the semiconductor pattern includes the entire region having a constant interval and a part of the region having a gradually increasing interval. A thin film transistor having a shape.
  2. 　前記ゲート電極がゲート配線に接続され、前記ソース電極がソース配線に接続された、マトリクス状の薄膜トランジスタであって、前記半導体パターンが、前記ソース配線に沿った等幅ストライプ形状であり、複数の薄膜トランジスタの半導体がつながって成ることを特徴とする請求項１記載の薄膜トランジスタ。 A thin film transistor in the form of a matrix in which the gate electrode is connected to a gate wiring and the source electrode is connected to the source wiring, wherein the semiconductor pattern has a uniform width stripe shape along the source wiring, and a plurality of thin film transistors 2. The thin film transistor according to claim 1, wherein the semiconductors are connected to each other.
  3. 　絶縁基板上に、ゲート電極と、ゲート絶縁膜と、平面視で前記ゲート電極と重なる領域に互いの間隙を有するソース電極およびドレイン電極とを、順に積層されるように有し、前記間隙に領域を有する半導体パターンを有する薄膜トランジスタであって、
    　前記間隙が、間隔が一定の第１の領域と間隔が漸増する第２の領域とを有し、前記半導体パターンが、前記第１の領域には形成されており、前記第２の領域には必ずしも形成されていないことを特徴とする薄膜トランジスタ。     A gate electrode, a gate insulating film, and a source electrode and a drain electrode having a mutual gap in a region overlapping with the gate electrode in plan view are stacked in order on an insulating substrate, and the region in the gap A thin film transistor having a semiconductor pattern comprising:
    The gap includes a first region having a constant interval and a second region in which the interval gradually increases, and the semiconductor pattern is formed in the first region. A thin film transistor which is not necessarily formed.
  4. 　前記ゲート電極がゲート配線に接続され、前記ソース電極がソース配線に接続された、マトリクス状の薄膜トランジスタであって、前記半導体パターンが、前記ソース配線に沿ったストライプ形状であり、複数の薄膜トランジスタの半導体がつながって成ることを特徴とする請求項３記載の薄膜トランジスタ。 A thin film transistor having a matrix shape in which the gate electrode is connected to a gate wiring and the source electrode is connected to the source wiring, wherein the semiconductor pattern has a stripe shape along the source wiring, and a plurality of thin film transistor semiconductors The thin film transistor according to claim 3, wherein the thin film transistors are connected.
  5. 　絶縁基板上に、ゲート電極と、ゲート絶縁膜と、平面視で前記ゲート電極と重なる領域に互いの間隙を有するソース電極およびドレイン電極とを、順に積層するように形成する工程と、前記間隙に領域を有する半導体パターンを印刷する工程とを少なくとも有する薄膜トランジスタの製造方法であって、
    　前記間隙が、間隔が一定の第１の領域と間隔が漸増する第２の領域とを有し、前記半導体パターンの印刷を、前記第１の領域の全体と前記第２の領域の一部とを含むように行うことを特徴とする薄膜トランジスタの製造方法。     Forming a gate electrode, a gate insulating film, and a source electrode and a drain electrode having a gap in a region overlapping with the gate electrode in plan view on the insulating substrate so as to be sequentially stacked; A method of manufacturing a thin film transistor having at least a step of printing a semiconductor pattern having a region,
    The gap includes a first region having a constant interval and a second region having a gradually increasing interval, and printing of the semiconductor pattern is performed between the entire first region and a part of the second region. A method for producing a thin film transistor, characterized by comprising:
  6. 　前記半導体パターンの印刷パターンが、ソース配線に沿った等幅ストライプ形状であることを特徴とする請求項５記載の薄膜トランジスタの製造方法。 6. The method of manufacturing a thin film transistor according to claim 5, wherein the printed pattern of the semiconductor pattern has a uniform width stripe shape along the source wiring.
  7. 　前記第１の領域の全体と前記第２の領域の一部とを含むように印刷された前記半導体パターンの前記印刷パターンのうち、前記第２の領域に印刷された半導体が、前記第１の領域に吸収されることを特徴とする請求項５または６記載の薄膜トランジスタの製造方法。 Of the printed pattern of the semiconductor pattern printed so as to include the entire first region and a part of the second region, the semiconductor printed in the second region is the first region. 7. The method for manufacturing a thin film transistor according to claim 5, wherein the thin film transistor is absorbed in the region.
  8. 　前記第２の領域の前記間隙と、前記半導体パターンの前記印刷パターンとの重なりが、鋭角を有することを特徴とする請求項５または６記載の薄膜トランジスタの製造方法。 7. The method of manufacturing a thin film transistor according to claim 5, wherein an overlap between the gap in the second region and the printed pattern of the semiconductor pattern has an acute angle.
  9. 　前記第２の領域の前記間隙と、前記半導体パターンの前記印刷パターンとの重なりが、鋭角を有することを特徴とする請求項７記載の薄膜トランジスタの製造方法。 The method of manufacturing a thin film transistor according to claim 7, wherein the gap between the second region and the printed pattern of the semiconductor pattern has an acute angle.
PCT/JP2013/005126 2012-09-26 2013-08-29 Thin-film transistor and method for producing same WO2014049968A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012212533A JP2014067884A (en) 2012-09-26 2012-09-26 Thin film transistor and manufacturing method of the same
JP2012-212533 2012-09-26

Publications (1)

Publication Number Publication Date
WO2014049968A1 true WO2014049968A1 (en) 2014-04-03

Family

ID=50387417

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/005126 WO2014049968A1 (en) 2012-09-26 2013-08-29 Thin-film transistor and method for producing same

Country Status (3)

Country Link
JP (1) JP2014067884A (en)
TW (1) TWI617030B (en)
WO (1) WO2014049968A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6627213B2 (en) * 2014-10-30 2020-01-08 凸版印刷株式会社 Bottom-gate / bottom-contact thin film transistor, method of manufacturing bottom-gate / bottom-contact thin film transistor, and image display device
JP6711350B2 (en) * 2015-04-22 2020-06-17 凸版印刷株式会社 Substrate for forming thin film transistor array, substrate for image display device, and method for manufacturing substrate for forming thin film transistor array

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005072135A (en) * 2003-08-21 2005-03-17 Nec Lcd Technologies Ltd Method of manufacturing liquid crystal display and thin film transistor
JP2006352083A (en) * 2005-05-18 2006-12-28 Ricoh Co Ltd Organic thin film transistor and active matrix display device
JP2008235861A (en) * 2007-02-21 2008-10-02 Toppan Printing Co Ltd Thin film transistor array, method of manufacturing the same, and active matrix display using the same
JP2008270744A (en) * 2007-03-28 2008-11-06 Toppan Printing Co Ltd Thin-film transistor array, manufacturing method of thin-film transistor array, and active matrix display

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100352040C (en) * 2004-04-17 2007-11-28 鸿富锦精密工业（深圳）有限公司 Low temperature polysilicon thin film electric crystal base board and its producing method
CN101562198A (en) * 2009-05-27 2009-10-21 友达光电股份有限公司 Thin-film transistor structure and production method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005072135A (en) * 2003-08-21 2005-03-17 Nec Lcd Technologies Ltd Method of manufacturing liquid crystal display and thin film transistor
JP2006352083A (en) * 2005-05-18 2006-12-28 Ricoh Co Ltd Organic thin film transistor and active matrix display device
JP2008235861A (en) * 2007-02-21 2008-10-02 Toppan Printing Co Ltd Thin film transistor array, method of manufacturing the same, and active matrix display using the same
JP2008270744A (en) * 2007-03-28 2008-11-06 Toppan Printing Co Ltd Thin-film transistor array, manufacturing method of thin-film transistor array, and active matrix display

Also Published As

Publication number Publication date
TW201413970A (en) 2014-04-01
JP2014067884A (en) 2014-04-17
TWI617030B (en) 2018-03-01

Similar Documents

Publication Publication Date Title
JP5369367B2 (en) Thin film transistor and manufacturing method thereof
JP5365007B2 (en) Thin film transistor array and manufacturing method thereof
JP4946286B2 (en) Thin film transistor array, image display device using the same, and driving method thereof
JP6028642B2 (en) Thin film transistor array
WO2019146264A1 (en) Display device and production method therefor
JP5990889B2 (en) Electrophoretic display and manufacturing method thereof
JP2010003723A (en) Thin-film transistor, thin-film transistor array and image display
JP2016146422A (en) Display device
JP2007311377A (en) Manufacturing method of thin-film transistor, thin-film transistor, and display
JP2007134482A (en) Thin film transistor device, its manufacturing method, thin film transistor array using the same and thin film transistor display
JP5292805B2 (en) Thin film transistor array and manufacturing method thereof
US20090224247A1 (en) Liquid crystal display device
JP5103742B2 (en) THIN FILM TRANSISTOR DEVICE, ITS MANUFACTURING METHOD, THIN FILM TRANSISTOR ARRAY AND THIN FILM TRANSISTOR DISPLAY
JP6402713B2 (en) THIN FILM TRANSISTOR ARRAY, ITS MANUFACTURING METHOD, IMAGE DISPLAY DEVICE AND DISPLAY METHOD
WO2014049968A1 (en) Thin-film transistor and method for producing same
US8257992B2 (en) Method of fabricating a pixel array
JP6127425B2 (en) Laminated structure, thin film transistor array, and manufacturing method thereof
JP2008008963A (en) Display panel
JP5135891B2 (en) Organic TFT element and organic EL display panel using the same
JP5741134B2 (en) Electrophoretic display device and manufacturing method thereof
WO2016208414A1 (en) Element substrate, method for producing element substrate and display device
JP6451054B2 (en) THIN FILM TRANSISTOR ARRAY, ITS MANUFACTURING METHOD, AND IMAGE DISPLAY DEVICE
CN102124568B (en) Electronic device comprising static induction transistor and thin film transistor, method of manufacturing an electronic device and display panel
WO2020059026A1 (en) Display device and manufacturing method of display device
JP2016171282A (en) Thin film transistor and manufacturing method of the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13840304

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13840304

Country of ref document: EP

Kind code of ref document: A1