WO2017018203A1 - Display device and image pickup device - Google Patents

Display device and image pickup device Download PDF

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Publication number
WO2017018203A1
WO2017018203A1 PCT/JP2016/070574 JP2016070574W WO2017018203A1 WO 2017018203 A1 WO2017018203 A1 WO 2017018203A1 JP 2016070574 W JP2016070574 W JP 2016070574W WO 2017018203 A1 WO2017018203 A1 WO 2017018203A1
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WIPO (PCT)
Prior art keywords
semiconductor layer
electrode
thin film
insulating film
display device
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PCT/JP2016/070574
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French (fr)
Japanese (ja)
Inventor
真央 勝原
僚 佐々木
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ソニー株式会社
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Publication of WO2017018203A1 publication Critical patent/WO2017018203A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure relates to a display device and an imaging device including, for example, an organic thin film transistor (TFT: Thin Film Transistor).
  • TFT organic thin film transistor
  • TFT organic TFT
  • the organic TFT is soluble in a solvent and can be formed by a low-cost process such as coating and printing.
  • Patent Document 1 a method of forming a light shielding layer using metal or black resist in the backplane has been proposed.
  • a first display device includes a plurality of pixels and a thin film transistor provided for each pixel.
  • the thin film transistor is disposed to face the first electrode and the first electrode with an insulating film interposed therebetween.
  • a light absorption layer made of an organic semiconductor is disposed apart from the semiconductor layer of the thin film transistor. Accordingly, even when light emitted from the pixel, illumination light from the backlight, external light, or the like enters the thin film transistor, the incident light is absorbed by the light absorption layer and is prevented from reaching the semiconductor layer.
  • a second display device includes a plurality of pixels and a thin film transistor provided for each pixel.
  • the thin film transistor is disposed opposite to the first electrode and the first electrode, and is an organic semiconductor.
  • the insulating film formed between the semiconductor layer of the thin film transistor and the first electrode locally includes a thin film portion having a small thickness.
  • a first imaging device includes a plurality of pixels and a thin film transistor provided for each pixel, and the thin film transistor is disposed to face the first electrode and the first electrode with an insulating film interposed therebetween.
  • a light absorption layer made of an organic semiconductor is disposed apart from the semiconductor layer of the thin film transistor.
  • the incident light is absorbed by the light absorption layer and is prevented from reaching the semiconductor layer.
  • a second imaging device includes a plurality of pixels and a thin film transistor provided for each pixel.
  • the thin film transistor is disposed opposite to the first electrode and the first electrode, and is an organic semiconductor.
  • the insulating film formed between the semiconductor layer of the thin film transistor and the first electrode locally includes a thin film portion having a small thickness. Accordingly, even when a part of the received light enters the thin film transistor, the incident light is suppressed from reaching the semiconductor layer using the insulating film as a waveguide.
  • the light absorption layer made of an organic semiconductor is disposed apart from the semiconductor layer of the thin film transistor, so that even when light enters the thin film transistor, The arrival of incident light to the semiconductor layer can be suppressed.
  • a semiconductor layer including an organic semiconductor threshold fluctuation or the like may occur due to light incidence, but the threshold fluctuation due to incident light can be suppressed by arranging the light absorption layer as described above. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT.
  • the insulating film formed between the semiconductor layer of the thin film transistor and the first electrode locally includes a thin film portion having a small thickness, so that the thin film transistor can receive light. Even when light enters, the arrival of this incident light to the semiconductor layer can be suppressed.
  • a semiconductor layer including an organic semiconductor threshold fluctuation or the like may occur due to light incidence.
  • the insulating film includes the thin film portion as described above, threshold fluctuation due to incident light can be suppressed. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT.
  • the light absorption layer made of an organic semiconductor is arranged apart from the semiconductor layer of the thin film transistor, so that even when light is incident on the thin film transistor, The arrival of incident light to the semiconductor layer can be suppressed.
  • a semiconductor layer including an organic semiconductor threshold fluctuation or the like may occur due to light incidence, but the threshold fluctuation due to incident light can be suppressed by arranging the light absorption layer as described above. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT.
  • the insulating film formed between the semiconductor layer of the thin film transistor and the first electrode includes a thin film portion having a small thickness locally, so that the thin film transistor can receive light. Even when light enters, the arrival of this incident light to the semiconductor layer can be suppressed.
  • a semiconductor layer including an organic semiconductor threshold fluctuation or the like may occur due to light incidence.
  • the insulating film includes the thin film portion as described above, threshold fluctuation due to incident light can be suppressed. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT.
  • FIG. 3B is a cross-sectional diagram illustrating a process following the process in FIG. 3B.
  • FIG. 3C is a cross-sectional diagram illustrating a process following the process in FIG. 3C. It is sectional drawing showing the process of following FIG. 3D. It is sectional drawing showing the process of following FIG. 3E. It is sectional drawing showing the process of following FIG. 3F. It is sectional drawing showing the process of following FIG.
  • FIG. 2E It is a cross-sectional schematic diagram showing the principal part structure and light incidence of the element substrate which concerns on a comparative example. It is a cross-sectional schematic diagram showing the principal part structure and light incidence of the element substrate shown in FIG. It is sectional drawing showing the principal part structure of the element substrate which concerns on 2nd Embodiment of this indication. It is sectional drawing for demonstrating the manufacturing method of the element substrate shown in FIG. It is sectional drawing showing the process of following FIG. 8A. It is sectional drawing showing the process of following FIG. 8B. It is sectional drawing showing the process of following FIG. 8C. It is sectional drawing showing the process of following FIG. 8D. It is sectional drawing showing the process of following FIG. 9A.
  • FIG. 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 1.
  • FIG. 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 2-1.
  • FIG. 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 2-2.
  • 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 2-3.
  • FIG. 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 2-4.
  • FIG. FIG. 10 is a cross-sectional view illustrating a main part configuration of an element substrate according to Modification 2-5.
  • FIG. 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 2-6.
  • FIG. FIG. 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 3-1.
  • 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 3-2.
  • FIG. 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 3-3.
  • FIG. It is a functional block diagram showing the whole structure of the display apparatus using element substrates, such as the said embodiment. It is a functional block diagram showing the whole structure of the imaging device using element substrates, such as the said embodiment.
  • First embodiment an example of an element substrate provided with a light absorption layer made of an organic semiconductor apart from a semiconductor layer of an organic TFT
  • Second embodiment an example of an element substrate in which a thin film portion is provided on a gate insulating film of an organic TFT
  • Modification 1 Example of element substrate having both a light absorption layer and a thin film portion
  • Modified examples 2-1 to 2-6 another example of the protective film and an example in which the protective film is not formed
  • Modified examples 3-1 to 3-3 an example of another element structure of an organic TFT
  • FIG. 1 is a cross-sectional view illustrating a schematic configuration of an element substrate (element substrate 1A) according to the first embodiment of the present disclosure.
  • the element substrate 1A is a circuit substrate used for a display driving backplane or a sensor array of an imaging device, for example. The overall configuration of the display device and the imaging device will be described later.
  • circuit elements such as a plurality of TFTs 10 and wiring layers are formed over a plurality of layers and integrated.
  • FIG. 1 only one TFT 10 which is a part of the element substrate 1A and the vicinity thereof are shown.
  • the TFT 10 is, for example, an organic TFT having a so-called bottom gate type and top contact structure.
  • the TFT 10 has a first electrode (gate electrode) 12 in a selective region on the substrate 11.
  • a semiconductor layer is sandwiched between the first electrode 12 and a first insulating film (gate insulating film) 13.
  • 14A is provided.
  • the semiconductor layer 14 ⁇ / b> A is patterned in a selective region facing the first electrode 12 on the first insulating film 13.
  • a pair of second electrodes (a source electrode and a drain electrode) 15a and 15b are disposed in electrical connection with the semiconductor layer 14A.
  • the substrate 11 is made of a flexible plastic sheet such as polyimide (PI), polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), or liquid crystal polymer.
  • the substrate 11 may be a flexible metal sheet such as stainless steel (SUS), aluminum (Al), or copper (Cu) whose surface is insulated.
  • the substrate 11 may have a rigid property such as a glass substrate in addition to the material that can exhibit such flexibility.
  • the first electrode 12 controls the carrier density in the semiconductor layer 14A by the gate voltage (Vg) applied to the TFT 10, and has a function as a wiring for supplying a potential.
  • the first electrode 12 is made of, for example, aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), molybdenum (Mo), niobium ( Nb), neodymium (Nd), rubidium (Rb), rhodium (Rh), silver (Ag), tantalum (Ta), tungsten (W), copper, indium (In) and tin (Sn) A single layer film, or a laminated film composed of two or more of them.
  • the first electrode 12 is composed of a laminated film of aluminum (film thickness 50 nm) and molybdenum (film thickness 30 nm).
  • the first insulating film 13 includes an organic insulating film or an inorganic insulating film.
  • organic insulating films include polyvinylphenol (PVP), diallyl phthalate, polyimide, polymethyl methacrylate, polyvinyl alcohol (PVA), polyester, polyethylene, polycarbonate, polyamide, polyamideimide, polyetherimide, polysiloxane, polymethacrylamide. , Polyurethane, polybutadiene, polystyrene, polyvinyl chloride, nitrile rubber, acrylic rubber, butyl rubber, silicone resin, epoxy resin, phenol resin, melamine resin, urea resin, novolac resin, fluorine resin, etc. It is a film, or a mixed film or a laminated film composed of two or more of them.
  • the inorganic insulating film examples include SiN x (silicon nitride), SiO x (silicon oxide), and SiO x N y (silicon oxynitride).
  • oxides or silicate compounds such as aluminum (Al), zirconium, hafnium (Zr), and titanium (Ti) may be used.
  • a vacuum process such as a chemical vapor deposition method or a sputtering method can be used, but a coating formation using a sol-gel method or the like is also possible.
  • the thickness of the first insulating film 13 is not particularly limited, but is, for example, not less than 200 nm and not more than 1000 nm.
  • the semiconductor layer 14A forms a channel by applying a gate voltage, and includes, for example, the following organic semiconductor.
  • organic semiconductors include polypyrrole and polypyrrole substitution products, polythiophene and polythiophene substitution products, isothianaphthenes such as polyisothianaphthene, chainylene vinylenes such as polychenylene vinylene, and poly (p-phenylene vinylene).
  • derivatives of acenes include, for example, those obtained by substituting a part of carbon of acenes with an atom such as N, S, O or a functional group such as carbonyl group (triphenodioxazine, triphenodithiazine, hexacene-6, 15-quinone, perixanthenoxanthene, etc.), or hydrogens of acenes substituted with other functional groups.
  • condensed polycyclic compounds of thiophene / selenophene ring and benzene ring represented by dinaphthothienothiophene and their derivatives, metal phthalocyanines, tetrathiafulvalene and its derivatives, and those of tetrathiapentalene Derivatives, condensed ring tetracarboxylic acid diimides such as naphthalene tetracarboxylic acid diimides and anthracene tetracarboxylic acid diimides, fullerenes such as C60, C70, C76, C78, C84 and derivatives thereof, carbon nanotubes such as SWNT, merocyanine dyes And dyes such as hemicyanine dyes and derivatives thereof.
  • naphthalenetetracarboxylic acid diimides examples include naphthalene 1,4,5,8-tetracarboxylic acid diimide, N, N ′ -bis (4-trifluoromethylbenzyl) naphthalene 1,4,5,8-tetracarboxylic acid.
  • Acid diimide N, N ′ -bis (1H, 1H-perfluorooctyl), N, N ′ -bis (1H, 1H-perfluorobutyl) and N, N ′ -dioctylnaphthalene 1,4,5,8-tetracarboxylic Acid diimide derivatives, naphthalene 2,3,6,7 tetracarboxylic acid diimide and the like can be mentioned.
  • Examples of anthracene tetracarboxylic acid diimides include anthracene 2,3,6,7-tetracarboxylic acid diimide.
  • the second electrodes 15a and 15b function as source electrodes or drain electrodes. As the constituent materials of the second electrodes 15a and 15b, the same materials as those listed in the first electrode 12 can be cited. Each of these second electrodes 15a and 15b is electrically connected to the semiconductor layer 14A, and is disposed in a state of being electrically separated (separated) from the semiconductor layer 14A.
  • a protective film 16 is provided on the semiconductor layer 14A.
  • the protective film 16 is formed so as to cover a portion of the upper surface of the semiconductor layer 14A exposed from the second electrodes 15a and 15b and a light absorption layer 14B described later.
  • a second insulating film 17 is formed as an interlayer insulating film.
  • a third electrode 18 electrically connected to the second electrode 15a is formed on the second insulating film 17.
  • the third electrode 18 functions as a pixel electrode provided for each pixel, for example.
  • the constituent material of the third electrode 18 include the same materials as those listed for the first electrode 12.
  • the second insulating film 17 the same materials as those listed in the first insulating film 13 can be used.
  • a light absorption layer 14B made of an organic semiconductor is formed apart from the semiconductor layer 14A.
  • the light absorption layer 14B is made of, for example, any one of the organic semiconductor materials exemplified as the constituent material of the semiconductor layer 14A.
  • the light absorption layer 14B is preferably made of the same material as the semiconductor layer 14A and is formed in the same layer as the semiconductor layer 14A. Further, the thicknesses of the semiconductor layer 14A and the light absorption layer 14B are also substantially the same.
  • the semiconductor layer 14A and the light absorption layer 14B can be formed and patterned in a lump, and an increase in the number of steps and an increase in cost due to material addition can be suppressed.
  • the light absorption layer 14B is formed in a region not overlapping with the second electrodes 15a and 15b in the same layer as the semiconductor layer 14A. In other words, the light absorption layer 14B is not formed in a region immediately below the second electrodes 15a and 15b.
  • FIG. 2 schematically shows a planar configuration of the TFT 10 and the light absorption layer 14B.
  • the second electrode 15b is electrically connected to a wiring such as a signal line
  • the second electrode 15a is electrically connected to the third electrode 18 (not shown in FIG. 2). ing.
  • the light absorption layer 14B is formed so as to cover the non-formation regions of the second electrodes 15a and 15b in plan view.
  • FIG. 3A to 4B are cross-sectional views for explaining a method of manufacturing the element substrate 1A (TFT 10).
  • the element substrate 1A can be manufactured, for example, as follows.
  • the first electrode 12 is formed in a selective region on the substrate 11.
  • the above-described conductive film material for example, a laminated film of aluminum having a thickness of 50 nm and molybdenum having a thickness of 30 nm
  • patterning is performed into a predetermined shape by, for example, wet etching using a photolithography method.
  • a first insulating film 13 is formed on the substrate 11.
  • the above-described material for example, silicone resin
  • the above-described material is formed on the entire surface of the substrate 11 by, for example, spin coating, and then cured by heating.
  • the first insulating film 13 may be formed by, for example, an air doctor coater method, a blade coater method, a rod coater method, a knife coater method, a squeeze coater method,
  • the coating method include a reverse roll coater method, a transfer roll coater method, a gravure coater method, a kiss coater method, a cast coater method, a spray coater method, a slit orifice coater method, a calendar coater method, and a dipping method.
  • an inorganic insulating film is formed as the first insulating film 13
  • a vacuum process such as a chemical vapor deposition method or a vapor deposition polymerization method is generally used, but a coating method such as a sol-gel method is used. May be used.
  • the semiconductor layer 14A and the light absorption layer 14B are patterned on the first insulating film 13 using, for example, an inorganic resist film (inorganic resist film 210).
  • an inorganic resist film inorganic resist film 210.
  • the organic semiconductor as described above for example, DNTT (dinaphtho [2,3-b: 2 ′, 3′-f with a thickness of 20 nm] is formed on the entire surface of the substrate 11.
  • thieno [3,2-b] thiophene: dinaphthothienothiophene is formed by, for example, vacuum deposition.
  • an inorganic resist film 210 made of a metal material is patterned on the semiconductor layer 14.
  • the inorganic resist film 210 is formed in the formation region of the semiconductor layer 14A and the light absorption layer 14B. Thereafter, the semiconductor layer 14A and the light absorption layer 14B are collectively formed by patterning the semiconductor layer 14 by, for example, etching using a photolithography method. In other words, the semiconductor layer 14 is left not only in the region facing the first electrode 12 but also in the region where the second electrodes 15a and 15b are not formed. Thus, by performing patterning using an inorganic resist film, fine patterning can be performed at low cost.
  • the inorganic resist film 210 is removed as shown in FIG. 3D. However, the inorganic resist film 210 may be left without being removed.
  • the inorganic resist film 210 can function as a light shielding film. Simultaneously with the patterning of the semiconductor layer 14A, a light shielding layer made of the inorganic resist film 210 can be formed.
  • the second electrodes 15a and 15b are formed. Specifically, first, the above-described conductive film material (for example, the same material as the first electrode 12) is formed over the entire surface of the substrate 11, for example, by sputtering, and then wet etching using, for example, photolithography. Thus, patterning is performed in a predetermined shape.
  • the above-described conductive film material for example, the same material as the first electrode 12
  • the protective film 16 made of the above-described material is patterned.
  • the protective film 16 is formed so as to cover not only the semiconductor layer 14A but also the light absorption layer 14B. In this way, the TFT 10 can be formed.
  • a second insulating film 17 is formed on the formed TFT 10. Specifically, the insulating material as described above is formed over the entire surface of the substrate 11 by, eg, spin coating, and then cured by heating. Thereafter, the second insulating film 17 is patterned by, for example, etching using a photolithography method. At this time, a through hole 17a is formed in a portion of the second insulating film 17 facing the second electrode 15a.
  • the third electrode 18 is patterned so as to fill the through hole 17a. Thereby, the element substrate 1A shown in FIG. 1 is completed.
  • the element substrate 1A of the present embodiment for example, when a predetermined potential is supplied to the first electrode 12 in the TFT 10, an electric field is generated in the semiconductor layer 14A (a channel is formed), and the second electrodes 15a and 15b are connected to each other. Conduct.
  • the element substrate 1A forms a backplane for display driving, for example, a signal voltage applied to the second electrode 15b is supplied to the third electrode 18 to perform display driving.
  • an organic semiconductor is used for the semiconductor layer 14A.
  • transistor characteristics may fluctuate when light (visible light) is incident from the outside.
  • the organic semiconductor has absorption with respect to visible light, and a carrier (photocarrier) excited by light irradiation is generated to change the threshold voltage.
  • the following light may enter. That is, when a self-luminous element such as an organic electroluminescent element is provided on the third electrode 18, light emitted from such a self-luminous element enters the TFT 10. Alternatively, when a display element such as a liquid crystal display element is provided on the third electrode 18, illumination light from the backlight is incident on the TFT 10. When an electrophoretic display element or the like is provided on the third electrode 18, external light (sunlight, illumination light, etc.) may enter the TFT 10. Furthermore, when the element substrate 1A is used in a sensor array of an imaging apparatus, a part of the received light is incident on the TFT 10.
  • FIG. 5 shows a cross-sectional configuration of a main part of a TFT (TFT 100) according to a comparative example of the present embodiment.
  • TFT 100 a TFT (TFT 100) according to a comparative example of the present embodiment.
  • a first electrode 102, a first insulating film 103, a semiconductor layer 104, and second electrodes 105a and 105b are provided in this order on a substrate 101.
  • light L is incident from the outside through the non-formation region of the second electrodes 105a and 105b, reaches the semiconductor layer 104, and causes the characteristic variation as described above.
  • a light absorption layer 14B made of an organic semiconductor is provided apart from the semiconductor layer 14A of the TFT 10. Accordingly, even when light L is incident on the TFT 10 from the outside, the light L is absorbed by the light absorption layer 14B and is prevented from reaching the semiconductor layer 14A (the amount of light reaching the semiconductor layer 14A is reduced). ).
  • the semiconductor layer 14A exists on the entire surface of the substrate 11, leakage between the electrodes occurs, and normal circuit driving becomes difficult.
  • the organic semiconductor film has low adhesion to other layers (electrode layers and insulating layers), and particularly when it exists directly under a fine metal wiring, the mechanical reliability is lowered. Since the light absorption layer 14B is formed in a region that is separated from the semiconductor layer 14A and not overlapped with the second electrodes 15a and 15b, the occurrence of leakage between the electrodes and mechanical reliability can be prevented. The decrease can be suppressed.
  • the light absorption layer 14B is formed so as to cover the non-formation regions of the second electrodes 15a and 15b, so that the semiconductor layer can be suppressed while suppressing the occurrence of leakage and the deterioration of mechanical reliability as described above.
  • the amount of light reaching 14A can be more effectively reduced.
  • the light absorption layer 14B is made of the same material as the semiconductor layer 14A and is formed in the same layer, the light absorption layer 14B and the semiconductor layer 14A can be formed in the same film formation process and in the manufacturing process. It can be formed through a patterning step (can be formed all at once). Moreover, it is not necessary to prepare a new material for light shielding. That is, the light absorption layer 14B can be formed without increasing the number of steps and the cost, and the characteristic variation of the TFT 10 can be suppressed.
  • the light absorption layer 14 ⁇ / b> B made of an organic semiconductor is disposed apart from the semiconductor layer 14 ⁇ / b> A, so that even when light enters the TFT 10, The arrival of incident light to the semiconductor layer 14A can be suppressed.
  • the semiconductor layer 14A containing an organic semiconductor threshold fluctuation and the like may occur due to light incidence, but the threshold fluctuation due to incident light can be suppressed by arranging the light absorption layer 14B. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT 10.
  • FIG. 7 is a cross-sectional view illustrating a schematic configuration of an element substrate (element substrate 1B) according to the second embodiment of the present disclosure.
  • the element substrate 1B is a circuit board used for, for example, a display driving backplane or a sensor array of an imaging device, and includes a plurality of TFTs, wiring layers, Circuit elements are formed and integrated over multiple layers.
  • FIG. 7 shows only one TFT 10 which is a part of the element substrate 1B and a region in the vicinity thereof.
  • the TFT 10 is, for example, an organic TFT having a so-called bottom gate type and a top contact structure, and has a first electrode 12 and a first insulating film (first insulating film) on the substrate 11.
  • the semiconductor layer 14A is sandwiched between the film 13A).
  • a pair of second electrodes 15a and 15b are disposed in electrical connection with the semiconductor layer 14A.
  • a protective film 16 is formed on the semiconductor layer 14A.
  • a second insulating film 17 is formed on the TFT 10, and a third electrode 18 electrically connected to the second electrode 15 a is formed on the second insulating film 17.
  • the first insulating film 13A includes a thin film portion 13A1 having a locally small thickness.
  • the first insulating film 13A is provided between the first electrode 12 and the semiconductor layer 14A, and is formed in common for a plurality of pixels or separated for each pixel.
  • the first insulating film 13A is made of the same material as the organic insulating film or the inorganic insulating film listed as the constituent material of the first insulating film 13 of the first embodiment.
  • the thin film portion 13A1 is provided at least at one location with respect to one TFT 10 in the pixel, for example. Specifically, the thin film portion 13A1 is provided so as not to overlap with the semiconductor layer 14A and adjacent to the semiconductor layer 14A (adjacent in plan view). Desirably, as in the present embodiment, the thin film portion 13A1 is provided on both sides of the semiconductor layer 14A. In plan view, the thin film portion 13A1 is provided surrounding the semiconductor layer 14A (along the outer periphery of the semiconductor layer 14A). Further, it is desirable that a stepped step is formed in the vicinity of the boundary between the thin film portion 13A1 and the other portion (portion facing the semiconductor layer 14A) as shown in the figure. However, in the vicinity of the boundary, the thickness may change gently, or it may have a forward taper shape or a reverse taper shape.
  • the thickness t2 of the thin film portion 13A1 is, for example, not less than 50 nm and not more than 900 nm.
  • the width d of the thin film portion 13A1 is, for example, 2 ⁇ m or more and 50 ⁇ m or less.
  • the difference (t1 ⁇ t2) between the thickness t1 and the thickness t2 is preferably 200 nm or less, for example. This is because the flatness of each layer formed on the first insulating film 13 is ensured, and the electrode pattern or the capacitance is easily formed uniformly.
  • [Production method] 8A to 9B are views for explaining a method of manufacturing the element substrate 1B.
  • the element substrate 1B can be manufactured, for example, as follows.
  • the first electrode 12 and the first insulating film 13A are formed on the substrate 11 in the same manner as in the first embodiment.
  • inorganic resist films 211a and 211b are patterned.
  • the inorganic resist film 211a is formed in the formation region of the semiconductor layer 14A, and the inorganic resist film 211b is formed at an interval (interval corresponding to the width d) from the semiconductor layer 14A.
  • the semiconductor layer 14A is formed by patterning the semiconductor layer 14 by etching using, for example, a photolithography method.
  • the semiconductor layer 14A remains at the formation position of the inorganic resist film 211b simultaneously with the formation of the semiconductor layer 14A corresponding to the formation position of the inorganic resist film 211a.
  • the etching conditions By adjusting the etching conditions at this time, a part of the surface side of the first insulating film 13A formed under the semiconductor layer 14A is also etched. Thereby, the thin film portion 13A1 can be formed in a region of the first insulating film 13A adjacent to, for example, the semiconductor layer 14A.
  • the inorganic resist films 211a and 211b are removed. However, the inorganic resist films 211a and 211b may be left without being removed. By leaving the inorganic resist film 211b, the inorganic resist film 211b can function as a light-shielding film. Simultaneously with the patterning of the semiconductor layer 14A, it is possible to form a light shielding layer of the inorganic resist film 211b.
  • the second electrodes 15a and 15b are formed. Specifically, first, the above-described conductive film material (for example, the same material as the first electrode 12) is formed over the entire surface of the substrate 11, for example, by sputtering, and then wet etching using, for example, photolithography. Thus, patterning is performed in a predetermined shape.
  • the above-described conductive film material for example, the same material as the first electrode 12
  • the protective film 16 made of the above-described material or the like is patterned. In this way, the TFT 10 can be formed.
  • a second insulating film 17 is formed on the TFT 10 in the same manner as in the first embodiment.
  • a through hole 17a is formed in a portion of the second insulating film 17 facing the second electrode 15a.
  • the third electrode 18 is patterned so as to fill the through hole 17a. Thereby, the element substrate 1B shown in FIG. 7 is completed.
  • the element substrate 1B of the present embodiment for example, in the TFT 10, when a predetermined potential is supplied to the first electrode 12, an electric field is generated in the semiconductor layer 14A (a channel is formed), and the second electrodes 15a and 15b are connected to each other. Conduct.
  • the element substrate 1A forms a backplane for display driving, for example, a signal voltage applied to the second electrode 15b is supplied to the third electrode 18 to perform display driving.
  • an organic semiconductor is used for the semiconductor layer 14A, as in the first embodiment.
  • transistor characteristics such as a threshold voltage may fluctuate when light (visible light) is incident from the outside.
  • the thin film portion 13A1 having a locally small thickness is provided on the first insulating film 13A. Accordingly, even when light is incident on the TFT 10 from the outside, the light is suppressed from reaching the semiconductor layer 14A using the first insulating film 13A as a waveguide (the amount of light reaching the semiconductor layer 14A is reduced). .
  • the thin film portion 13A1 is provided so as not to overlap with and adjacent to the semiconductor layer 14A, the thin film portion 13A1 can be formed by adjusting the etching conditions in the patterning process of the semiconductor layer 14A in the manufacturing process. is there. Moreover, it is not necessary to prepare a new material for light shielding. That is, the thin film portion 13A1 can be formed without increasing the number of steps and the cost, and the characteristic variation of the TFT 10 can be suppressed.
  • the amount of light reaching the semiconductor layer 14A can be more effectively reduced by providing the thin film portions 13A1 on both sides of the semiconductor layer 14A (along the outer periphery of the semiconductor layer 14 in plan view). Can do.
  • the first insulating film 13 ⁇ / b> A has the thin film portion 13 ⁇ / b> A ⁇ b> 1 having a locally small thickness, so that even when light enters the TFT 10, Reaching the semiconductor layer 14A can be suppressed.
  • the semiconductor layer 14A containing an organic semiconductor threshold fluctuation and the like may occur due to light incidence, but the threshold fluctuation due to incident light can be suppressed by arranging the light absorption layer 14B. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT 10.
  • FIG. 10 illustrates a main configuration of an element substrate (element substrate 1 ⁇ / b> C) according to the first modification.
  • element substrate 1C of this modification both the light absorption layer 14B described in the first embodiment and the thin film portion 13A1 described in the second embodiment are provided.
  • a light absorption layer 14B made of an organic semiconductor is provided apart from the semiconductor layer 14A, and the first insulating film 13A has a thin film portion 13A1 with a small thickness locally. Also good. That is, the thin film portion 13A1 is disposed between the semiconductor layer 14A and the light absorption layer 14B. Even in such a case, effects equivalent to or higher than those of the first and second embodiments can be obtained.
  • FIGS. 11A and 11B show the main configuration of the element substrate according to Modifications 2-1 and 2-2.
  • the protective film 16 is formed in a selective region facing the semiconductor layer 14A and the light absorption layer 14B.
  • the formation position of the protective film 16 is not particularly limited.
  • the protective film 16 may be formed so as to cover the entire element substrate.
  • FIG. 11B a configuration in which the protective film 16 is not formed may be used.
  • the protective film 16 should just be provided as needed.
  • FIGS. 12A and 12B show the main configuration of the element substrate according to Modifications 2-3 and 2-4.
  • the protective film 16 is formed in a selective region facing the semiconductor layer 14A.
  • the place where the protective film 16 is formed is not particularly limited.
  • the protective film 16 may be formed so as to cover the entire element substrate.
  • the structure in which the protective film 16 is not formed may be sufficient.
  • the protective film 16 should just be provided as needed.
  • FIGS. 13A and 13B show the main configuration of the element substrate according to Modifications 2-5 and 2-6.
  • the location where the protective film 16 is formed is not particularly limited.
  • the protective film 16 may be formed so as to cover the entire element substrate.
  • the structure in which the protective film 16 is not formed may be sufficient.
  • the protective film 16 should just be provided as needed.
  • ⁇ Modifications 3-1 to 3-3> 14A to 14C show the main configuration of the element substrate according to the modified examples 3-1 to 3-3.
  • the element structure of the TFT 10 is exemplified by the bottom gate type and the top contact structure, but the thin film transistor of the present disclosure can also be applied to other element structures.
  • TFT 10A (FIG. 14A) having a bottom gate type and bottom contact structure
  • TFT 10B (FIG. 14B) having a top gate type and top contact structure
  • TFT 10C FIG. 14C) having a top gate type and bottom contact structure are also applied. Is possible.
  • the element substrate 1 ⁇ / b> A described in the above embodiments and the like (the same applies to the element substrates 1 ⁇ / b> B and 1 ⁇ / b> C) is preferably used as a backplane used in the display device 1.
  • Examples of the display device 1 include an organic EL display device, an LED display, a liquid crystal display device, and an electronic paper display.
  • FIG. 15 schematically shows a functional block configuration example of the display device 1.
  • the display device 1 includes a pixel driving circuit 140 including a plurality of pixels PXL in a display area S on a substrate 11, and a signal line driving circuit 120 that is a video display driver and a display area S around the display area S.
  • a scanning line driving circuit 130 is included.
  • the pixel driving circuit 140 is a driving circuit driven by, for example, an active matrix method.
  • a plurality of signal lines 120A are arranged along the column direction, and a plurality of scanning lines 130A are arranged along the row direction. An intersection between each signal line 120A and each scanning line 130A corresponds to each pixel PXL.
  • Each signal line 120A is connected to the signal line drive circuit 120, and an image signal is supplied from the signal line drive circuit 120 to each pixel PXL via the signal line 120A.
  • Each scanning line 130A is connected to a scanning line driving circuit 130, and a scanning signal is sequentially supplied from the scanning line driving circuit 130 to each pixel PXL via the scanning line 130A.
  • a light emitting element such as an organic electroluminescent element and LED (Light Emitting Diode), or a display element such as an electrophoretic display element and a liquid crystal display element, and the TFT 10 according to the above-described embodiment, etc. Is arranged.
  • the display device 1 by providing the element substrates 1 ⁇ / b> A, 1 ⁇ / b> B, 1 ⁇ / b> C and the like, it is possible to suppress the characteristic variation of the TFT and improve the reliability.
  • the element substrate 1A described in the above embodiments and the like is preferably used for a sensor array used in the imaging device 2.
  • the imaging device 2 include a solid-state imaging device such as a CMOS image sensor.
  • FIG. 16 schematically shows a functional block configuration example of the imaging apparatus 2.
  • the imaging device 2 includes, for example, a pixel unit 2a including a plurality of pixels P as an imaging area, and a circuit unit 230 including a row scanning unit 231, a horizontal selection unit 233, a column scanning unit 234, and a system control unit 232. ing.
  • the circuit unit 230 may be formed on the same substrate as the pixel unit 2a, or the circuit unit 230 and the pixel unit 2a may be stacked on the substrate.
  • the row scanning unit 231 includes a shift register, an address decoder, and the like, and is a pixel driving unit that drives each pixel P of the pixel unit 2a, for example, in units of rows.
  • a signal output from each pixel P in the pixel row that is selectively scanned by the row scanning unit 231 is supplied to the horizontal selection unit 233 through each of the vertical signal lines Lsig.
  • the horizontal selection unit 233 is configured by an amplifier, a horizontal selection switch, and the like provided for each vertical signal line Lsig.
  • the column scanning unit 234 is configured by a shift register, an address decoder, and the like, and drives the horizontal selection switches in the horizontal selection unit 233 in order while scanning.
  • the output signal of each pixel is sequentially output to the horizontal signal line 235 through each of the vertical signal lines Lsig, and is output to the outside via the horizontal signal line 235.
  • the system control unit 232 receives an externally supplied clock, data for instructing an operation mode, and the like, and outputs data such as internal information of the imaging device 2.
  • the system control unit 232 further includes a timing generator that generates various timing signals.
  • the row scanning unit 231, the horizontal selection unit 233, the column scanning unit 234, and the like are based on the various timing signals generated by the timing generator. Drive control is performed.
  • the pixel unit 2a has, for example, a plurality of pixels P that are two-dimensionally arranged in a matrix.
  • a pixel drive line Lread (row selection line, reset control line, etc.) is arranged for each pixel row, and a vertical signal line Lsig is arranged for each pixel column.
  • the pixel drive line Lread supplies a drive signal for reading a signal from the pixel.
  • One end of the pixel drive line Lread is connected to an output end corresponding to each row of the row scanning unit 231.
  • the TFT 10 of the above-described embodiment or the like is disposed.
  • the imaging device 2 by providing the element substrates 1A, 1B, 1C and the like, it is possible to suppress the characteristic variation of the TFT and improve the reliability.
  • the effect demonstrated in the said embodiment etc. is an example, The other effect may be sufficient and the other effect may be included.
  • the present disclosure may be configured as follows. (1) A plurality of pixels, and a thin film transistor provided for each pixel, The thin film transistor A first electrode; A semiconductor layer disposed opposite to the first electrode via an insulating film and including an organic semiconductor; A second electrode electrically connected to the semiconductor layer; A display device that is disposed separately from the semiconductor layer and has a light absorption layer made of an organic semiconductor. (2) The said light absorption layer is comprised from the same material as the said semiconductor layer. The display apparatus as described in said (1). (3) The display device according to (1) or (2), wherein the light absorption layer is formed in the same layer as the semiconductor layer. (4) The display device according to any one of (1) to (3), wherein the light absorption layer is formed in a region not overlapping with the second electrode.
  • a plurality of pixels, and a thin film transistor provided for each pixel, The thin film transistor A first electrode; A semiconductor layer disposed opposite to the first electrode and including an organic semiconductor; An insulating film formed between the first electrode and the semiconductor layer; A second electrode electrically connected to the semiconductor layer, The insulating film includes a thin film portion having a locally small thickness.
  • the display device according to (9), wherein the thin film portion is formed along an outer periphery of the semiconductor layer.
  • a plurality of pixels, and a thin film transistor provided for each pixel The thin film transistor A first electrode; A semiconductor layer disposed opposite to the first electrode via an insulating film and including an organic semiconductor; A second electrode electrically connected to the semiconductor layer; An imaging device that is disposed separately from the semiconductor layer and has a light absorption layer made of an organic semiconductor.
  • (12) A plurality of pixels, and a thin film transistor provided for each pixel, The thin film transistor A first electrode; A semiconductor layer disposed opposite to the first electrode and including an organic semiconductor; An insulating film formed between the first electrode and the semiconductor layer; A second electrode electrically connected to the semiconductor layer, The insulating film includes a thin film portion having a locally small thickness.

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Abstract

Provided is a display device comprising a plurality of pixels and thin film transistors one of which is provided to each pixel. The thin film transistors each include the following: a first electrode; a semiconductor layer which includes an organic semiconductor and which is disposed opposing the first electrode with an insulative film interposed therebetween; and a second electrode which is electrically connected to the semiconductor layer; and a light absorbing layer which is disposed so as to be spaced apart from the semiconductor layer and which is formed from an organic semiconductor.

Description

表示装置および撮像装置Display device and imaging device
　本開示は、例えば有機薄膜トランジスタ（ＴＦＴ：Thin Film Transistor）を備えた表示装置および撮像装置に関する。 The present disclosure relates to a display device and an imaging device including, for example, an organic thin film transistor (TFT: Thin Film Transistor).
　表示装置のバックプレーンあるいは撮像装置のセンサーアレイなどに用いられるＴＦＴでは、トランジスタ特性を安定に保つことが重要である。特に、閾値電圧が変化すると、表示やセンシングといった機能に大きな影響を及ぼすことから、閾値電圧の変化を最小限にとどめることが求められる。一方で、高い柔軟性をもち、フレキシブルなデバイスへの応用が期待されるＴＦＴとして、有機半導体を用いたＴＦＴ（有機ＴＦＴ）の開発がなされている。有機ＴＦＴは、溶剤に可溶であり、塗布および印刷などの低コストのプロセスにより形成可能である。 It is important to keep transistor characteristics stable in TFTs used for backplanes of display devices or sensor arrays of imaging devices. In particular, when the threshold voltage changes, it greatly affects functions such as display and sensing. Therefore, it is required to minimize the change in threshold voltage. On the other hand, a TFT (organic TFT) using an organic semiconductor has been developed as a TFT having high flexibility and expected to be applied to a flexible device. The organic TFT is soluble in a solvent and can be formed by a low-cost process such as coating and printing.
　ところが、有機ＴＦＴを表示装置のバックプレーン等に用いた場合、自発光素子から生じた光、バックライトからの照明光あるいは外光などが半導体層（活性層）に入射することがあり、これに起因して閾値電圧の変動が生じる。そこで、バックプレーン内に、メタルあるいはブラックレジストを利用して遮光層を形成する手法が提案されている（特許文献１）。 However, when an organic TFT is used for a backplane or the like of a display device, light generated from a self-luminous element, illumination light from a backlight, or external light may enter a semiconductor layer (active layer). As a result, the threshold voltage varies. Therefore, a method of forming a light shielding layer using metal or black resist in the backplane has been proposed (Patent Document 1).
特開２００２－１０８２５０号公報JP 2002-108250 A
　しかしながら、上記特許文献１の手法では、バックプレーンに入射した光が、バックプレーン内で反射され、この反射光が半導体層に到達することで、ＴＦＴの閾値を変動させてしまう。また、遮光層を形成するために、別途材料を要すると共に、プロセス工程数が増え、コストも増す。製造プロセスの追加やコスト増大を招くことなく、トランジスタ特性の変動を抑制して、信頼性を向上させることが可能な構造の実現が望まれている。 However, in the method of Patent Document 1, light incident on the backplane is reflected in the backplane, and this reflected light reaches the semiconductor layer, thereby changing the threshold value of the TFT. In addition, a separate material is required to form the light shielding layer, the number of process steps is increased, and the cost is increased. It is desired to realize a structure capable of improving the reliability by suppressing fluctuations in transistor characteristics without adding a manufacturing process and increasing costs.
　ＴＦＴの特性変動を抑制して信頼性を向上させることが可能な表示装置および撮像装置を提供することが望ましい。 It is desirable to provide a display device and an imaging device that can improve the reliability by suppressing the characteristic variation of the TFT.
　本開示の一実施の形態の第１の表示装置は、複数の画素と、画素毎に設けられた薄膜トランジスタとを備え、薄膜トランジスタは、第１電極と、第１電極に絶縁膜を介して対向配置されると共に有機半導体を含む半導体層と、半導体層に電気的に接続された第２電極と、半導体層と離隔して配置されると共に、有機半導体から構成された光吸収層とを有するものである。 A first display device according to an embodiment of the present disclosure includes a plurality of pixels and a thin film transistor provided for each pixel. The thin film transistor is disposed to face the first electrode and the first electrode with an insulating film interposed therebetween. A semiconductor layer including an organic semiconductor; a second electrode electrically connected to the semiconductor layer; and a light absorption layer that is disposed apart from the semiconductor layer and is made of an organic semiconductor. is there.
　本開示の一実施の形態の第１の表示装置では、薄膜トランジスタの半導体層と離隔して、有機半導体から構成された光吸収層が配置されている。これにより、画素からの発光光、バックライトからの照明光あるいは外光などが薄膜トランジスタに入射した場合にも、この入射光は光吸収層によって吸収され、半導体層へ到達することが抑制される。 In the first display device according to the embodiment of the present disclosure, a light absorption layer made of an organic semiconductor is disposed apart from the semiconductor layer of the thin film transistor. Accordingly, even when light emitted from the pixel, illumination light from the backlight, external light, or the like enters the thin film transistor, the incident light is absorbed by the light absorption layer and is prevented from reaching the semiconductor layer.
　本開示の一実施の形態の第２の表示装置は、複数の画素と、画素毎に設けられた薄膜トランジスタとを備え、薄膜トランジスタは、第１電極と、第１電極と対向配置されると共に有機半導体を含む半導体層と、第１電極と半導体層との間に形成された絶縁膜と、半導体層に電気的に接続された第２電極とを有し、絶縁膜は、局所的に厚みの小さな薄膜部分を含むものである。 A second display device according to an embodiment of the present disclosure includes a plurality of pixels and a thin film transistor provided for each pixel. The thin film transistor is disposed opposite to the first electrode and the first electrode, and is an organic semiconductor. A semiconductor layer, an insulating film formed between the first electrode and the semiconductor layer, and a second electrode electrically connected to the semiconductor layer, the insulating film having a locally small thickness It includes a thin film portion.
　本開示の一実施の形態の第２の表示装置では、薄膜トランジスタの半導体層と第１電極との間に形成された絶縁膜が、局所的に厚みの小さな薄膜部分を含む。これにより、画素からの発光光、バックライトからの照明光あるいは外光などが薄膜トランジスタに入射した場合にも、この入射光が絶縁膜を導波路として半導体層へ到達することが抑制される。 In the second display device according to the embodiment of the present disclosure, the insulating film formed between the semiconductor layer of the thin film transistor and the first electrode locally includes a thin film portion having a small thickness. Thus, even when light emitted from the pixel, illumination light from the backlight, or external light enters the thin film transistor, the incident light is suppressed from reaching the semiconductor layer using the insulating film as a waveguide.
　本開示の一実施の形態の第１の撮像装置は、複数の画素と、画素毎に設けられた薄膜トランジスタとを備え、薄膜トランジスタは、第１電極と、第１電極に絶縁膜を介して対向配置されると共に有機半導体を含む半導体層と、半導体層に電気的に接続された第２電極と、半導体層と離隔して配置されると共に、有機半導体から構成された光吸収層とを有するものである。 A first imaging device according to an embodiment of the present disclosure includes a plurality of pixels and a thin film transistor provided for each pixel, and the thin film transistor is disposed to face the first electrode and the first electrode with an insulating film interposed therebetween. A semiconductor layer including an organic semiconductor; a second electrode electrically connected to the semiconductor layer; and a light absorption layer that is disposed apart from the semiconductor layer and is made of an organic semiconductor. is there.
　本開示の一実施の形態の第１の撮像装置では、薄膜トランジスタの半導体層と離隔して、有機半導体から構成された光吸収層が配置されている。これにより、受光光の一部などが薄膜トランジスタに入射した場合にも、この入射光は光吸収層によって吸収され、半導体層へ到達することが抑制される。 In the first imaging device according to an embodiment of the present disclosure, a light absorption layer made of an organic semiconductor is disposed apart from the semiconductor layer of the thin film transistor. Thus, even when part of the received light enters the thin film transistor, the incident light is absorbed by the light absorption layer and is prevented from reaching the semiconductor layer.
　本開示の一実施の形態の第２の撮像装置は、複数の画素と、画素毎に設けられた薄膜トランジスタとを備え、薄膜トランジスタは、第１電極と、第１電極と対向配置されると共に有機半導体を含む半導体層と、第１電極と半導体層との間に形成された絶縁膜と、半導体層に電気的に接続された第２電極とを有し、絶縁膜は、局所的に厚みの小さな薄膜部分を含むものである。 A second imaging device according to an embodiment of the present disclosure includes a plurality of pixels and a thin film transistor provided for each pixel. The thin film transistor is disposed opposite to the first electrode and the first electrode, and is an organic semiconductor. A semiconductor layer, an insulating film formed between the first electrode and the semiconductor layer, and a second electrode electrically connected to the semiconductor layer, the insulating film having a locally small thickness It includes a thin film portion.
　本開示の一実施の形態の第２の撮像装置では、薄膜トランジスタの半導体層と第１電極との間に形成された絶縁膜が、局所的に厚みの小さな薄膜部分を含む。これにより、受光光の一部などが薄膜トランジスタに入射した場合にも、この入射光が絶縁膜を導波路として半導体層へ到達することが抑制される。 In the second imaging device according to the embodiment of the present disclosure, the insulating film formed between the semiconductor layer of the thin film transistor and the first electrode locally includes a thin film portion having a small thickness. Accordingly, even when a part of the received light enters the thin film transistor, the incident light is suppressed from reaching the semiconductor layer using the insulating film as a waveguide.
　本開示の一実施の形態の第１の表示装置では、薄膜トランジスタの半導体層と離隔して、有機半導体から構成された光吸収層を配置したことにより、薄膜トランジスタに光が入射した場合にも、この入射光の半導体層への到達を抑制することができる。有機半導体を含む半導体層では、光入射によって閾値変動などを生じ得るが、上記のような光吸収層が配置されることで、入射光による閾値変動を抑制することができる。よって、ＴＦＴの特性変動を抑制して信頼性を向上させることが可能となる。 In the first display device according to the embodiment of the present disclosure, the light absorption layer made of an organic semiconductor is disposed apart from the semiconductor layer of the thin film transistor, so that even when light enters the thin film transistor, The arrival of incident light to the semiconductor layer can be suppressed. In a semiconductor layer including an organic semiconductor, threshold fluctuation or the like may occur due to light incidence, but the threshold fluctuation due to incident light can be suppressed by arranging the light absorption layer as described above. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT.
　本開示の一実施の形態の第２の表示装置では、薄膜トランジスタの半導体層と第１電極との間に形成された絶縁膜が、局所的に厚みの小さな薄膜部分を含むことにより、薄膜トランジスタに光が入射した場合にも、この入射光の半導体層への到達を抑制することができる。有機半導体を含む半導体層では、光入射によって閾値変動などを生じ得るが、絶縁膜が上記のような薄膜部分を含むことにより、入射光による閾値変動を抑制することができる。よって、ＴＦＴの特性変動を抑制して信頼性を向上させることが可能となる。 In the second display device according to the embodiment of the present disclosure, the insulating film formed between the semiconductor layer of the thin film transistor and the first electrode locally includes a thin film portion having a small thickness, so that the thin film transistor can receive light. Even when light enters, the arrival of this incident light to the semiconductor layer can be suppressed. In a semiconductor layer including an organic semiconductor, threshold fluctuation or the like may occur due to light incidence. However, when the insulating film includes the thin film portion as described above, threshold fluctuation due to incident light can be suppressed. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT.
　本開示の一実施の形態の第１の撮像装置では、薄膜トランジスタの半導体層と離隔して、有機半導体から構成された光吸収層を配置したことにより、薄膜トランジスタに光が入射した場合にも、この入射光の半導体層への到達を抑制することができる。有機半導体を含む半導体層では、光入射によって閾値変動などを生じ得るが、上記のような光吸収層が配置されることで、入射光による閾値変動を抑制することができる。よって、ＴＦＴの特性変動を抑制して信頼性を向上させることが可能となる。 In the first imaging device according to the embodiment of the present disclosure, the light absorption layer made of an organic semiconductor is arranged apart from the semiconductor layer of the thin film transistor, so that even when light is incident on the thin film transistor, The arrival of incident light to the semiconductor layer can be suppressed. In a semiconductor layer including an organic semiconductor, threshold fluctuation or the like may occur due to light incidence, but the threshold fluctuation due to incident light can be suppressed by arranging the light absorption layer as described above. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT.
　本開示の一実施の形態の第２の撮像装置では、薄膜トランジスタの半導体層と第１電極との間に形成された絶縁膜が、局所的に厚みの小さな薄膜部分を含むことにより、薄膜トランジスタに光が入射した場合にも、この入射光の半導体層への到達を抑制することができる。有機半導体を含む半導体層では、光入射によって閾値変動などを生じ得るが、絶縁膜が上記のような薄膜部分を含むことにより、入射光による閾値変動を抑制することができる。よって、ＴＦＴの特性変動を抑制して信頼性を向上させることが可能となる。 In the second imaging device according to the embodiment of the present disclosure, the insulating film formed between the semiconductor layer of the thin film transistor and the first electrode includes a thin film portion having a small thickness locally, so that the thin film transistor can receive light. Even when light enters, the arrival of this incident light to the semiconductor layer can be suppressed. In a semiconductor layer including an organic semiconductor, threshold fluctuation or the like may occur due to light incidence. However, when the insulating film includes the thin film portion as described above, threshold fluctuation due to incident light can be suppressed. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT.
　尚、上記内容は本開示の一例である。本開示の効果は、上述したものに限らず、他の異なる効果であってもよいし、更に他の効果を含んでいてもよい。 The above content is an example of the present disclosure. The effects of the present disclosure are not limited to those described above, and may be other different effects or may include other effects.
本開示の第１の実施の形態に係る素子基板の要部構成を表す断面図である。It is sectional drawing showing the principal part structure of the element substrate which concerns on 1st Embodiment of this indication. 図１に示した素子基板の要部構成を表す平面図である。It is a top view showing the principal part structure of the element substrate shown in FIG. 図１に示した素子基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the element substrate shown in FIG. 図３Ａに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 3A. 図３Ｂに続く工程を表す断面図である。FIG. 3B is a cross-sectional diagram illustrating a process following the process in FIG. 3B. 図３Ｃに続く工程を表す断面図である。FIG. 3C is a cross-sectional diagram illustrating a process following the process in FIG. 3C. 図３Ｄに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 3D. 図３Ｅに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 3E. 図３Ｆに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 3F. 図２Ｅに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 2E. 比較例に係る素子基板の要部構成と光入射について表す断面模式図である。It is a cross-sectional schematic diagram showing the principal part structure and light incidence of the element substrate which concerns on a comparative example. 図１に示した素子基板の要部構成と光入射について表す断面模式図である。It is a cross-sectional schematic diagram showing the principal part structure and light incidence of the element substrate shown in FIG. 本開示の第２の実施の形態に係る素子基板の要部構成を表す断面図である。It is sectional drawing showing the principal part structure of the element substrate which concerns on 2nd Embodiment of this indication. 図７に示した素子基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the element substrate shown in FIG. 図８Ａに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 8A. 図８Ｂに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 8B. 図８Ｃに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 8C. 図８Ｄに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 8D. 図９Ａに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 9A. 変形例１に係る素子基板の要部構成を表す断面図である。10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 1. 変形例２－１に係る素子基板の要部構成を表す断面図である。FIG. 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 2-1. 変形例２－２に係る素子基板の要部構成を表す断面図である。FIG. 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 2-2. 変形例２－３に係る素子基板の要部構成を表す断面図である。10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 2-3. FIG. 変形例２－４に係る素子基板の要部構成を表す断面図である。10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 2-4. FIG. 変形例２－５に係る素子基板の要部構成を表す断面図である。FIG. 10 is a cross-sectional view illustrating a main part configuration of an element substrate according to Modification 2-5. 変形例２－６に係る素子基板の要部構成を表す断面図である。10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 2-6. FIG. 変形例３－１に係る素子基板の要部構成を表す断面図である。FIG. 10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 3-1. 変形例３－２に係る素子基板の要部構成を表す断面図である。10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 3-2. FIG. 変形例３－３に係る素子基板の要部構成を表す断面図である。10 is a cross-sectional view illustrating a configuration of a main part of an element substrate according to Modification 3-3. FIG. 上記実施の形態等の素子基板を用いた表示装置の全体構成を表す機能ブロック図である。It is a functional block diagram showing the whole structure of the display apparatus using element substrates, such as the said embodiment. 上記実施の形態等の素子基板を用いた撮像装置の全体構成を表す機能ブロック図である。It is a functional block diagram showing the whole structure of the imaging device using element substrates, such as the said embodiment.
　以下、本開示における実施形態について図面を参照して詳細に説明する。尚、説明は以下の順序で行う。
１．第１の実施の形態（有機ＴＦＴの半導体層と離隔して、有機半導体からなる光吸収層を設けた素子基板の例）
２．第２の実施の形態（有機ＴＦＴのゲート絶縁膜に、薄膜部分を設けた素子基板の例）
３．変形例１（光吸収層と薄膜部分との両方をもつ素子基板の例）
４．変形例２－１～２－６（保護膜の他の例および保護膜を形成しない場合の例）
５．変形例３－１～３－３（有機ＴＦＴの他の素子構造例）
６．適用例（素子基板を備えた表示装置および撮像装置の例） Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.
1. First embodiment (an example of an element substrate provided with a light absorption layer made of an organic semiconductor apart from a semiconductor layer of an organic TFT)
2. Second embodiment (an example of an element substrate in which a thin film portion is provided on a gate insulating film of an organic TFT)
3. Modification 1 (Example of element substrate having both a light absorption layer and a thin film portion)
4). Modified examples 2-1 to 2-6 (another example of the protective film and an example in which the protective film is not formed)
5). Modified examples 3-1 to 3-3 (an example of another element structure of an organic TFT)
6). Application example (example of display device and imaging device provided with element substrate)
＜第１の実施の形態＞
［構成］
　図１は、本開示の第１の実施の形態に係る素子基板（素子基板１Ａ）の概略構成を表す断面図である。素子基板１Ａは、例えば表示駆動用のバックプレーンあるいは撮像装置のセンサーアレイ等に用いられる回路基板である。表示装置および撮像装置の全体構成については後述する。この素子基板１Ａでは、例えば複数のＴＦＴ１０および配線層等の回路要素が多層にわたって形成され、集積化されている。図１では、素子基板１Ａの一部である１つのＴＦＴ１０とその近傍の領域のみを示している。 <First Embodiment>
[Constitution]
FIG. 1 is a cross-sectional view illustrating a schematic configuration of an element substrate (element substrate 1A) according to the first embodiment of the present disclosure. The element substrate 1A is a circuit substrate used for a display driving backplane or a sensor array of an imaging device, for example. The overall configuration of the display device and the imaging device will be described later. In the element substrate 1A, for example, circuit elements such as a plurality of TFTs 10 and wiring layers are formed over a plurality of layers and integrated. In FIG. 1, only one TFT 10 which is a part of the element substrate 1A and the vicinity thereof are shown.
　ＴＦＴ１０は、例えばいわゆるボトムゲート型およびトップコンタクト構造を有する有機ＴＦＴである。ＴＦＴ１０は、基板１１上の選択的な領域に第１電極（ゲート電極）１２を有しており、この第１電極１２上には、第１絶縁膜（ゲート絶縁膜）１３を挟んで半導体層１４Ａが設けられている。半導体層１４Ａは、第１絶縁膜１３上において、第１電極１２と対向する選択的な領域にパターン形成されている。この半導体層１４Ａ上には、一対の第２電極（ソース電極およびドレイン電極）１５ａ，１５ｂが半導体層１４Ａと電気的に接続されて配設されている。 The TFT 10 is, for example, an organic TFT having a so-called bottom gate type and top contact structure. The TFT 10 has a first electrode (gate electrode) 12 in a selective region on the substrate 11. A semiconductor layer is sandwiched between the first electrode 12 and a first insulating film (gate insulating film) 13. 14A is provided. The semiconductor layer 14 </ b> A is patterned in a selective region facing the first electrode 12 on the first insulating film 13. On the semiconductor layer 14A, a pair of second electrodes (a source electrode and a drain electrode) 15a and 15b are disposed in electrical connection with the semiconductor layer 14A.
　基板１１は、例えばポリイミド（ＰＩ），ポリエチレンテレフタレート（ＰＥＴ），ポリエーテルサルフォン（ＰＥＳ），ポリエチレンナフタレート（ＰＥＮ），ポリカーボネート（ＰＣ），液晶ポリマーなどのフレキシブルなプラスチックシートからなる。あるいは、基板１１には、表面に絶縁処理が施されたステンレス（ＳＵＳ），アルミニウム（Ａｌ），銅（Ｃｕ）等のフレキシブルな金属シートが用いられてもよい。但し、基板１１は、このようなフレキシブル性を発揮し得るものの他にも、ガラス基板等のリジット性を有するものであってもよい。 The substrate 11 is made of a flexible plastic sheet such as polyimide (PI), polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), or liquid crystal polymer. Alternatively, the substrate 11 may be a flexible metal sheet such as stainless steel (SUS), aluminum (Al), or copper (Cu) whose surface is insulated. However, the substrate 11 may have a rigid property such as a glass substrate in addition to the material that can exhibit such flexibility.
　第１電極１２は、ＴＦＴ１０に印加されるゲート電圧（Ｖｇ）によって半導体層１４Ａ中のキャリア密度を制御すると共に、電位を供給する配線としての機能を有するものである。この第１電極１２は、例えばアルミニウム（Ａｌ），チタン（Ｔｉ），白金（Ｐｔ），金（Ａｕ），パラジウム（Ｐｄ），クロム（Ｃｒ），ニッケル（Ｎｉ），モリブデン（Ｍｏ），ニオブ（Ｎｂ），ネオジム（Ｎｄ），ルビジウム（Ｒｂ），ロジウム（Ｒｈ），銀（Ａｇ），タンタル（Ｔａ），タングステン（Ｗ），銅、インジウム（Ｉｎ）および錫（Ｓｎ）のうちの１種からなる単層膜、もしくはこれらのうちの２種以上からなる積層膜から構成されている。一例としては、第１電極１２は、アルミニウム（膜厚５０ｎｍ）とモリブデン（膜厚３０ｎｍ）との積層膜から構成されている。 The first electrode 12 controls the carrier density in the semiconductor layer 14A by the gate voltage (Vg) applied to the TFT 10, and has a function as a wiring for supplying a potential. The first electrode 12 is made of, for example, aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), molybdenum (Mo), niobium ( Nb), neodymium (Nd), rubidium (Rb), rhodium (Rh), silver (Ag), tantalum (Ta), tungsten (W), copper, indium (In) and tin (Sn) A single layer film, or a laminated film composed of two or more of them. As an example, the first electrode 12 is composed of a laminated film of aluminum (film thickness 50 nm) and molybdenum (film thickness 30 nm).
　第１絶縁膜１３は、有機絶縁膜または無機絶縁膜を含んで構成されている。有機絶縁膜としては、例えばポリビニルフェノール（ＰＶＰ），ジアリルフタレート，ポリイミド，ポリメタクリル酸メチル，ポリビニルアルコール（ＰＶＡ），ポリエステル，ポリエチレン，ポリカーボネート，ポリアミド，ポリアミドイミド，ポリエーテルイミド，ポリシロキサン，ポリメタクリルアミド，ポリウレタン，ポリブタジエン，ポリスチレン，ポリ塩化ビニル，ニトリルゴム，アクリルゴム，ブチルゴム，シリコーン樹脂，エポキシ樹脂，フェノール樹脂，メラミン樹脂，ウレア樹脂，ノボラック樹脂，フッ素系樹脂などのうちの１種よりなる単層膜、またはそれらのうちの２種以上よりなる混合膜もしくは積層膜である。 The first insulating film 13 includes an organic insulating film or an inorganic insulating film. Examples of organic insulating films include polyvinylphenol (PVP), diallyl phthalate, polyimide, polymethyl methacrylate, polyvinyl alcohol (PVA), polyester, polyethylene, polycarbonate, polyamide, polyamideimide, polyetherimide, polysiloxane, polymethacrylamide. , Polyurethane, polybutadiene, polystyrene, polyvinyl chloride, nitrile rubber, acrylic rubber, butyl rubber, silicone resin, epoxy resin, phenol resin, melamine resin, urea resin, novolac resin, fluorine resin, etc. It is a film, or a mixed film or a laminated film composed of two or more of them.
　無機絶縁膜としては、例えばＳｉＮx（窒化シリコン）、ＳｉＯx（酸化シリコン）あるいはＳｉＯxＮy（酸窒化シリコン）が挙げられる。あるいは、アルミニウム（Ａｌ）、ジルコニウム、ハフニウム（Ｚｒ）およびチタン（Ｔｉ）等の、酸化物またはシリケイト化合物などが用いられてもよい。これらの絶縁膜の形成方法としては化学的気相成長法やスパッタリング法等の真空プロセスを用いることができるが、ゾルゲル法等を用いた塗布形成も可能である。 Examples of the inorganic insulating film include SiN x (silicon nitride), SiO x (silicon oxide), and SiO x N y (silicon oxynitride). Alternatively, oxides or silicate compounds such as aluminum (Al), zirconium, hafnium (Zr), and titanium (Ti) may be used. As a method for forming these insulating films, a vacuum process such as a chemical vapor deposition method or a sputtering method can be used, but a coating formation using a sol-gel method or the like is also possible.
　この第１絶縁膜１３の厚みは、特に限定されないが、例えば２００ｎｍ以上１０００ｎｍ以下である。 The thickness of the first insulating film 13 is not particularly limited, but is, for example, not less than 200 nm and not more than 1000 nm.
　半導体層１４Ａは、ゲート電圧の印加によりチャネルを形成するものであり、例えば次のような有機半導体を含んで構成されている。有機半導体としては、例えば、ポリピロールおよびポリピロール置換体、ポリチオフェンおよびポリチオフェン置換体、ポリイソチアナフテンなどのイソチアナフテン類、ポリチェニレンビニレンなどのチェニレンビニレン類、ポリ（ｐ－フェニレンビニレン）などのポリ（ｐ－フェニレンビニレン）類、ポリアニリンおよびポリアニリン置換体、ポリアセチレン類、ポリジアセチレン類、ポリアズレン類、ポリピレン類、ポリカルバゾール類、ポリセレノフェン類、ポリフラン類、ポリ（ｐ－フェニレン）類、ポリインドール類、ポリピリダジン類、ポリビニルカルバゾール，ポリフエニレンスルフィド，ポリビニレンスルフィドなどのポリマーおよび多環縮合体、上述した材料中のポリマーと同じ繰返し単位を有するオリゴマー類、ナフタセン，ペンタセン，ヘキサセン，ヘプタセン，ジベンゾペンタセン，テトラベンゾペンタセン，ピレン，ジベンゾピレン，クリセン，ペリレン，コロネン，テリレン，オバレン，クオテリレンおよびサーカムアントラセンなどのアセン類、およびアセン類の誘導体などが挙げられる。アセン類の誘導体としては、例えば、アセン類の炭素の一部をＮ，Ｓ，Ｏなどの原子またはカルボニル基などの官能基に置換したもの（トリフェノジオキサジン、トリフェノジチアジン、ヘキサセン－６，１５－キノン，ペリキサンテノキサンテンなど）、またはアセン類の水素を他の官能基で置換したものが挙げられる。 The semiconductor layer 14A forms a channel by applying a gate voltage, and includes, for example, the following organic semiconductor. Examples of organic semiconductors include polypyrrole and polypyrrole substitution products, polythiophene and polythiophene substitution products, isothianaphthenes such as polyisothianaphthene, chainylene vinylenes such as polychenylene vinylene, and poly (p-phenylene vinylene). Poly (p-phenylene vinylene) s, polyaniline and polyaniline substituted products, polyacetylenes, polydiacetylenes, polyazulenes, polypyrenes, polycarbazoles, polyselenophenes, polyfurans, poly (p-phenylene) s, polyindoles Polymers, polypyridazines, polyvinylcarbazole, polyphenylene sulfide, polyvinylene sulfide and other polymers and polycyclic condensates, oligomers having the same repeating units as the polymers in the above materials, naphth Sen, pentacene, hexacene, heptacene, dibenzo pentacene, tetrabenzopentacene, pyrene, dibenzopyrene, chrysene, perylene, coronene, terylene, ovalene, acenes such quaterrylene and circumflex anthracene, and the like derivatives of acenes like. Examples of derivatives of acenes include, for example, those obtained by substituting a part of carbon of acenes with an atom such as N, S, O or a functional group such as carbonyl group (triphenodioxazine, triphenodithiazine, hexacene-6, 15-quinone, perixanthenoxanthene, etc.), or hydrogens of acenes substituted with other functional groups.
　また、この他にも、ジナフトチエノチオフェンに代表されるチオフェン／セレノフェン環とベンゼン環の縮合多環系化合物とその誘導体、金属フタロシアニン類、テトラチアフルバレンとその誘導体、テトラチアペンタレンとのその誘導体、ナフタレンテトラカルボン酸ジイミド類およびアントラセンテトラカルボン酸ジイミド類などの縮合環テトラカルボン酸ジイミド類、Ｃ６０，Ｃ７０，Ｃ７６，Ｃ７８，Ｃ８４等フラーレン類とその誘導体、ＳＷＮＴなどのカーボンナノチューブ、メロシアニン色素類およびヘミシアニン色素類などの色素とこれらの誘導体等が挙げられる。ナフタレンテトラカルボン酸ジイミド類としては、例えば、ナフタレン１，４，５，８－テトラカルボン酸ジイミド、Ｎ，Ｎ' －ビス（４－トリフルオロメチルベンジル）ナフタレン１，４，５，８－テトラカルボン酸ジイミド、Ｎ，Ｎ' －ビス（１Ｈ，１Ｈ－ペルフルオロオクチル）、Ｎ，Ｎ' －ビス（１Ｈ，１Ｈ－ペルフルオロブチル）およびＮ，Ｎ' －ジオクチルナフタレン１，４，５，８－テトラカルボン酸ジイミド誘導体、またはナフタレン２，３，６，７テトラカルボン酸ジイミドなどが挙げられる。アントラセンテトラカルボン酸ジイミド類としては、例えば、アントラセン２，３，６，７－テトラカルボン酸ジイミドなどが挙げられる。 In addition to these, condensed polycyclic compounds of thiophene / selenophene ring and benzene ring represented by dinaphthothienothiophene and their derivatives, metal phthalocyanines, tetrathiafulvalene and its derivatives, and those of tetrathiapentalene Derivatives, condensed ring tetracarboxylic acid diimides such as naphthalene tetracarboxylic acid diimides and anthracene tetracarboxylic acid diimides, fullerenes such as C60, C70, C76, C78, C84 and derivatives thereof, carbon nanotubes such as SWNT, merocyanine dyes And dyes such as hemicyanine dyes and derivatives thereof. Examples of naphthalenetetracarboxylic acid diimides include naphthalene 1,4,5,8-tetracarboxylic acid diimide, N, N ′ -bis (4-trifluoromethylbenzyl) naphthalene 1,4,5,8-tetracarboxylic acid. Acid diimide, N, N ′ -bis (1H, 1H-perfluorooctyl), N, N ′ -bis (1H, 1H-perfluorobutyl) and N, N ′ -dioctylnaphthalene 1,4,5,8-tetracarboxylic Acid diimide derivatives, naphthalene 2,3,6,7 tetracarboxylic acid diimide and the like can be mentioned. Examples of anthracene tetracarboxylic acid diimides include anthracene 2,3,6,7-tetracarboxylic acid diimide.
　第２電極１５ａ，１５ｂは、ソース電極またはドレイン電極として機能するものである。これらの第２電極１５ａ，１５ｂの構成材料としては、上記第１電極１２において列挙したものと同様のものが挙げられる。これらの第２電極１５ａ，１５ｂはそれぞれ、半導体層１４Ａに電気的に接続されると共に、半導体層１４Ａ上において互いに電気的に分離した状態で（離隔して）配設されている。 The second electrodes 15a and 15b function as source electrodes or drain electrodes. As the constituent materials of the second electrodes 15a and 15b, the same materials as those listed in the first electrode 12 can be cited. Each of these second electrodes 15a and 15b is electrically connected to the semiconductor layer 14A, and is disposed in a state of being electrically separated (separated) from the semiconductor layer 14A.
　ＴＦＴ１０では、半導体層１４Ａ上に保護膜１６が設けられている。この保護膜１６は、半導体層１４Ａの上面のうち第２電極１５ａ，１５ｂから露出した部分と、後述の光吸収層１４Ｂとを覆うように形成されている。 In the TFT 10, a protective film 16 is provided on the semiconductor layer 14A. The protective film 16 is formed so as to cover a portion of the upper surface of the semiconductor layer 14A exposed from the second electrodes 15a and 15b and a light absorption layer 14B described later.
　このＴＦＴ１０の上には、層間絶縁膜として第２絶縁膜１７が形成されている。第２絶縁膜１７上には、第２電極１５ａに電気的に接続された第３電極１８が形成されている。第３電極１８は、例えば素子基板１Ａが表示駆動用のバックプレーンとして用いられる場合には、例えば画素毎に設けられる画素電極として機能するものである。第３電極１８の構成材料としては、上記第１電極１２において列挙したものと同様のものが挙げられる。第２絶縁膜１７としては、上記第１絶縁膜１３において列挙したものと同様の材料を用いることができる。 On the TFT 10, a second insulating film 17 is formed as an interlayer insulating film. A third electrode 18 electrically connected to the second electrode 15a is formed on the second insulating film 17. For example, when the element substrate 1A is used as a backplane for display driving, the third electrode 18 functions as a pixel electrode provided for each pixel, for example. Examples of the constituent material of the third electrode 18 include the same materials as those listed for the first electrode 12. As the second insulating film 17, the same materials as those listed in the first insulating film 13 can be used.
　本実施の形態では、上記のようなＴＦＴ１０において、半導体層１４Ａと離隔して、有機半導体から構成された光吸収層１４Ｂが形成されている。光吸収層１４Ｂは、例えば、半導体層１４Ａの構成材料として例示した上記有機半導体のいずれかの材料から構成されている。但し、光吸収層１４Ｂは、図１に示したように、望ましくは、半導体層１４Ａと同一材料から構成されると共に、半導体層１４Ａと同一層内に形成されている。また、半導体層１４Ａと光吸収層１４Ｂとの厚みも略同一となる。後述する製造プロセスにおいて、半導体層１４Ａおよび光吸収層１４Ｂの成膜およびパターニングを一括して行うことができ、工程数の増大や材料追加によるコスト増大等を抑制することができる。 In the present embodiment, in the TFT 10 as described above, a light absorption layer 14B made of an organic semiconductor is formed apart from the semiconductor layer 14A. The light absorption layer 14B is made of, for example, any one of the organic semiconductor materials exemplified as the constituent material of the semiconductor layer 14A. However, as shown in FIG. 1, the light absorption layer 14B is preferably made of the same material as the semiconductor layer 14A and is formed in the same layer as the semiconductor layer 14A. Further, the thicknesses of the semiconductor layer 14A and the light absorption layer 14B are also substantially the same. In a manufacturing process to be described later, the semiconductor layer 14A and the light absorption layer 14B can be formed and patterned in a lump, and an increase in the number of steps and an increase in cost due to material addition can be suppressed.
　この光吸収層１４Ｂは、半導体層１４Ａと同層において、第２電極１５ａ，１５ｂと非重畳の領域に形成されている。換言すると、光吸収層１４Ｂは、第２電極１５ａ，１５ｂの直下の領域には形成されていない。図２に、ＴＦＴ１０と、光吸収層１４Ｂとの平面構成について模式的に示す。このように、ＴＦＴ１０では、第２電極１５ｂが、例えば信号線などの配線に電気的に接続され、第２電極１５ａが第３電極１８（図２には図示せず）に電気的に接続されている。このような構成において、光吸収層１４Ｂは、平面視的に、第２電極１５ａ，１５ｂの非形成領域を覆うように形成されている。 The light absorption layer 14B is formed in a region not overlapping with the second electrodes 15a and 15b in the same layer as the semiconductor layer 14A. In other words, the light absorption layer 14B is not formed in a region immediately below the second electrodes 15a and 15b. FIG. 2 schematically shows a planar configuration of the TFT 10 and the light absorption layer 14B. As described above, in the TFT 10, the second electrode 15b is electrically connected to a wiring such as a signal line, and the second electrode 15a is electrically connected to the third electrode 18 (not shown in FIG. 2). ing. In such a configuration, the light absorption layer 14B is formed so as to cover the non-formation regions of the second electrodes 15a and 15b in plan view.
［製造方法］
　図３Ａ～図４Ｂは、素子基板１Ａ（ＴＦＴ１０）の製造方法を説明するための断面図である。素子基板１Ａは、例えば次のようにして製造することができる。 [Production method]
3A to 4B are cross-sectional views for explaining a method of manufacturing the element substrate 1A (TFT 10). The element substrate 1A can be manufactured, for example, as follows.
　まず、図３Ａに示したように、基板１１上の選択的な領域に第１電極１２を形成する。具体的には、まず、基板１１上の全面に、上述した導電膜材料（例えば厚み５０ｎｍのアルミニウムと厚み３０ｎｍのモリブデンとの積層膜）を、例えばスパッタ法により成膜する。この後、例えばフォトリソグラフィ法を用いたウェットエッチングにより、所定の形状にパターニングする。 First, as shown in FIG. 3A, the first electrode 12 is formed in a selective region on the substrate 11. Specifically, first, the above-described conductive film material (for example, a laminated film of aluminum having a thickness of 50 nm and molybdenum having a thickness of 30 nm) is formed on the entire surface of the substrate 11 by, for example, a sputtering method. Thereafter, patterning is performed into a predetermined shape by, for example, wet etching using a photolithography method.
　続いて、図３Ｂに示したように、基板１１上に第１絶縁膜１３を形成する。具体的には、基板１１上の全面にわたって、例えばスピンコート法により、上述した材料（例えばシリコーン樹脂）を成膜した後、加熱して硬化させる。尚、第１絶縁膜１３（有機絶縁膜）の成膜手法としては、スピンコート法の他にも、例えば、エアドクタコーター法、ブレードコーター法、ロッドコーター法、ナイフコーター法、スクイズコーター法、リバースロールコーター法、トランスファーロールコーター法、グラビアコーター法、キスコーター法、キャストコーター法、スプレーコーター法、スリットオリフィスコーター法、カレンダーコーター法、浸漬法等の塗布法が挙げられる。あるいは、第１絶縁膜１３として無機絶縁膜を形成する場合には、例えば化学的気相成長法や蒸着重合法等の真空プロセスが用いられるのが一般的ではあるが、ゾルゲル法などの塗布法が用いられても構わない。 Subsequently, as shown in FIG. 3B, a first insulating film 13 is formed on the substrate 11. Specifically, the above-described material (for example, silicone resin) is formed on the entire surface of the substrate 11 by, for example, spin coating, and then cured by heating. In addition to the spin coating method, the first insulating film 13 (organic insulating film) may be formed by, for example, an air doctor coater method, a blade coater method, a rod coater method, a knife coater method, a squeeze coater method, Examples of the coating method include a reverse roll coater method, a transfer roll coater method, a gravure coater method, a kiss coater method, a cast coater method, a spray coater method, a slit orifice coater method, a calendar coater method, and a dipping method. Alternatively, when an inorganic insulating film is formed as the first insulating film 13, for example, a vacuum process such as a chemical vapor deposition method or a vapor deposition polymerization method is generally used, but a coating method such as a sol-gel method is used. May be used.
　次いで、第１絶縁膜１３上に半導体層１４Ａおよび光吸収層１４Ｂを、例えば無機レジスト膜（無機レジスト膜２１０）を用いてパターン形成する。具体的には、まず、図３Ｃに示したように、基板１１の全面にわたって、上述したような有機半導体、例えば膜厚２０ｎｍのＤＮＴＴ（dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene：ジナフトチエノチオフェン）を、例えば真空蒸着法により成膜する。続いて、半導体層１４上に、金属材料からなる無機レジスト膜２１０をパターン形成する。無機レジスト膜２１０は、半導体層１４Ａと光吸収層１４Ｂとの形成領域に形成する。この後、例えばフォトリソグラフィ法を用いたエッチングにより、半導体層１４をパターニングすることにより、半導体層１４Ａおよび光吸収層１４Ｂを一括形成する。換言すると、第１電極１２に対向する領域だけでなく、第２電極１５ａ，１５ｂの非形成領域にも半導体層１４を残存させる。このように、無機レジスト膜を用いたパターニングを行うことで、低コストで、微細なパターニングが可能となる。 Next, the semiconductor layer 14A and the light absorption layer 14B are patterned on the first insulating film 13 using, for example, an inorganic resist film (inorganic resist film 210). Specifically, first, as shown in FIG. 3C, the organic semiconductor as described above, for example, DNTT (dinaphtho [2,3-b: 2 ′, 3′-f with a thickness of 20 nm] is formed on the entire surface of the substrate 11. ] thieno [3,2-b] thiophene: dinaphthothienothiophene) is formed by, for example, vacuum deposition. Subsequently, an inorganic resist film 210 made of a metal material is patterned on the semiconductor layer 14. The inorganic resist film 210 is formed in the formation region of the semiconductor layer 14A and the light absorption layer 14B. Thereafter, the semiconductor layer 14A and the light absorption layer 14B are collectively formed by patterning the semiconductor layer 14 by, for example, etching using a photolithography method. In other words, the semiconductor layer 14 is left not only in the region facing the first electrode 12 but also in the region where the second electrodes 15a and 15b are not formed. Thus, by performing patterning using an inorganic resist film, fine patterning can be performed at low cost.
　半導体層１４Ａおよび光吸収層１４Ｂを形成した後、図３Ｄに示したように、無機レジスト膜２１０を除去する。但し、無機レジスト膜２１０は、除去せずに残してもよい。無機レジスト膜２１０をチャネルとなる半導体層１４Ａ以外の部分にも形成することにより、無機レジスト膜２１０を遮光膜として機能させることができる。半導体層１４Ａのパターニングと同時に、無機レジスト膜２１０による遮光層を形成することが可能である。 After forming the semiconductor layer 14A and the light absorption layer 14B, the inorganic resist film 210 is removed as shown in FIG. 3D. However, the inorganic resist film 210 may be left without being removed. By forming the inorganic resist film 210 in a portion other than the semiconductor layer 14A to be a channel, the inorganic resist film 210 can function as a light shielding film. Simultaneously with the patterning of the semiconductor layer 14A, a light shielding layer made of the inorganic resist film 210 can be formed.
　続いて、図３Ｅに示したように、第２電極１５ａ，１５ｂを形成する。具体的には、まず、基板１１上の全面にわたって、上述した導電膜材料（例えば、第１電極１２と同一材料）を、例えばスパッタ法により成膜した後、例えばフォトリソグラフィ法を用いたウェットエッチングにより、所定の形状にパターニングする。 Subsequently, as shown in FIG. 3E, the second electrodes 15a and 15b are formed. Specifically, first, the above-described conductive film material (for example, the same material as the first electrode 12) is formed over the entire surface of the substrate 11, for example, by sputtering, and then wet etching using, for example, photolithography. Thus, patterning is performed in a predetermined shape.
　続いて、図３Ｆに示したように、上述した材料等からなる保護膜１６をパターン形成する。この際、保護膜１６を、半導体層１４Ａだけでなく、光吸収層１４Ｂをも覆うように形成する。このようにして、ＴＦＴ１０を形成することができる。 Subsequently, as shown in FIG. 3F, the protective film 16 made of the above-described material is patterned. At this time, the protective film 16 is formed so as to cover not only the semiconductor layer 14A but also the light absorption layer 14B. In this way, the TFT 10 can be formed.
　次いで、図４Ａに示したように、形成したＴＦＴ１０上に第２絶縁膜１７を形成する。具体的には、基板１１上の全面にわたって、例えばスピンコート法により、上述したような絶縁材料を成膜した後、加熱して硬化させる。この後、例えばフォトリソグラフィ法を用いたエッチングにより、第２絶縁膜１７をパターニングする。この際、第２絶縁膜１７のうちの第２電極１５ａに対向する部分に貫通孔１７ａを形成する。 Next, as shown in FIG. 4A, a second insulating film 17 is formed on the formed TFT 10. Specifically, the insulating material as described above is formed over the entire surface of the substrate 11 by, eg, spin coating, and then cured by heating. Thereafter, the second insulating film 17 is patterned by, for example, etching using a photolithography method. At this time, a through hole 17a is formed in a portion of the second insulating film 17 facing the second electrode 15a.
　最後に、図４Ｂに示したように、第３電極１８を、貫通孔１７ａを埋め込みようにパターン形成する。これにより、図１に示した素子基板１Ａを完成する。 Finally, as shown in FIG. 4B, the third electrode 18 is patterned so as to fill the through hole 17a. Thereby, the element substrate 1A shown in FIG. 1 is completed.
［効果］
　本実施の形態の素子基板１Ａでは、例えばＴＦＴ１０において、第１電極１２に所定の電位が供給されると、半導体層１４Ａに電界が生じ（チャネルが形成され）、第２電極１５ａ，１５ｂ間が導通する。例えば、素子基板１Ａが表示駆動用のバックプレーンを成す場合には、例えば第２電極１５ｂに印加された信号電圧等が、第３電極１８に供給され、表示駆動がなされる。 [effect]
In the element substrate 1A of the present embodiment, for example, when a predetermined potential is supplied to the first electrode 12 in the TFT 10, an electric field is generated in the semiconductor layer 14A (a channel is formed), and the second electrodes 15a and 15b are connected to each other. Conduct. For example, when the element substrate 1A forms a backplane for display driving, for example, a signal voltage applied to the second electrode 15b is supplied to the third electrode 18 to perform display driving.
　本実施の形態の素子基板１Ａでは、半導体層１４Ａに有機半導体が用いられている。このような有機半導体を用いたＴＦＴ１０では、外部から光（可視光）が入射すると、トランジスタ特性が変動することがある。詳細には、有機半導体は、可視光に対する吸収を持ち、光照射によって励起されたキャリア（フォトキャリア）が発生して閾値電圧を変化させる。 In the element substrate 1A of the present embodiment, an organic semiconductor is used for the semiconductor layer 14A. In the TFT 10 using such an organic semiconductor, transistor characteristics may fluctuate when light (visible light) is incident from the outside. Specifically, the organic semiconductor has absorption with respect to visible light, and a carrier (photocarrier) excited by light irradiation is generated to change the threshold voltage.
　例えば、このような素子基板１Ａを表示装置のバックプレーンとして用いた場合、次のような光が入射することがある。即ち、第３電極１８上に、有機電界発光素子などの自発光素子を備える場合には、そのような自発光素子からの発光光がＴＦＴ１０に入射する。あるいは、第３電極１８上に液晶表示素子などの表示素子を備える場合には、バックライトからの照明光がＴＦＴ１０に入射する。また、第３電極１８上に電気泳動表示素子などを備える場合には、外光（太陽光や照明光など）がＴＦＴ１０に入射することがある。更には、素子基板１Ａが、撮像装置のセンサーアレイに用いられた場合には、受光光の一部がＴＦＴ１０に入射する。 For example, when such an element substrate 1A is used as a backplane of a display device, the following light may enter. That is, when a self-luminous element such as an organic electroluminescent element is provided on the third electrode 18, light emitted from such a self-luminous element enters the TFT 10. Alternatively, when a display element such as a liquid crystal display element is provided on the third electrode 18, illumination light from the backlight is incident on the TFT 10. When an electrophoretic display element or the like is provided on the third electrode 18, external light (sunlight, illumination light, etc.) may enter the TFT 10. Furthermore, when the element substrate 1A is used in a sensor array of an imaging apparatus, a part of the received light is incident on the TFT 10.
　図５に、本実施の形態の比較例に係るＴＦＴ（ＴＦＴ１００）の要部の断面構成について示す。比較例に係るＴＦＴ１００では、基板１０１上に、第１電極１０２、第１絶縁膜１０３、半導体層１０４および第２電極１０５ａ，１０５ｂがこの順に設けられている。このようなＴＦＴ１００では、例えば第２電極１０５ａ，１０５ｂの非形成領域を通じて、外部から光Ｌが入射し、半導体層１０４へ到達し、上述したような特性変動を引き起してしまう。 FIG. 5 shows a cross-sectional configuration of a main part of a TFT (TFT 100) according to a comparative example of the present embodiment. In the TFT 100 according to the comparative example, a first electrode 102, a first insulating film 103, a semiconductor layer 104, and second electrodes 105a and 105b are provided in this order on a substrate 101. In such a TFT 100, for example, light L is incident from the outside through the non-formation region of the second electrodes 105a and 105b, reaches the semiconductor layer 104, and causes the characteristic variation as described above.
　これに対し、本実施の形態の素子基板１Ａでは、ＴＦＴ１０の半導体層１４Ａと離隔して、有機半導体よりなる光吸収層１４Ｂが設けられている。これにより、外部から光ＬがＴＦＴ１０に入射した場合にも、この光Ｌは光吸収層１４Ｂによって吸収され、半導体層１４Ａへ到達することが抑制される（半導体層１４Ａへ到達する光量が低減する）。 On the other hand, in the element substrate 1A of the present embodiment, a light absorption layer 14B made of an organic semiconductor is provided apart from the semiconductor layer 14A of the TFT 10. Accordingly, even when light L is incident on the TFT 10 from the outside, the light L is absorbed by the light absorption layer 14B and is prevented from reaching the semiconductor layer 14A (the amount of light reaching the semiconductor layer 14A is reduced). ).
　一方で、半導体層１４Ａが基板１１の全面に存在すると、電極間のリークが生じ、正常な回路の駆動が困難となる。また、有機半導体膜は、他の層（電極層や絶縁層）と密着性が低く、特に微細な金属配線の直下に存在すると機械的な信頼性が低下してしまう。光吸収層１４Ｂが、半導体層１４Ａと離隔して、かつ第２電極１５ａ，１５ｂと非重畳の領域に形成されていることにより、そのような電極間のリークの発生や機械的な信頼性の低下を抑制することができる。 On the other hand, if the semiconductor layer 14A exists on the entire surface of the substrate 11, leakage between the electrodes occurs, and normal circuit driving becomes difficult. In addition, the organic semiconductor film has low adhesion to other layers (electrode layers and insulating layers), and particularly when it exists directly under a fine metal wiring, the mechanical reliability is lowered. Since the light absorption layer 14B is formed in a region that is separated from the semiconductor layer 14A and not overlapped with the second electrodes 15a and 15b, the occurrence of leakage between the electrodes and mechanical reliability can be prevented. The decrease can be suppressed.
　また、光吸収層１４Ｂが、第２電極１５ａ，１５ｂの非形成領域を覆うように形成されることで、上記のようなリークの発生や機械的な信頼性の低下を抑制しつつ、半導体層１４Ａへの到達光量をより効果的に低減することができる。 In addition, the light absorption layer 14B is formed so as to cover the non-formation regions of the second electrodes 15a and 15b, so that the semiconductor layer can be suppressed while suppressing the occurrence of leakage and the deterioration of mechanical reliability as described above. The amount of light reaching 14A can be more effectively reduced.
　加えて、光吸収層１４Ｂが、半導体層１４Ａと同一材料から構成されると共に、同一層に形成されることにより、製造プロセスにおいて、光吸収層１４Ｂと半導体層１４Ａとを同一の成膜工程およびパターニング工程を経て形成可能である（一括して形成可能である）。また、遮光のために新たな材料を用意する必要もない。つまり、工程数およびコストの増大を招くことなく、光吸収層１４Ｂを形成し、ＴＦＴ１０の特性変動を抑制することが可能である。 In addition, since the light absorption layer 14B is made of the same material as the semiconductor layer 14A and is formed in the same layer, the light absorption layer 14B and the semiconductor layer 14A can be formed in the same film formation process and in the manufacturing process. It can be formed through a patterning step (can be formed all at once). Moreover, it is not necessary to prepare a new material for light shielding. That is, the light absorption layer 14B can be formed without increasing the number of steps and the cost, and the characteristic variation of the TFT 10 can be suppressed.
　以上説明したように、本実施の形態では、ＴＦＴ１０において、半導体層１４Ａと離隔して、有機半導体から構成された光吸収層１４Ｂを配置したことにより、ＴＦＴ１０に光が入射した場合にも、この入射光の半導体層１４Ａへの到達を抑制することができる。有機半導体を含む半導体層１４Ａでは、光入射によって閾値変動などを生じ得るが、光吸収層１４Ｂが配置されることで、入射光による閾値変動を抑制することができる。よって、ＴＦＴ１０の特性変動を抑制して信頼性を向上させることが可能となる。 As described above, in the present embodiment, in the TFT 10, the light absorption layer 14 </ b> B made of an organic semiconductor is disposed apart from the semiconductor layer 14 </ b> A, so that even when light enters the TFT 10, The arrival of incident light to the semiconductor layer 14A can be suppressed. In the semiconductor layer 14A containing an organic semiconductor, threshold fluctuation and the like may occur due to light incidence, but the threshold fluctuation due to incident light can be suppressed by arranging the light absorption layer 14B. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT 10.
　次に、上記実施の形態の他の実施の形態および変形例について説明する。尚、以下では、上記実施の形態と同様の構成要素については同一の符号を付し、適宜その説明を省略する。 Next, other embodiments and modifications of the above embodiment will be described. In the following, the same components as those in the above embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
＜第２の実施の形態＞
［構成］
　図７は、本開示の第２の実施の形態に係る素子基板（素子基板１Ｂ）の概略構成を表す断面図である。素子基板１Ｂは、上記第１の実施の形態の素子基板１Ａと同様、例えば表示駆動用のバックプレーンまたは撮像装置のセンサーアレイ等に用いられる回路基板であり、例えば複数のＴＦＴおよび配線層等の回路要素が多層にわたって形成され、集積化されている。図７では、素子基板１Ｂの一部である１つのＴＦＴ１０とその近傍の領域のみを示している。 <Second Embodiment>
[Constitution]
FIG. 7 is a cross-sectional view illustrating a schematic configuration of an element substrate (element substrate 1B) according to the second embodiment of the present disclosure. Similar to the element substrate 1A of the first embodiment, the element substrate 1B is a circuit board used for, for example, a display driving backplane or a sensor array of an imaging device, and includes a plurality of TFTs, wiring layers, Circuit elements are formed and integrated over multiple layers. FIG. 7 shows only one TFT 10 which is a part of the element substrate 1B and a region in the vicinity thereof.
　ＴＦＴ１０は、上記第１の実施の形態でも述べたように、例えばいわゆるボトムゲート型およびトップコンタクト構造を有する有機ＴＦＴであり、基板１１上に、第１電極１２、第１絶縁膜（第１絶縁膜１３Ａ）を挟んで半導体層１４Ａを有している。半導体層１４Ａ上には、一対の第２電極１５ａ，１５ｂが半導体層１４Ａと電気的に接続されて配設されている。また、半導体層１４Ａ上には、保護膜１６が形成されている。但し、本実施の形態では、保護膜１６が、少なくとも、半導体層１４Ａのうちの第２電極１５ａ，１５ｂから露出した領域を覆っていればよい。このＴＦＴ１０の上には、第２絶縁膜１７が形成され、第２絶縁膜１７上には、第２電極１５ａに電気的に接続された第３電極１８が形成されている。 As described in the first embodiment, the TFT 10 is, for example, an organic TFT having a so-called bottom gate type and a top contact structure, and has a first electrode 12 and a first insulating film (first insulating film) on the substrate 11. The semiconductor layer 14A is sandwiched between the film 13A). On the semiconductor layer 14A, a pair of second electrodes 15a and 15b are disposed in electrical connection with the semiconductor layer 14A. A protective film 16 is formed on the semiconductor layer 14A. However, in the present embodiment, it is only necessary that the protective film 16 covers at least the regions exposed from the second electrodes 15a and 15b in the semiconductor layer 14A. A second insulating film 17 is formed on the TFT 10, and a third electrode 18 electrically connected to the second electrode 15 a is formed on the second insulating film 17.
　本実施の形態では、上記第１の実施の形態と異なり、第１絶縁膜１３Ａが局所的に厚みの小さな薄膜部分１３Ａ１を含んでいる。第１絶縁膜１３Ａは、第１電極１２と半導体層１４Ａとの間に設けられると共に、複数の画素に共通して形成されるか、または画素毎に分離されて形成されている。この第１絶縁膜１３Ａは、上記第１の実施の形態の第１絶縁膜１３の構成材料として列挙した有機絶縁膜または無機絶縁膜と同様の材料から構成されている。 In the present embodiment, unlike the first embodiment, the first insulating film 13A includes a thin film portion 13A1 having a locally small thickness. The first insulating film 13A is provided between the first electrode 12 and the semiconductor layer 14A, and is formed in common for a plurality of pixels or separated for each pixel. The first insulating film 13A is made of the same material as the organic insulating film or the inorganic insulating film listed as the constituent material of the first insulating film 13 of the first embodiment.
　薄膜部分１３Ａ１は、例えば画素内において、１つのＴＦＴ１０に対して少なくとも１箇所に設けられている。具体的には、薄膜部分１３Ａ１は、半導体層１４Ａと非重畳で、かつ半導体層１４Ａに隣接して（平面視的に隣接して）設けられている。望ましくは、本実施の形態のように、薄膜部分１３Ａ１は、半導体層１４Ａを挟んで両側に設けられている。平面視では、薄膜部分１３Ａ１は、半導体層１４Ａを囲んで（半導体層１４Ａの外周に沿って）設けられている。また、薄膜部分１３Ａ１とその他の部分（半導体層１４Ａに対向する部分）との境界付近には、図示したように階段状の段差が形成されていることが望ましい。但し、その境界付近では、なだらかに厚みが変化してもよいし、順テーパ形状あるいは逆テーパ形状を有していても構わない。 The thin film portion 13A1 is provided at least at one location with respect to one TFT 10 in the pixel, for example. Specifically, the thin film portion 13A1 is provided so as not to overlap with the semiconductor layer 14A and adjacent to the semiconductor layer 14A (adjacent in plan view). Desirably, as in the present embodiment, the thin film portion 13A1 is provided on both sides of the semiconductor layer 14A. In plan view, the thin film portion 13A1 is provided surrounding the semiconductor layer 14A (along the outer periphery of the semiconductor layer 14A). Further, it is desirable that a stepped step is formed in the vicinity of the boundary between the thin film portion 13A1 and the other portion (portion facing the semiconductor layer 14A) as shown in the figure. However, in the vicinity of the boundary, the thickness may change gently, or it may have a forward taper shape or a reverse taper shape.
　この薄膜部分１３Ａ１の厚みｔ２は、例えば５０ｎｍ以上９００ｎｍ以下である。また、薄膜部分１３Ａ１の幅ｄは、例えば２μｍ以上５０μｍ以下である。また、厚みｔ１と厚みｔ２との差（ｔ１－ｔ２）は、例えば２００ｎｍ以下であることが望ましい。第１絶縁膜１３上に形成する各層における平坦性を確保すると共に、電極パターンあるいは電気容量を均一に形成し易くなるためである。 The thickness t2 of the thin film portion 13A1 is, for example, not less than 50 nm and not more than 900 nm. The width d of the thin film portion 13A1 is, for example, 2 μm or more and 50 μm or less. Further, the difference (t1−t2) between the thickness t1 and the thickness t2 is preferably 200 nm or less, for example. This is because the flatness of each layer formed on the first insulating film 13 is ensured, and the electrode pattern or the capacitance is easily formed uniformly.
［製造方法］
　図８Ａ～図９Ｂは、素子基板１Ｂの製造方法を説明するための図である。素子基板１Ｂは、例えば次のようにして製造することができる。 [Production method]
8A to 9B are views for explaining a method of manufacturing the element substrate 1B. The element substrate 1B can be manufactured, for example, as follows.
　まず、図８Ａに示したように、上記第１の実施の形態と同様にして、基板１１上に第１電極１２および第１絶縁膜１３Ａを形成する。続いて、第１絶縁膜１３Ａ上に、上記第１の実施の形態と同様にして、半導体層１４を成膜した後、無機レジスト膜２１１ａ，２１１ｂをパターン形成する。このとき、無機レジスト膜２１１ａは、半導体層１４Ａの形成領域に形成され、無機レジスト膜２１１ｂは、半導体層１４Ａから間隔（幅ｄ相当の間隔）をおいて、形成される。 First, as shown in FIG. 8A, the first electrode 12 and the first insulating film 13A are formed on the substrate 11 in the same manner as in the first embodiment. Subsequently, after the semiconductor layer 14 is formed on the first insulating film 13A in the same manner as in the first embodiment, inorganic resist films 211a and 211b are patterned. At this time, the inorganic resist film 211a is formed in the formation region of the semiconductor layer 14A, and the inorganic resist film 211b is formed at an interval (interval corresponding to the width d) from the semiconductor layer 14A.
　この後、図８Ｂに示したように、例えばフォトリソグラフィ法を用いたエッチングにより、半導体層１４をパターニングすることにより、半導体層１４Ａを形成する。尚、無機レジスト膜２１１ａの形成箇所に対応して、半導体層１４Ａが形成されると同時に、無機レジスト膜２１１ｂの形成箇所にも、半導体層１４が残存する。この際のエッチング条件を調整することにより、半導体層１４Ａの下に形成された第１絶縁膜１３Ａの表面側の一部をもエッチングする。これにより、第１絶縁膜１３Ａのうちの例えば半導体層１４Ａに隣接する領域に、薄膜部分１３Ａ１を形成することができる。 Thereafter, as shown in FIG. 8B, the semiconductor layer 14A is formed by patterning the semiconductor layer 14 by etching using, for example, a photolithography method. Incidentally, the semiconductor layer 14A remains at the formation position of the inorganic resist film 211b simultaneously with the formation of the semiconductor layer 14A corresponding to the formation position of the inorganic resist film 211a. By adjusting the etching conditions at this time, a part of the surface side of the first insulating film 13A formed under the semiconductor layer 14A is also etched. Thereby, the thin film portion 13A1 can be formed in a region of the first insulating film 13A adjacent to, for example, the semiconductor layer 14A.
　半導体層１４Ａおよび薄膜部分１３Ａ１を形成した後、無機レジスト膜２１１ａ，２１１ｂを除去する。但し、無機レジスト膜２１１ａ，２１１ｂは、除去せずに残してもよい。無機レジスト膜２１１ｂを残すことで、無機レジスト膜２１１ｂを遮光膜として機能させることができる。半導体層１４Ａのパターニングと同時に、無機レジスト膜２１１ｂによる遮光層を形成することが可能である。 After forming the semiconductor layer 14A and the thin film portion 13A1, the inorganic resist films 211a and 211b are removed. However, the inorganic resist films 211a and 211b may be left without being removed. By leaving the inorganic resist film 211b, the inorganic resist film 211b can function as a light-shielding film. Simultaneously with the patterning of the semiconductor layer 14A, it is possible to form a light shielding layer of the inorganic resist film 211b.
　続いて、図８Ｃに示したように、第２電極１５ａ，１５ｂを形成する。具体的には、まず、基板１１上の全面にわたって、上述した導電膜材料（例えば、第１電極１２と同一材料）を、例えばスパッタ法により成膜した後、例えばフォトリソグラフィ法を用いたウェットエッチングにより、所定の形状にパターニングする。 Subsequently, as shown in FIG. 8C, the second electrodes 15a and 15b are formed. Specifically, first, the above-described conductive film material (for example, the same material as the first electrode 12) is formed over the entire surface of the substrate 11, for example, by sputtering, and then wet etching using, for example, photolithography. Thus, patterning is performed in a predetermined shape.
　続いて、図８Ｄに示したように、上述した材料等からなる保護膜１６をパターン形成する。このようにして、ＴＦＴ１０を形成することができる。 Subsequently, as shown in FIG. 8D, the protective film 16 made of the above-described material or the like is patterned. In this way, the TFT 10 can be formed.
　次いで、図９Ａに示したように、上記第１の実施の形態と同様にして、ＴＦＴ１０上に第２絶縁膜１７を形成する。また、第２絶縁膜１７のうちの第２電極１５ａに対向する部分には、貫通孔１７ａを形成する。 Next, as shown in FIG. 9A, a second insulating film 17 is formed on the TFT 10 in the same manner as in the first embodiment. A through hole 17a is formed in a portion of the second insulating film 17 facing the second electrode 15a.
　最後に、図９Ｂに示したように、第３電極１８を、貫通孔１７ａを埋め込みようにパターン形成する。これにより、図７に示した素子基板１Ｂを完成する。 Finally, as shown in FIG. 9B, the third electrode 18 is patterned so as to fill the through hole 17a. Thereby, the element substrate 1B shown in FIG. 7 is completed.
［効果］
　本実施の形態の素子基板１Ｂでは、例えばＴＦＴ１０において、第１電極１２に所定の電位が供給されると、半導体層１４Ａに電界が生じ（チャネルが形成され）、第２電極１５ａ，１５ｂ間が導通する。例えば、素子基板１Ａが表示駆動用のバックプレーンを成す場合には、例えば第２電極１５ｂに印加された信号電圧等が、第３電極１８に供給され、表示駆動がなされる。 [effect]
In the element substrate 1B of the present embodiment, for example, in the TFT 10, when a predetermined potential is supplied to the first electrode 12, an electric field is generated in the semiconductor layer 14A (a channel is formed), and the second electrodes 15a and 15b are connected to each other. Conduct. For example, when the element substrate 1A forms a backplane for display driving, for example, a signal voltage applied to the second electrode 15b is supplied to the third electrode 18 to perform display driving.
　本実施の形態の素子基板１Ｂにおいても、上記第１の実施の形態と同様、半導体層１４Ａに有機半導体が用いられている。このような有機半導体を用いたＴＦＴ１０では、外部から光（可視光）が入射すると、閾値電圧などのトランジスタ特性が変動することがある。 Also in the element substrate 1B of the present embodiment, an organic semiconductor is used for the semiconductor layer 14A, as in the first embodiment. In the TFT 10 using such an organic semiconductor, transistor characteristics such as a threshold voltage may fluctuate when light (visible light) is incident from the outside.
　ここで、本実施の形態の素子基板１Ｂでは、第１絶縁膜１３Ａに、局所的に厚みの小さな薄膜部分１３Ａ１が設けられている。これにより、外部から光がＴＦＴ１０に入射した場合にも、この光が第１絶縁膜１３Ａを導波路として半導体層１４Ａへ到達することが抑制される（半導体層１４Ａへ到達する光量が低減する）。 Here, in the element substrate 1B of the present embodiment, the thin film portion 13A1 having a locally small thickness is provided on the first insulating film 13A. Accordingly, even when light is incident on the TFT 10 from the outside, the light is suppressed from reaching the semiconductor layer 14A using the first insulating film 13A as a waveguide (the amount of light reaching the semiconductor layer 14A is reduced). .
　また、薄膜部分１３Ａ１が、半導体層１４Ａと非重畳で、かつ隣接して設けられることにより、製造プロセスにおいて、半導体層１４Ａのパターニング工程においてエッチング条件を調整することによって、薄膜部分１３Ａ１を形成可能である。また、遮光のために新たな材料を用意する必要もない。つまり、工程数およびコストの増大を招くことなく、薄膜部分１３Ａ１を形成し、ＴＦＴ１０の特性変動を抑制することが可能である。 Further, since the thin film portion 13A1 is provided so as not to overlap with and adjacent to the semiconductor layer 14A, the thin film portion 13A1 can be formed by adjusting the etching conditions in the patterning process of the semiconductor layer 14A in the manufacturing process. is there. Moreover, it is not necessary to prepare a new material for light shielding. That is, the thin film portion 13A1 can be formed without increasing the number of steps and the cost, and the characteristic variation of the TFT 10 can be suppressed.
　加えて、薄膜部分１３Ａ１が、半導体層１４Ａを挟んで両側に（平面視では、半導体層１４の外周に沿って）設けられることで、半導体層１４Ａへの到達光量をより効果的に低減することができる。 In addition, the amount of light reaching the semiconductor layer 14A can be more effectively reduced by providing the thin film portions 13A1 on both sides of the semiconductor layer 14A (along the outer periphery of the semiconductor layer 14 in plan view). Can do.
　以上説明したように、本実施の形態では、ＴＦＴ１０において、第１絶縁膜１３Ａが、局所的に厚みの小さな薄膜部分１３Ａ１を有することで、ＴＦＴ１０に光が入射した場合にも、この入射光の半導体層１４Ａへの到達を抑制することができる。有機半導体を含む半導体層１４Ａでは、光入射によって閾値変動などを生じ得るが、光吸収層１４Ｂが配置されることで、入射光による閾値変動を抑制することができる。よって、ＴＦＴ１０の特性変動を抑制して信頼性を向上させることが可能となる。 As described above, in the present embodiment, in the TFT 10, the first insulating film 13 </ b> A has the thin film portion 13 </ b> A <b> 1 having a locally small thickness, so that even when light enters the TFT 10, Reaching the semiconductor layer 14A can be suppressed. In the semiconductor layer 14A containing an organic semiconductor, threshold fluctuation and the like may occur due to light incidence, but the threshold fluctuation due to incident light can be suppressed by arranging the light absorption layer 14B. Therefore, it becomes possible to improve the reliability by suppressing the characteristic variation of the TFT 10.
＜変形例１＞
　図１０は、変形例１に係る素子基板（素子基板１Ｃ）の要部構成を表したものである。本変形例の素子基板１Ｃでは、上記第１の実施の形態において説明した光吸収層１４Ｂと、上記第２の実施の形態において説明した薄膜部分１３Ａ１との両方が設けられている。 <Modification 1>
FIG. 10 illustrates a main configuration of an element substrate (element substrate 1 </ b> C) according to the first modification. In the element substrate 1C of this modification, both the light absorption layer 14B described in the first embodiment and the thin film portion 13A1 described in the second embodiment are provided.
　本変形例のように、半導体層１４Ａと離隔して、有機半導体から構成された光吸収層１４Ｂが設けられると共に、第１絶縁膜１３Ａが局所的に厚みの小さな薄膜部分１３Ａ１を有していてもよい。即ち、半導体層１４Ａと光吸収層１４Ｂとの間に、薄膜部分１３Ａ１が配置されている。このような場合であっても、上記第１および第２の実施の形態と同等またはそれ以上の効果を得ることができる。 As in this modification, a light absorption layer 14B made of an organic semiconductor is provided apart from the semiconductor layer 14A, and the first insulating film 13A has a thin film portion 13A1 with a small thickness locally. Also good. That is, the thin film portion 13A1 is disposed between the semiconductor layer 14A and the light absorption layer 14B. Even in such a case, effects equivalent to or higher than those of the first and second embodiments can be obtained.
＜変形例２－１～２－６＞
　図１１Ａおよび１１Ｂは、変形例２－１，２－２に係る素子基板の要部構成を表したものである。上記第１の実施の形態では、保護膜１６を半導体層１４Ａおよび光吸収層１４Ｂに対向する選択的な領域に形成したが、この保護膜１６の形成箇所は特に限定されない。例えば、図１１Ａに示したように、保護膜１６は、素子基板の全体を覆うように形成されていてもよい。また、図１１Ｂに示したように、保護膜１６が形成されていない構成であっても構わない。保護膜１６は、必要に応じて設けられていればよい。 <Modifications 2-1 to 2-6>
FIGS. 11A and 11B show the main configuration of the element substrate according to Modifications 2-1 and 2-2. In the first embodiment, the protective film 16 is formed in a selective region facing the semiconductor layer 14A and the light absorption layer 14B. However, the formation position of the protective film 16 is not particularly limited. For example, as shown in FIG. 11A, the protective film 16 may be formed so as to cover the entire element substrate. Further, as shown in FIG. 11B, a configuration in which the protective film 16 is not formed may be used. The protective film 16 should just be provided as needed.
　図１２Ａおよび１２Ｂは、変形例２－３，２－４に係る素子基板の要部構成を表したものである。上記第２の実施の形態では、保護膜１６を半導体層１４Ａに対向する選択的な領域に形成したが、この保護膜１６の形成箇所は特に限定されない。例えば、図１２Ａに示したように、保護膜１６は、素子基板の全体を覆うように形成されていてもよい。また、図１２Ｂに示したように、保護膜１６が形成されていない構成であっても構わない。保護膜１６は、必要に応じて設けられていればよい。 FIGS. 12A and 12B show the main configuration of the element substrate according to Modifications 2-3 and 2-4. In the second embodiment, the protective film 16 is formed in a selective region facing the semiconductor layer 14A. However, the place where the protective film 16 is formed is not particularly limited. For example, as illustrated in FIG. 12A, the protective film 16 may be formed so as to cover the entire element substrate. Moreover, as shown to FIG. 12B, the structure in which the protective film 16 is not formed may be sufficient. The protective film 16 should just be provided as needed.
　図１３Ａおよび１３Ｂは、変形例２－５，２－６に係る素子基板の要部構成を表したものである。このように、上記変形例１において説明した素子基板の構成においても、保護膜１６の形成箇所は特に限定されない。例えば、図１３Ａに示したように、保護膜１６は、素子基板の全体を覆うように形成されていてもよい。また、図１３Ｂに示したように、保護膜１６が形成されていない構成であっても構わない。保護膜１６は、必要に応じて設けられていればよい。 FIGS. 13A and 13B show the main configuration of the element substrate according to Modifications 2-5 and 2-6. Thus, even in the configuration of the element substrate described in Modification 1, the location where the protective film 16 is formed is not particularly limited. For example, as illustrated in FIG. 13A, the protective film 16 may be formed so as to cover the entire element substrate. Moreover, as shown to FIG. 13B, the structure in which the protective film 16 is not formed may be sufficient. The protective film 16 should just be provided as needed.
＜変形例３－１～３－３＞
　図１４Ａ～１４Ｃは、変形例３－１～３－３に係る素子基板の要部構成を表したものである。上記実施の形態等では、ＴＦＴ１０の素子構造として、ボトムゲート型およびトップコンタクト構造のものを例示したが、本開示の薄膜トランジスタは、その他の素子構造のものにも適用可能である。例えば、ボトムゲート型およびボトムコンタクト構造をもつＴＦＴ１０Ａ（図１４Ａ）、トップゲート型およびトップコンタクト構造をもつＴＦＴ１０Ｂ（図１４Ｂ）、あるいはトップゲート型およびボトムコンタクト構造を持つＴＦＴ１０Ｃ（図１４Ｃ）にも適用可能である。 <Modifications 3-1 to 3-3>
14A to 14C show the main configuration of the element substrate according to the modified examples 3-1 to 3-3. In the above-described embodiment and the like, the element structure of the TFT 10 is exemplified by the bottom gate type and the top contact structure, but the thin film transistor of the present disclosure can also be applied to other element structures. For example, TFT 10A (FIG. 14A) having a bottom gate type and bottom contact structure, TFT 10B (FIG. 14B) having a top gate type and top contact structure, or TFT 10C (FIG. 14C) having a top gate type and bottom contact structure are also applied. Is possible.
＜適用例＞
　上記実施の形態等で説明した素子基板１Ａ（素子基板１Ｂ，１Ｃ等も同様）は、表示装置１に使用されるバックプレーンとして好適に用いられる。尚、表示装置１としては、例えば有機ＥＬ表示装置、ＬＥＤディスプレイ、液晶表示装置、電子ペーパーディスプレイ等が挙げられる。図１５に、表示装置１の機能ブロック構成例について模式的に示す。 <Application example>
The element substrate 1 </ b> A described in the above embodiments and the like (the same applies to the element substrates 1 </ b> B and 1 </ b> C) is preferably used as a backplane used in the display device 1. Examples of the display device 1 include an organic EL display device, an LED display, a liquid crystal display device, and an electronic paper display. FIG. 15 schematically shows a functional block configuration example of the display device 1.
　この表示装置１は、基板１１上の表示領域Ｓに、複数の画素ＰＸＬを含む画素駆動回路１４０を有すると共に、表示領域Ｓの周辺には、映像表示用のドライバである信号線駆動回路１２０および走査線駆動回路１３０を有している。 The display device 1 includes a pixel driving circuit 140 including a plurality of pixels PXL in a display area S on a substrate 11, and a signal line driving circuit 120 that is a video display driver and a display area S around the display area S. A scanning line driving circuit 130 is included.
　画素駆動回路１４０は、例えばアクティブマトリクス方式により駆動される駆動回路である。この画素駆動回路１４０では、列方向に沿って信号線１２０Ａ、行方向に沿って走査線１３０Ａがそれぞれ複数配置されている。各信号線１２０Ａと各走査線１３０Ａとの交差部が、各画素ＰＸＬに対応している。各信号線１２０Ａは、信号線駆動回路１２０に接続され、この信号線駆動回路１２０から信号線１２０Ａを介して各画素ＰＸＬに画像信号が供給されるようになっている。各走査線１３０Ａは走査線駆動回路１３０に接続され、この走査線駆動回路１３０から走査線１３０Ａを介して各画素ＰＸＬに走査信号が順次供給されるようになっている。この画素ＰＸＬ内に、例えば、有機電界発光素子およびＬＥＤ（Light Emitting Diode：発光ダイオード）等の発光素子、または電気泳動表示素子および液晶表示素子等の表示素子と、上記実施の形態等のＴＦＴ１０とが配置されている。表示装置１では、素子基板１Ａ，１Ｂ，１Ｃ等を備えることにより、ＴＦＴの特性変動を抑制して、信頼性を向上させることが可能である。 The pixel driving circuit 140 is a driving circuit driven by, for example, an active matrix method. In the pixel driving circuit 140, a plurality of signal lines 120A are arranged along the column direction, and a plurality of scanning lines 130A are arranged along the row direction. An intersection between each signal line 120A and each scanning line 130A corresponds to each pixel PXL. Each signal line 120A is connected to the signal line drive circuit 120, and an image signal is supplied from the signal line drive circuit 120 to each pixel PXL via the signal line 120A. Each scanning line 130A is connected to a scanning line driving circuit 130, and a scanning signal is sequentially supplied from the scanning line driving circuit 130 to each pixel PXL via the scanning line 130A. In this pixel PXL, for example, a light emitting element such as an organic electroluminescent element and LED (Light Emitting Diode), or a display element such as an electrophoretic display element and a liquid crystal display element, and the TFT 10 according to the above-described embodiment, etc. Is arranged. In the display device 1, by providing the element substrates 1 </ b> A, 1 </ b> B, 1 </ b> C and the like, it is possible to suppress the characteristic variation of the TFT and improve the reliability.
　あるいは、上記実施の形態等で説明した素子基板１Ａ（素子基板１Ｂ，１Ｃ等も同様）は、撮像装置２に使用されるセンサーアレイに好適に用いられる。尚、撮像装置２としては、例えばＣＭＯＳイメージセンサ等の固体撮像装置が挙げられる。図１６に、撮像装置２の機能ブロック構成例について模式的に示す。 Alternatively, the element substrate 1A described in the above embodiments and the like (the same applies to the element substrates 1B and 1C) is preferably used for a sensor array used in the imaging device 2. Examples of the imaging device 2 include a solid-state imaging device such as a CMOS image sensor. FIG. 16 schematically shows a functional block configuration example of the imaging apparatus 2.
　この撮像装置２は、例えば、撮像エリアとして複数の画素Ｐを含む画素部２ａと、行走査部２３１、水平選択部２３３、列走査部２３４およびシステム制御部２３２を含む回路部２３０とを有している。 The imaging device 2 includes, for example, a pixel unit 2a including a plurality of pixels P as an imaging area, and a circuit unit 230 including a row scanning unit 231, a horizontal selection unit 233, a column scanning unit 234, and a system control unit 232. ing.
　回路部２３０は、画素部２ａと同一の基板上に形成されていてもよいし、あるいは基板上に回路部２３０と画素部２ａとが積層されていてもよい。行走査部２３１は、シフトレジスタやアドレスデコーダ等によって構成され、画素部２ａの各画素Ｐを、例えば行単位で駆動する画素駆動部である。行走査部２３１によって選択走査された画素行の各画素Ｐから出力された信号は、垂直信号線Ｌsigの各々を通して水平選択部２３３に供給される。水平選択部２３３は、垂直信号線Ｌsigごとに設けられたアンプや水平選択スイッチ等によって構成されている。列走査部２３４は、シフトレジスタやアドレスデコーダ等によって構成され、水平選択部２３３の各水平選択スイッチを走査しつつ順番に駆動するものである。この列走査部２３４による選択走査により、垂直信号線Ｌsigの各々を通じて各画素の出力信号が順番に水平信号線２３５に出力され、水平信号線２３５を介して外部へ出力される。 The circuit unit 230 may be formed on the same substrate as the pixel unit 2a, or the circuit unit 230 and the pixel unit 2a may be stacked on the substrate. The row scanning unit 231 includes a shift register, an address decoder, and the like, and is a pixel driving unit that drives each pixel P of the pixel unit 2a, for example, in units of rows. A signal output from each pixel P in the pixel row that is selectively scanned by the row scanning unit 231 is supplied to the horizontal selection unit 233 through each of the vertical signal lines Lsig. The horizontal selection unit 233 is configured by an amplifier, a horizontal selection switch, and the like provided for each vertical signal line Lsig. The column scanning unit 234 is configured by a shift register, an address decoder, and the like, and drives the horizontal selection switches in the horizontal selection unit 233 in order while scanning. By the selective scanning by the column scanning unit 234, the output signal of each pixel is sequentially output to the horizontal signal line 235 through each of the vertical signal lines Lsig, and is output to the outside via the horizontal signal line 235.
　システム制御部２３２は、外部から与えられるクロックや、動作モードを指令するデータなどを受け取り、また、撮像装置２の内部情報などのデータを出力するものである。システム制御部２３２はさらに、各種のタイミング信号を生成するタイミングジェネレータを有し、このタイミングジェネレータで生成された各種のタイミング信号を基に行走査部２３１、水平選択部２３３および列走査部２３４などの駆動制御を行う。 The system control unit 232 receives an externally supplied clock, data for instructing an operation mode, and the like, and outputs data such as internal information of the imaging device 2. The system control unit 232 further includes a timing generator that generates various timing signals. The row scanning unit 231, the horizontal selection unit 233, the column scanning unit 234, and the like are based on the various timing signals generated by the timing generator. Drive control is performed.
　画素部２ａは、例えば行列状に２次元配置された複数の画素Ｐを有している。この画素Ｐには、例えば画素行ごとに画素駆動線Ｌread（行選択線およびリセット制御線など）が配置され、画素列ごとに垂直信号線Ｌsigが配置されている。画素駆動線Ｌreadは、画素からの信号読み出しのための駆動信号を供給するものである。画素駆動線Ｌreadの一端は、行走査部２３１の各行に対応した出力端に接続されている。画素部２ａに形成された各画素Ｐ内に、上記実施の形態等のＴＦＴ１０が配置されている。撮像装置２では、素子基板１Ａ，１Ｂ，１Ｃ等を備えることにより、ＴＦＴの特性変動を抑制して、信頼性を向上させることが可能である。 The pixel unit 2a has, for example, a plurality of pixels P that are two-dimensionally arranged in a matrix. In this pixel P, for example, a pixel drive line Lread (row selection line, reset control line, etc.) is arranged for each pixel row, and a vertical signal line Lsig is arranged for each pixel column. The pixel drive line Lread supplies a drive signal for reading a signal from the pixel. One end of the pixel drive line Lread is connected to an output end corresponding to each row of the row scanning unit 231. In each pixel P formed in the pixel portion 2a, the TFT 10 of the above-described embodiment or the like is disposed. In the imaging device 2, by providing the element substrates 1A, 1B, 1C and the like, it is possible to suppress the characteristic variation of the TFT and improve the reliability.
　以上、実施の形態、変形例および適用例を挙げて説明したが、本開示内容はこれらの実施の形態等に限定されず、種々の変形が可能である。例えば、上記実施の形態等において説明した各層以外にも図示しない他の層や膜を備えていてもよい。 The embodiments, modifications, and application examples have been described above, but the present disclosure is not limited to these embodiments and the like, and various modifications can be made. For example, in addition to the layers described in the above embodiments, other layers and films not shown may be provided.
　また、上記実施の形態等において説明した効果は一例であり、他の効果であってもよい
し、更に他の効果を含んでいてもよい。 Moreover, the effect demonstrated in the said embodiment etc. is an example, The other effect may be sufficient and the other effect may be included.
　尚、本開示は、以下のような構成であってもよい。
（１）
　複数の画素と、前記画素毎に設けられた薄膜トランジスタとを備え、
　前記薄膜トランジスタは、
　第１電極と、
　前記第１電極に絶縁膜を介して対向配置されると共に有機半導体を含む半導体層と、
　前記半導体層に電気的に接続された第２電極と、
　前記半導体層と離隔して配置されると共に、有機半導体から構成された光吸収層と
　を有する
　表示装置。
（２）
　前記光吸収層は、前記半導体層と同一材料から構成されている
　上記（１）に記載の表示装置。
（３）
　前記光吸収層は、前記半導体層と同一層に形成されている
　上記（１）または（２）に記載の表示装置。
（４）
　前記光吸収層は、前記第２電極と非重畳の領域に形成されている
　上記（１）～（３）のいずれか１つに記載の表示装置。
（５）
　前記光吸収層は、前記画素内において、平面視的に前記第２電極の非形成領域を覆って形成されている
　上記（４）に記載の表示装置。
（６）
　前記絶縁膜は、局所的に厚みの小さな薄膜部分を有する
　上記（１）～（５）のいずれか１つに記載の表示装置。
（７）
　前記薄膜部分は、前記半導体層と前記光吸収層との間に設けられている
　上記（６）に記載の表示装置。
（８）
　複数の画素と、前記画素毎に設けられた薄膜トランジスタとを備え、
　前記薄膜トランジスタは、
　第１電極と、
　前記第１電極と対向配置されると共に有機半導体を含む半導体層と、
　前記第１電極と前記半導体層との間に形成された絶縁膜と、
　前記半導体層に電気的に接続された第２電極と
　を有し、
　前記絶縁膜は、局所的に厚みの小さな薄膜部分を含む
　表示装置。
（９）
　前記薄膜部分は、前記半導体層と非重畳で、かつ前記半導体層に平面視的に隣接して設けられている
　上記（８）に記載の表示装置。
（１０）
　前記薄膜部分は、前記半導体層の外周に沿って形成されている
　上記（９）に記載の表示装置。
（１１）
　複数の画素と、前記画素毎に設けられた薄膜トランジスタとを備え、
　前記薄膜トランジスタは、
　第１電極と、
　前記第１電極に絶縁膜を介して対向配置されると共に有機半導体を含む半導体層と、
　前記半導体層に電気的に接続された第２電極と、
　前記半導体層と離隔して配置されると共に、有機半導体から構成された光吸収層と
　を有する
　撮像装置。
（１２）
　複数の画素と、前記画素毎に設けられた薄膜トランジスタとを備え、
　前記薄膜トランジスタは、
　第１電極と、
　前記第１電極と対向配置されると共に有機半導体を含む半導体層と、
　前記第１電極と前記半導体層との間に形成された絶縁膜と、
　前記半導体層に電気的に接続された第２電極と
　を有し、
　前記絶縁膜は、局所的に厚みの小さな薄膜部分を含む
　撮像装置。 The present disclosure may be configured as follows.
(1)
A plurality of pixels, and a thin film transistor provided for each pixel,
The thin film transistor
A first electrode;
A semiconductor layer disposed opposite to the first electrode via an insulating film and including an organic semiconductor;
A second electrode electrically connected to the semiconductor layer;
A display device that is disposed separately from the semiconductor layer and has a light absorption layer made of an organic semiconductor.
(2)
The said light absorption layer is comprised from the same material as the said semiconductor layer. The display apparatus as described in said (1).
(3)
The display device according to (1) or (2), wherein the light absorption layer is formed in the same layer as the semiconductor layer.
(4)
The display device according to any one of (1) to (3), wherein the light absorption layer is formed in a region not overlapping with the second electrode.
(5)
The display device according to (4), wherein the light absorption layer is formed in the pixel so as to cover a region where the second electrode is not formed in plan view.
(6)
The display device according to any one of (1) to (5), wherein the insulating film has a thin film portion having a locally small thickness.
(7)
The display device according to (6), wherein the thin film portion is provided between the semiconductor layer and the light absorption layer.
(8)
A plurality of pixels, and a thin film transistor provided for each pixel,
The thin film transistor
A first electrode;
A semiconductor layer disposed opposite to the first electrode and including an organic semiconductor;
An insulating film formed between the first electrode and the semiconductor layer;
A second electrode electrically connected to the semiconductor layer,
The insulating film includes a thin film portion having a locally small thickness.
(9)
The display device according to (8), wherein the thin film portion is provided so as not to overlap the semiconductor layer and adjacent to the semiconductor layer in plan view.
(10)
The display device according to (9), wherein the thin film portion is formed along an outer periphery of the semiconductor layer.
(11)
A plurality of pixels, and a thin film transistor provided for each pixel,
The thin film transistor
A first electrode;
A semiconductor layer disposed opposite to the first electrode via an insulating film and including an organic semiconductor;
A second electrode electrically connected to the semiconductor layer;
An imaging device that is disposed separately from the semiconductor layer and has a light absorption layer made of an organic semiconductor.
(12)
A plurality of pixels, and a thin film transistor provided for each pixel,
The thin film transistor
A first electrode;
A semiconductor layer disposed opposite to the first electrode and including an organic semiconductor;
An insulating film formed between the first electrode and the semiconductor layer;
A second electrode electrically connected to the semiconductor layer,
The insulating film includes a thin film portion having a locally small thickness.
　本出願は、日本国特許庁において２０１５年７月２４日に出願された日本特許出願番号第２０１５－１４７０４４号を基礎として優先権を主張するものであり、この出願のすべての内容を参照によって本出願に援用する。 This application claims priority on the basis of Japanese Patent Application No. 2015-147044 filed on July 24, 2015 at the Japan Patent Office. The entire contents of this application are incorporated herein by reference. This is incorporated into the application.
　当業者であれば、設計上の要件や他の要因に応じて、種々の修正、コンビネーション、サブコンビネーション、および変更を想到し得るが、それらは添付の請求の範囲やその均等物の範囲に含まれるものであることが理解される。 Those skilled in the art will envision various modifications, combinations, subcombinations, and changes, depending on design requirements and other factors, which are within the scope of the appended claims and their equivalents. It is understood that

Claims (12)

  1. 　複数の画素と、前記画素毎に設けられた薄膜トランジスタとを備え、
    　前記薄膜トランジスタは、
    　第１電極と、
    　前記第１電極に絶縁膜を介して対向配置されると共に有機半導体を含む半導体層と、
    　前記半導体層に電気的に接続された第２電極と、
    　前記半導体層と離隔して配置されると共に、有機半導体から構成された光吸収層と
    　を有する
    　表示装置。     A plurality of pixels, and a thin film transistor provided for each pixel,
    The thin film transistor
    A first electrode;
    A semiconductor layer disposed opposite to the first electrode via an insulating film and including an organic semiconductor;
    A second electrode electrically connected to the semiconductor layer;
    A display device that is disposed separately from the semiconductor layer and has a light absorption layer made of an organic semiconductor.
  2. 　前記光吸収層は、前記半導体層と同一材料から構成されている
    　請求項１に記載の表示装置。     The display device according to claim 1, wherein the light absorption layer is made of the same material as the semiconductor layer.
  3. 　前記光吸収層は、前記半導体層と同一層に形成されている
    　請求項１に記載の表示装置。     The display device according to claim 1, wherein the light absorption layer is formed in the same layer as the semiconductor layer.
  4. 　前記光吸収層は、前記第２電極と非重畳の領域に形成されている
    　請求項１に記載の表示装置。     The display device according to claim 1, wherein the light absorption layer is formed in a region not overlapping with the second electrode.
  5. 　前記光吸収層は、前記画素内において、平面視的に前記第２電極の非形成領域を覆って形成されている
    　請求項４に記載の表示装置。     The display device according to claim 4, wherein the light absorption layer is formed so as to cover a non-formation region of the second electrode in plan view in the pixel.
  6. 　前記絶縁膜は、局所的に厚みの小さな薄膜部分を有する
    　請求項１に記載の表示装置。     The display device according to claim 1, wherein the insulating film has a thin film portion having a locally small thickness.
  7. 　前記薄膜部分は、前記半導体層と前記光吸収層との間に設けられている
    　請求項６に記載の表示装置。     The display device according to claim 6, wherein the thin film portion is provided between the semiconductor layer and the light absorption layer.
  8. 　複数の画素と、前記画素毎に設けられた薄膜トランジスタとを備え、
    　前記薄膜トランジスタは、
    　第１電極と、
    　前記第１電極と対向配置されると共に有機半導体を含む半導体層と、
    　前記第１電極と前記半導体層との間に形成された絶縁膜と、
    　前記半導体層に電気的に接続された第２電極と
    　を有し、
    　前記絶縁膜は、局所的に厚みの小さな薄膜部分を含む
    　表示装置。     A plurality of pixels, and a thin film transistor provided for each pixel,
    The thin film transistor
    A first electrode;
    A semiconductor layer disposed opposite to the first electrode and including an organic semiconductor;
    An insulating film formed between the first electrode and the semiconductor layer;
    A second electrode electrically connected to the semiconductor layer,
    The insulating film includes a thin film portion having a locally small thickness.
  9. 　前記薄膜部分は、前記半導体層と非重畳で、かつ前記半導体層に平面視的に隣接して設けられている
    　請求項８に記載の表示装置。     The display device according to claim 8, wherein the thin film portion is provided so as not to overlap the semiconductor layer and adjacent to the semiconductor layer in plan view.
  10. 　前記薄膜部分は、前記半導体層の外周に沿って形成されている
    　請求項９に記載の表示装置。     The display device according to claim 9, wherein the thin film portion is formed along an outer periphery of the semiconductor layer.
  11. 　複数の画素と、前記画素毎に設けられた薄膜トランジスタとを備え、
    　前記薄膜トランジスタは、
    　第１電極と、
    　前記第１電極に絶縁膜を介して対向配置されると共に有機半導体を含む半導体層と、
    　前記半導体層に電気的に接続された第２電極と、
    　前記半導体層と離隔して配置されると共に、有機半導体から構成された光吸収層と
    　を有する
    　撮像装置。     A plurality of pixels, and a thin film transistor provided for each pixel,
    The thin film transistor
    A first electrode;
    A semiconductor layer disposed opposite to the first electrode via an insulating film and including an organic semiconductor;
    A second electrode electrically connected to the semiconductor layer;
    An imaging device that is disposed separately from the semiconductor layer and has a light absorption layer made of an organic semiconductor.
  12. 　複数の画素と、前記画素毎に設けられた薄膜トランジスタとを備え、
    　前記薄膜トランジスタは、
    　第１電極と、
    　前記第１電極と対向配置されると共に有機半導体を含む半導体層と、
    　前記第１電極と前記半導体層との間に形成された絶縁膜と、
    　前記半導体層に電気的に接続された第２電極と
    　を有し、
    　前記絶縁膜は、局所的に厚みの小さな薄膜部分を含む
    　撮像装置。     A plurality of pixels, and a thin film transistor provided for each pixel,
    The thin film transistor
    A first electrode;
    A semiconductor layer disposed opposite to the first electrode and including an organic semiconductor;
    An insulating film formed between the first electrode and the semiconductor layer;
    A second electrode electrically connected to the semiconductor layer,
    The insulating film includes a thin film portion having a locally small thickness.
PCT/JP2016/070574 2015-07-24 2016-07-12 Display device and image pickup device WO2017018203A1 (en)

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