JP3396880B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a driving method thereof, and more particularly to a threshold voltage modulation type MOS image sensor used in a video camera, an electronic camera, an image input camera, a scanner or a facsimile. The present invention relates to a solid-state image pickup device using the same and a driving method thereof.

[0002]

2. Description of the Related Art Semiconductor image sensors such as CCD image sensors and MOS image sensors are excellent in mass productivity, and are applied to almost all image input device devices with the progress of pattern miniaturization technology. In particular,
In recent years, the power consumption is lower than that of a CCD image sensor, and the sensor element and the peripheral circuit element have the same CMOS.
Taking advantage of the fact that it can be created by technology, MOS
Type image sensor is being reviewed.

In view of such trends in the world, the applicant of the present application has improved the MOS type image sensor and applied for a patent for a sensor element having a carrier pocket (high-concentration buried layer) under the channel region (Japanese Patent Application No. 10-96). -186453
No.) to obtain a patent (Registration No. 2935492). In the invention according to this patent (Registration No. 2935492), in order to reduce the noise by suppressing the injection of photo-generated charges into the surface defects of the semiconductor layer, the light-receiving diode 111 has photo-generated charges (holes in this case). It has a buried structure for. That is, the n-type impurity region is formed in the surface layer of the p-type well region, the p-type well region is formed integrally with the p-type base region of the optical signal detecting MOS transistor, and the n-type impurity region is formed. Impurity region is integrally formed with the n-type drain region. Therefore, the structure is such that the photo-generated charges generated in the p-type well region of the light receiving diode 111 portion contribute to the detection of the optical signal.

This MOS type image sensor has a circuit configuration shown in FIG. 8 of a patent (registered number 2935492),
In the operation, there is an initialization period-accumulation period-reading period. During the initialization period, a high reverse voltage is applied to each electrode to deplete it, and the photogenerated holes remaining in the hole pocket 25 are emitted. Light-generated holes are generated by light irradiation during the accumulation period and accumulated in the hole pocket 25, and an optical signal proportional to the accumulation amount of the photo-generated holes is detected during the reading period.

[0005]

However, the CMO
The S circuit is in the direction of lowering the voltage, which conflicts with the demand for applying a high voltage during the initialization period to accelerate the initialization. The present invention was created in view of the above-mentioned problems of the prior art, and provides a solid-state imaging device and a driving method thereof capable of achieving both low voltage operation of a CMOS circuit and application of a high voltage during an initialization period. To do.

[0006]

In order to solve the above-mentioned problems, the present invention relates to a solid-state image pickup device, and as a basic configuration thereof, as shown in FIG. 4, a light receiving diode 111 and an optical signal detection adjacent to the light receiving diode 111. Insulated gate type field effect transistor (MOS transistor) 112 for each unit pixel 101, and MOS transistor 1
A gate electrode 12 is connected to a vertical scanning signal (VSCAN) driving scanning circuit 102, and a source region is a boosting scanning circuit 10.
It is characterized by being connected to 8.

In each unit pixel 101, the light receiving diode 111 and the MOS transistor 112 are formed in well regions 15a and 15b connected to each other, and MO
It is characterized by having a high-concentration buried layer (carrier pocket) 25 for accumulating photo-generated charges in the well region 15b in the peripheral portion of the source region of the S transistor 112.

In addition to the above structure, the drain region is connected to the drain voltage (VDD) driving scanning circuit 103, and the source region is connected to the constant current source 106 and the video signal output terminal 107 via the switches 105a and 105b. . The light detection signal input terminals 28a of the switches 105a and 105b are connected to the source region, the light signal output terminals 28C of the switches 105a and 105b are connected to the constant current source 106 and the video signal output terminal 107, and the HS of the switches 105a and 105b are connected.
The CAN input terminal 28b is connected to the horizontal scanning signal (HSCAN) input scanning circuit 104 via the HSCAN supply line 27a. In the driving method of the present invention, the booster circuit 1
22 is connected to the source region of the MOS transistor 112 for detecting an optical signal, the channel is closed at the time of switching from the accumulation period to the initialization period, and a voltage is applied from the booster circuit 122 to the source region, so that the gate electrode 19 In addition, through the capacitance between the source region 16 and the gate electrode 19, the gate voltage applied during the accumulation period is further increased by the booster circuit 12.
A boosted voltage higher than the power supply voltage of the VSCAN driving scan circuit 102 is applied from 2. As a result, a high voltage is applied to the gate electrode 19, so that the operation of sweeping out the carriers from the carrier pocket 25 can be accelerated.

When the well region or the like has a conductivity type opposite to the above, that is, when the high-concentration burying layer is n-type, the high-concentration burying layer becomes an electron pocket (carrier pocket) and accumulates photo-generated electrons. It will be.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to an embodiment of the present invention. Figure 1
As shown in FIG.
11 and the optical signal detecting MOS transistor 112 are provided adjacent to each other. As the MOS transistor 112, an n-channel MOS (nMOS) having a low concentration drain structure (LDD structure) is used.

The light receiving diode 111 and the MOS transistor 112 are formed in different well regions, that is, the first well region 15a and the second well region 15b, and the well regions 15a and 15b are connected to each other. The first well region 15a at the portion of the light receiving diode 111 constitutes a part of a region where charge is generated by light irradiation. The second well region 15b in the portion of the MOS transistor 112 constitutes a gate region in which the threshold voltage of the channel can be changed by the potential applied to this region 15b.

The portion of the MOS transistor 112 has a low concentration drain (LDD) structure. Drain region 1
7a and 17b are formed so as to surround the outer peripheral portion of the ring-shaped gate electrode 19, and the source region 16 is formed so as to be surrounded by the inner periphery of the ring-shaped gate electrode 19.
The low-concentration drain region 17a extends to form the impurity region 17 of the light-receiving diode 111 having the same impurity concentration as the low-concentration drain region 17a. That is,
The impurity region 17 and the low-concentration drain region 17a are integrally formed so that most of the region is on the surface layer of the first and second well regions 15a and 15b connected to each other. In addition, the impurity region 17 and the low-concentration drain region 1
A high-concentration drain region 17b serving as a contact layer is formed on the outer peripheral portion of 7a so as to avoid the light-receiving portion and be connected to the low-concentration drain region 17a.

Further, the carrier pocket (high-concentration buried layer) 25, which is a characteristic of this MOS type image sensor, is in the second well region 15b below the gate electrode 19,
The source region 16 is formed around the source region 16 so as to surround the source region 16. The drain regions 17a and 17b are connected to the drain voltage (V
DD) supply line (or drain electrode) 22 and the gate electrode 19 is a vertical scan signal (VSCAN) supply line 21.
And the source region 16 is connected to the vertical output line (or source electrode) 20.

Further, the light receiving window 24 of the light receiving diode 111
Areas other than the above are shielded from light by the metal layer (light-shielding film) 23. In the element operation for detecting the optical signal in the MOS image sensor, the sweep period (initialization period)
− Accumulation period − Readout period − Sweep period (initialization period) −
・ In this way, the sweep period (initialization period) -accumulation period-
A series of processes of the reading period is repeated.

In the sweep period (initialization period), before the photo-generated charges (photo-generated carriers) are accumulated, the photo-generated charges remaining after the reading is completed, the acceptors, the donors, etc. are neutralized, or the surface quasi-surface is neutralized. Holes and electrons captured in
The residual charge before reading the optical signal is discharged from the semiconductor, and the carrier pocket 25 is emptied. Source region 16
+ About the drain regions 17a and 17b and the gate electrode 19
A positive high voltage of 5 V or more, usually about 7 to 8 V is applied.

In the accumulation period, carriers are generated by light irradiation, and holes of the carriers are first and second holes.
The well regions 15a and 15b are moved to be accumulated in the carrier pocket 25. Drain regions 17a, 17b
A positive voltage of about +2 to 3 V is applied to the gate electrode 19, and a low positive or negative voltage that keeps the MOS transistor 112 in the cutoff state is applied to the gate electrode 19.

In the read period, the change in the threshold voltage of the MOS transistor 112 due to the photo-generated charges accumulated in the carrier pocket 25 is read as the change in the source potential. M
In order for the OS transistor 112 to operate in a saturated state,
A positive voltage of approximately +2 to 3V is applied to the drain regions 17a and 17b, and the gate electrode 19 is approximately +2 to 3V.
A positive voltage of V is applied.

Next, the device structure of the MOS type image sensor according to the embodiment of the present invention will be described with reference to sectional views. FIG. 2A is a cross-sectional view corresponding to the cross-sectional view taken along the line AA of FIG. 1, showing the device structure of the MOS image sensor according to the embodiment of the present invention. Figure 2
FIG. 6B is a diagram showing a state of the potential along the surface of the semiconductor substrate.

As shown in FIG. 2A, the impurity concentration is 1 ×
An impurity concentration of 1 × 1 is formed on a substrate (first semiconductor layer) 11 made of p-type (first conductivity type) silicon of 10 ¹⁸ cm ⁻³ or more.
An epitaxial layer (second semiconductor layer) 12 is formed by epitaxially growing n-type (second conductivity type) silicon of about 0 ¹⁵ cm ⁻³ . The light receiving diode 111 and the optical signal detecting MOS transistor 1 are formed on the epitaxial layer 12.
A plurality of unit pixels 101 including 12 are formed. A field insulating film (element isolation insulating film) 14 is formed by selective oxidation (LOCOS) on the surface of the epitaxial layer 12 between the adjacent unit pixels 101 so as to separate each unit pixel 101. Furthermore, the p-type element isolation region 13 is formed below the field insulating film 14 and above the substrate 11 so as to include the entire interface between the epitaxial layer 31 and the field insulating film 14 and separate the n-type epitaxial layer 12. Are formed.

Next, details of the light receiving diode 111 will be described with reference to FIG. Light receiving diode 111
Is the epitaxial layer 12, the p-type first well region 15a formed on the surface layer of the epitaxial layer 12, and the surface layer of the first well region 15a.
And an n-type impurity region 17 extending to the surface layer of. The p-type substrate 11 is the first part of the light receiving diode 111.
Forming a first semiconductor layer of conductivity type. The n-type epitaxial layer 12 also constitutes a second semiconductor layer of the second conductivity type.

The impurity region 17 is a low concentration drain (LD
D) MOS transistor 11 for optical signal detection having a structure
It is formed so as to extend from the second low-concentration drain region 17a and has almost the same impurity concentration as the low-concentration drain region 17a. Since the impurity concentration of the impurity region 17 is low, the shallower impurity region 17 is formed. Therefore, blue light, which has a short wavelength and is rapidly attenuated as the distance from the surface is increased, can be received with sufficient intensity.

In the accumulation period described above, the impurity region 17 is connected to the drain voltage supply line 22 and biased to a positive potential. At this time, a depletion layer spreads from the boundary surface between the impurity region 17 and the first well region 15a to the entire first well region 15a and reaches the n-type epitaxial layer 12. On the other hand, the substrate 11 and the epitaxial layer 1
The depletion layer spreads from the boundary surface with 2 to the epitaxial layer 12 and reaches the first well region 15a.

In the first well region 15a and the epitaxial layer 12, the potential distribution is such that the potential gradually decreases from the substrate 11 side toward the surface side.
The holes generated by light in the first well region 15a and the epitaxial layer 12 do not flow out to the substrate 11 side, and the first well region 15a and the epitaxial layer 12 do not flow out.
To stay inside. Since the first well region 15a and the epitaxial layer 12 are connected to the gate region 15b of the MOS transistor 112, these holes generated by light can be effectively used as charges for threshold voltage modulation of the MOS transistor 112. In other words, the first well region 15a and the epitaxial layer 1
The whole 2 becomes a carrier generation region by light.

Further, in the above light receiving diode 111, the light carrier generating region is arranged below the impurity region 17, and therefore the light receiving diode 111 has a buried structure for holes generated by light. is doing. Therefore, the noise can be reduced without being affected by the surface of the semiconductor layer having many trap levels. Next, details of the MOS transistor 112 for detecting an optical signal are shown in FIG.
This will be described with reference to (a).

The MOS transistor 112 portion is, in order from the bottom, a p-type substrate 11, an n-type epitaxial layer 12 formed on the substrate 11, and a p-type second layer formed in the epitaxial layer 12. Well region 15b. The p-type substrate 11 is a MOS transistor 11
Two parts constitute a first semiconductor layer of opposite conductivity type, and the epitaxial layer 12 similarly constitutes a second semiconductor layer of one conductivity type in the MOS transistor 112 part.

The MOS transistor 112 has a structure in which the outer periphery of the ring-shaped gate electrode 19 is surrounded by the n-type low-concentration drain region 17a. The n-type low-concentration drain region 17a is formed integrally with the n-type impurity region 17. The impurity region 17 is formed on the outer peripheral portion of the impurity region 17 extending from the low-concentration drain region 17a.
A high-concentration drain region 17b that is connected to the element isolation region 13 and extends to the element isolation insulating film 14 is formed. The high-concentration drain region 17b serves as a contact layer for the drain electrode 22.

An n-type source region 16 is formed so as to be surrounded by the ring-shaped gate electrode 19. The source region 16 has a high concentration in the central portion,
The peripheral area has a low concentration. The source electrode 20 is connected to the source region 16. The gate electrode 19 is formed in the second well region 1 between the drain region 17a and the source region 16.
It is formed on 5b via the gate insulating film 18. The surface layer of the second well region 15b below the gate electrode 19 becomes a channel region. Further, in order to keep the channel region in the inverted state or the depletion state at the normal operating voltage, the channel dope layer 15c is formed by introducing an n-type impurity having an appropriate concentration into the channel region.

In the second well region 15b below the channel region, in a partial region in the channel length direction, that is, in the peripheral portion of the source region 16, the source region 16 is surrounded by the p + type. Carrier pocket (high-concentration buried layer) 2
5 is formed. This p + type carrier pocket 2
5 can be formed by, for example, an ion implantation method. The carrier pocket 25 is formed in the second well region 15b below the channel region formed on the surface.
The carrier pocket 25 is preferably formed so as not to cover the channel region.

In the above-mentioned p + type carrier pocket 25, the potential of the photo-generated charges with respect to the photo-generated holes becomes low. Therefore, when a voltage higher than the gate voltage is applied to the drain regions 17a and 17b, the photo-generated holes are generated. It can be collected in the carrier pocket 25. Figure 2
(B) shows a potential diagram in a state in which photo-generated holes are accumulated in the carrier pocket 25 and electrons are induced in the channel region to generate an inversion region. This accumulated charge changes the threshold voltage of the MOS transistor 112.
Therefore, the optical signal can be detected by detecting the change in the threshold voltage.

By the way, during the above-mentioned carrier sweep period, a high voltage is applied to the gate electrode 19, and the electric field generated thereby sweeps out the carriers remaining in the second well region 15b to the substrate 11 side. in this case,
Due to the applied voltage, a depletion layer spreads from the boundary surface between the channel dope layer 15c in the channel region and the second well region 15b to the second well region 15b, and the boundary between the p-type substrate 11 and the epitaxial layer 12 is increased. From the surface, a depletion layer spreads to the epitaxial layer 12 below the second well region 15b.

Therefore, the range of the electric field caused by the voltage applied to the gate electrode 19 is mainly the second well region 15
b and the epitaxial layer 12 under the second well region 15b. In the MOS type image sensor according to the above-described embodiment, the p-type substrate 11 including the lower surface of the element isolation insulating film 14 on the p-type substrate 11 below the element isolation insulating film 14 is separated so as to isolate the epitaxial layer 12. The element isolation region 13 is formed. That is, the defects generated at the interface between the element isolation insulating film 14 and the element isolation region 13 are
Is surrounded by.

Therefore, when a positive voltage is applied to the n-type drain regions 17a and 17b during the initialization period and the accumulation period, the p-type well regions 15a and 15b or p type well regions 15a and 15b are formed.
The depletion layer extending from the substrate 11 of the mold into the epitaxial layer 12 reaches only the outer peripheral portion of the element isolation region 13,
Since it does not spread inside the element isolation region 13, the defect generated at the interface is not covered by the depletion layer. Therefore, it is possible to prevent the charge trapped in the defect from being released into the depletion layer, and thereby suppress the fixed pattern noise due to the accumulation of the charge in the hole pocket 25 due to the defect. .

Next, with reference to FIG. 4, the overall structure of a MOS image sensor using the unit pixel having the above structure will be described. FIG. 4 shows an MO according to the embodiment of the present invention.
The circuit block diagram of an S type image sensor is shown. As shown in FIG. 4, this MOS type image sensor has a two-dimensional array sensor configuration, and the unit pixel 10 having the above-described structure is used.
1 are arranged in a matrix in the column direction and the row direction.

A vertical scanning signal (VSCAN) driving scanning circuit 102 and a drain voltage (VDD) driving scanning circuit 103 are arranged on the left and right sides of the pixel region. The vertical scanning signal supply lines 21a and 21b are provided for each row from the driving scanning circuit 102 for the vertical scanning signal (VSCAN). The vertical scanning signal supply lines 21a and 21b are connected to the gates of the MOS transistors 112 in all the unit pixels 101 arranged in the row direction.

Further, the drain voltage supply lines (VDD supply lines) 22a and 22b are provided one by one for each row from the drive scanning circuit 103 for the drain voltage (VDD). The drain voltage supply lines (VDD supply lines) 22a and 22b are connected to the drains of the optical signal detection MOS transistors 112 in all the unit pixels 101 arranged in the row direction. Also,
Different vertical output lines 20a and 20b are provided for each column,
The vertical output lines 20a and 20b are connected to the sources of the MOS transistors 112 in all the unit pixels 101 arranged in the column direction.

Furthermore, M as a switch that is different for each column
OS transistors 105a and 105b are provided, and the vertical output lines 20a and 20b are connected to the drains (photodetection signal input terminals) 28a and 29a of the MOS transistors 105a and 105b, respectively. Gates (horizontal scanning signal input terminals) 28b and 29b of the respective switches 105a and 105b are connected to a driving scanning circuit 104 for a horizontal scanning signal (HSCAN).

The sources (light detection signal output terminals) 28c and 29c of the respective switches 105a and 105b pass through a common constant current source (load circuit) 106 and the video signal output terminal 1
It is connected to 07. That is, M in each unit pixel 101
The source of the OS transistor 112 is connected to the constant current source 106 to form a source follower circuit for each pixel. Therefore, the potential difference between the gate and the source and the potential difference between the bulk and the source of each MOS transistor 112 are determined by the connected constant current source 106.

The vertical scanning signal (VSCAN) and the horizontal scanning signal (HSCAN) sequentially drive the MOS transistor 112 of each unit pixel 101 to read out a video signal (Vout) proportional to the amount of incident light. Further, the boosting scanning circuit 108 is provided, and the boosting voltage output lines 30a and 30b from the boosting scanning circuit 108 are respectively connected to the vertical output lines 20a and 2a.
It is connected to 0b. That is, each unit pixel 101 for each column
The boosted voltage is applied to the source region of the MOS transistor 112. The boosted voltage is further applied to the gate as a result through the gate-source capacitance. As a result, the electric field strength applied to the well region can be increased and the sweeping out of carriers can be promoted.

FIG. 5 is a circuit diagram showing details of the step-up scanning circuit 108 portion of FIG. As shown in FIG. 5, the boost scan circuit 108 includes a clock generation circuit 121 and a boost circuit 1.
22 and a precharge circuit 123. In the clock generation circuit 121, the inverters G1 to G
4 are connected in series. Also, inverters G2 and G3
A capacitor C1 for delaying a clock pulse is connected in parallel between the two. The clock input from the clock input terminal (CL /) is amplified and output from the output end of the clock generation circuit 121 to the booster circuit 122 with the same polarity without being inverted.

In the booster circuit 122, the input end branches in two directions. One is connected to the gate of the transistor T5, the other is further branched in two directions, is connected to the gate of the transistor T4, and is connected to the input terminal of the inverter G9. One end of the capacitor C2 is connected to the output end of the inverter G9, and the other end of the capacitor C2 is connected to the source of the transistor T4 and the drain of the transistor T5.
The potential at the output end of the inverter G9 is indicated by CLD. Also,
The drain of T4 is connected to the 3.3V power source, and the output terminal of T5 is the boosted voltage output line 30 connected to the vertical output line 20a.
It is connected to a. Set the potential of the boosted voltage output line 30a to VP
Indicated by Sn.

When the clock pulse H (High) is input, T4 and T5 are opened, and 3.3V is applied to C2 through T4.
Is charged. In addition, the boosted voltage output line 30 passes through T5.
3.3V is output to a. Further, when L (Low) is input, 3.3V is charged in C2 through the inverter G9. At this time, if C2 is charged with 3.3V immediately before, the voltage across the terminals of C2 is 6.6V in total.

In the precharge circuit 123, the input terminal (PR /) is connected to the inverter G10, and the output terminal of the inverter G10 is connected to the transistor T6. The potential at the output end of the inverter G10 is indicated by PR. The source of T6, which is the output terminal of the precharge circuit 123, is connected to the boosted voltage output line 30a. Precharge circuit 123
When H is input to the input terminal (PR /) of, T6 is closed,
When L is input, T6 is opened and the ground potential is output to the boosted voltage output line 30a.

Next, the VSCAN drive scanning circuit 102 and V
An example of a detailed circuit of the DD drive scanning circuit 103 will be described. The VSCAN driving scanning circuit 102 and the VDD driving scanning circuit 103 share an input end, and the same scanning signal (VSCNn) is input from this input end. First, VSCAN
Details of the drive scanning circuit 102 will be described below. The input end is branched in two directions, one is connected to the input end of the inverter G8, and the other is branched to be connected to one input end of the two-input inverters G5 and G6. The output end of G6 is branched and one is connected to the other input end of G5 and the other is V
It is connected to the gate of a transistor T3 which is a switch of the DD drive scanning circuit 103. Set the gate potential of T3 to S
Shown as pbn.

The inverting output terminal of the clock generating circuit 121 is connected to the other input terminal of G6. The output terminal of G5 is connected to the input terminal of the inverter G7, and the output terminal of the inverter G7 is connected to the gate of the transistor T1. The potential at the output end of the inverter G7 is indicated by Vspn.
The output terminal of the inverter G8 is connected to the gate of the transistor T2.

The drains of the transistors T1 and T2 are connected to each other, and the source of T1 is connected to a 3.3V power source.
The source of 2 is grounded. The drains of T1 and T2 serve as the output terminals of the VSCAN driving scan circuit 102, and VS
It is connected to the CAN supply line 21a. The potential of the VSCAN supply line 21a is represented by VPPG (VSCAN). In the accumulation period, when T1 is off among T1 and T2, T2 is turned on and the ground potential appears, and during the read period, when T1 is turned on, T2 is turned off and approximately 2V appears at the output terminal. Further, in the initialization period, both T1 and T2 are turned off, the VSCAN supply line 21a becomes floating, and the gate potential of the MOS transistor 112 appears on the VSCAN supply line 21a.

A transistor T3 is provided as a switch of the VDD drive scanning circuit 103. The gate of T3 is connected to the output terminal of G6, the drain is connected to the 3.3V power supply, and the source, which is the output terminal of T3, is the VDD supply line 22a.
Connected with. The VDD supply line 22a is a unit pixel 1
It is connected to the drain of the MOS transistor 112 in 01. The potential of the VDD supply line 22a is set to Vpdn (VD
This is indicated by D).

FIG. 6 shows a timing chart of each input / output signal for operating the MOS type image sensor according to the present invention. p-type first and second well regions 15a,
This is applied when 15b is used and the optical signal detecting transistor 112 is an nMOS. Next, the optical signal detection operation of the series of continuous solid-state image pickup devices will be briefly described with reference to FIGS. As described above, the optical signal detection operation repeats a series of processes including the sweep period (initialization period) -accumulation period-readout period. Here, for convenience, the description starts from the accumulation period.

First, in the accumulation period, the boost scan circuit 1
08, a low gate voltage is applied to the gate electrode 19 of the optical signal detecting MOS transistor 112, and the drain region 17
A voltage (VDD) of about 2 to 3 V necessary for the operation of the transistor is applied to a and 17b. At this time, the first well region 15a, the second well region 15b and the epitaxial layer 12 are depleted. Then, the drain regions 17a, 1
An electric field is generated from 7b toward the source region 16.

Then, in the accumulation period immediately before the read period, the clock pulse L is input to the input end (PR /) of the precharge circuit 123, and the output end is set to the ground potential (the source potential of the MOS transistor 112). . At this time, the L of the clock pulse (VSCNn) is input to the input end of the VSCAN drive scanning circuit 102, and VSCA
The output of the N drive scanning circuit 102 is at the ground potential (becomes the gate potential of the MOS transistor 112). VD
The output (Vpdn) of the D drive scanning circuit 103 is approximately 2V.

Then, the light receiving diode 111 is irradiated with light. At this time, the carrier generation region of the portion of the light receiving diode 111 is formed near the surface, so that the wavelength such as blue light is short and the sensitivity is improved even for light that is easily attenuated near the surface. Since the total thickness is thick, the sensitivity is improved even for light having a long wavelength that reaches deep inside the light receiving portion such as red light. Therefore, it is possible to efficiently generate electron-hole pairs (photogenerated charges).

Due to the electric field, photogenerated holes of the photogenerated charges are injected into the gate region 15b of the optical signal detecting MOS transistor 112, and the carrier pocket 25 is formed.
Accumulated in. As a result, the width of the depletion layer extending from the channel region to the gate region 15b therebelow is limited, and the potential near the source region 16 is modulated, so that the threshold voltage of the MOS transistor 112 changes.

Next, in the read period, a clock pulse (VSCN) is applied to the input terminal of the VSCAN driving scanning circuit 102.
Enter H in n). As a result, the output (VPGn) of the VSCAN drive scanning circuit 102 is set to approximately 2V (becomes the gate potential of the MOS transistor 112). at the same time,
A clock pulse (P
R /) H is input and output (VPSn) is 3.3V (M
It becomes the source potential of the OS transistor 112).
On the other hand, the VDD drive scanning line 22a is maintained at about 2V.

That is, a gate voltage of about 2 to 3 V at which the MOS transistor 112 can operate in a saturated state is applied to the gate electrode 19, and a voltage VDD of about 2 to 3 V at which the MOS transistor 112 can operate at the drain regions 17a and 17b. Is applied. As a result, a low electric field inversion region is formed in a part of the channel region above the carrier pocket 25, and a high electric field region is formed in the remaining part. At this time, the drain voltage-current characteristic of the MOS transistor 112 shows a saturation characteristic as shown in FIG.

Further, a constant current source 106 is connected to the source regions 16a and 16b of the MOS transistor 112 to flow a constant current. As a result, the MOS transistor 112
Forms a source follower circuit. Therefore, the source potential changes following the fluctuation of the threshold voltage of the MOS transistor 112 due to the light generation hole, which causes a change in the output voltage.

In this way, the video signal (Vout) proportional to the light irradiation amount can be taken out. Next, the initialization operation starts. Carrier pocket 2 for initialization operation
5, the charges remaining in the first and second well regions 15a and 15b are discharged. That is, the VDD supply lines 22a and 22b
A high positive voltage of about 7 to 8 V is applied to the drain of the MOS transistor 112 for detecting an optical signal through the gate and to the gate through the VSCAN supply lines 21a and 21b.

Initialization period (TW period) immediately after the reading period
Will be described with reference to the timing chart of FIG. Figure 7
As shown in, a clock pulse (PR /) having a pulse width TW1 shorter than TW and a potential level L is input to the input terminal of the precharge circuit 123 of the step-up scanning circuit 108. The inverted output (PR) of G10 is from TW1 to TW
2 Delay and fall. And the clock pulse (PR
/) Corresponding to the rising edge of the clock generation circuit 121
The voltage of the clock pulse (CL /) input to the input terminal of is switched from H to L. This causes T3 to close and VD
The D supply line 22a becomes floating. Also, T2 is already closed, T1 is closed and VSCAN supply line 21
a also becomes floating.

On the other hand, between TW0 and TW1, T4 is opened by the clock pulse (CL /) of the clock generation circuit 121, and C2 is charged with 3.3V. Corresponding to the fall of the inverted output (PR) of G10 of the precharge circuit 123, T6 is closed, the vertical output line 20a becomes floating, and the fall of CL / causes C2 to rise.
Is further charged with 3.3V, and 6.6V appears on the vertical output line 20a. Moreover, since the VSCAN supply line 21a is in a floating state, the potential of the gate electrode 19 becomes about 8V in addition to the already charged 2V via the capacitance between the source and the gate because the source becomes 6.6V. It becomes 0.6V.

At this time, the voltage applied to the gate electrode 19 is the second well region 15b and the second well region 15b.
Underlying epitaxial layer 12. The high electric field generated at this time can surely sweep out the carriers from the second well region 15b. As described above, by providing the booster circuit, the carriers can be more surely swept out with a low power supply voltage.

In addition, during the initialization period and the storage period, when a positive voltage is applied to the n-type drain regions 17a and 17b, the interface between the element isolation insulating film 14 and the semiconductor layer is covered with the element isolation region 13. As a result, the interface is not exposed to the depletion layer extending from the well region, and thus it is possible to prevent the charge trapped by defects in the interface from being released into the depletion layer. As a result, fixed pattern noise due to the accumulation of charges in the hole pocket 25 due to defects can be suppressed.

Further, the n-type drain regions 17a and 17 are formed.
Since a drain electrode 22 is connected near the element isolation insulating film 14 when a positive voltage is applied to b, even if the charge is discharged from a defect near the element isolation insulating film 14, the charge is released into a hole. The flow toward the pocket 25 can be suppressed. As a result, fixed pattern noise due to the accumulation of charges in the hole pocket 25 due to defects can be further suppressed.

As described above, according to the embodiment of the present invention, by connecting the booster circuit 122 to the source region of the optical signal detecting MOS transistor 112, carriers can be swept out more reliably at a low power supply voltage. it can. In the initialization period and the accumulation period, fixed pattern noise due to the accumulation of charges in the hole pocket 25 due to the defect generated at the interface between the element isolation insulating film 14 and the element isolation region 13 can be further suppressed.

Further, in a series of processes of sweeping operation (initializing operation) -accumulating operation-reading operation, when the photogenerating hole moves, it is ideal that it does not interact with the noise source on the semiconductor surface or in the channel region. A photoelectric conversion mechanism can be realized. Further, by accumulating charges in the carrier pocket 25, as shown in FIG. 3, the MOS transistor 112 can be operated in a saturated state, and since the source follower circuit is formed, the threshold voltage due to the photo-generated charges is increased. The change can be detected as a change in the source potential. Therefore, photoelectric conversion with good linearity can be performed.

Although the present invention has been described in detail above with reference to the embodiments, the scope of the present invention is not limited to the examples concretely shown in the above embodiments, and does not depart from the scope of the present invention. Modifications of the above embodiment are included in the scope of the present invention. For example, in the above embodiment, the first and second well regions 15a and 15b are formed in the n-type epitaxial layer 12 on the p-type substrate 11,
In place of the p-type epitaxial layer 12, an n-type impurity is introduced into the p-type epitaxial layer to form an n-type well layer, and the first and second well regions 1 are formed in the n-type well layer.
5a and 15b may be formed.

Further, various modifications are conceivable as the structure of the solid-state image pickup device to which the present invention is applied. However, regardless of other structures, the light receiving diode and the MOS for detecting the optical signal are used.
The transistor and the transistor are adjacent to each other to form a unit pixel, and MO
A high-concentration buried layer (carrier pocket) may be provided in the p-type well region below the channel region of the S transistor and near the source region.

Further, although the p-type substrate 11 is used,
Alternatively, an n-type substrate may be used. In this case, in order to obtain the same effect as that of the above-described embodiment, all the conductivity types of each layer and each region described in the above-described embodiment may be reversed. In this case, the carriers to be stored in the carrier pocket 25 are electrons and holes.

[0066]

As described above, according to the present invention, the booster circuit is connected to the source region of the optical signal detecting MOS transistor, and the boosted voltage is applied to the source in the initialization period immediately after the reading period. The potential of the gate electrode can be made higher than the power supply voltage of the vertical scanning signal drive scanning circuit.

As a result, carriers can be swept out more reliably with a low power supply voltage.

[Brief description of drawings]

FIG. 1 is a plan view showing an element layout in a unit pixel of a solid-state image sensor used in a solid-state image sensor according to an embodiment of the present invention.

FIG. 2A is a cross-sectional view taken along line AA of FIG. 1, showing a structure of an element in a unit pixel of a solid-state imaging device used in the solid-state imaging device according to the embodiment of the present invention. . (B)
FIG. 4 is a diagram showing a potential state in which light generation holes are accumulated in carrier pockets and electrons are induced in a channel region to generate an inversion region.

FIG. 3 is a graph showing drain current-voltage characteristics of a MOS transistor for detecting an optical signal of a solid-state image pickup element used in the solid-state image pickup device according to the embodiment of the present invention.

FIG. 4 is a diagram showing an overall circuit configuration of a solid-state imaging device according to an embodiment of the present invention.

FIG. 5 is a circuit diagram showing details of a drive circuit of the solid-state imaging device according to the embodiment of the present invention.

FIG. 6 is a timing chart when operating the drive circuit of FIG.

7 is a timing chart showing in detail the operation at the time of switching from the reading period to the initialization period in the timing chart of FIG.

[Explanation of symbols]

Reference Signs List 11 substrate (first semiconductor layer) 12 n-type well layer (one conductivity type region, second semiconductor layer) 12a epitaxial layer (one conductivity type region, second semiconductor layer) 13 element isolation region 14 element isolation insulating film 15a First well region 15b Second well region 15c Channel dope layer 16a Low concentration source region 16b High concentration source region (contact layer) 17 Impurity region 17a Low concentration drain region 17b High concentration drain region (contact layer ) 18 gate insulating film 19 gate electrode 25 carrier pocket (high-concentration buried layer) 30a, 30b boosted voltage supply line 101 unit pixel 106 constant current source (load circuit) 107 video signal output terminal 108 boosted scanning circuit 111 light receiving diode 112 light Insulated gate type field effect transistor for signal detection (MOS transistor for optical signal detection Motor) 121 clock generation circuit 122 boost circuit 123 precharge circuit

Claims (10)

(57) [Claims] 1. A unit pixel comprising a light receiving diode and an insulated gate field effect transistor adjacent to the light receiving diode for detecting an optical signal, wherein the insulated gate field effect transistor has a gate in the vicinity of a source region. A solid-state imaging device having a high-concentration buried layer for accumulating carriers generated in the light-receiving diode, provided in a well region below the electrode, and a vertical scanning signal drive scanning circuit for outputting a vertical scanning signal voltage to the gate electrode. And a step-up scanning circuit that outputs a step-up voltage higher than a power supply voltage of the vertical scanning signal drive scanning circuit to the source region, and a step-up voltage higher than the vertical scanning signal voltage from the step-up scanning circuit to the source region. By applying a voltage, the source region and the gate electrode are selectively formed on the gate electrode to which the vertical scanning signal voltage is selectively applied. The boosted voltage is applied via the capacitance between the two to form a gate voltage raised by the vertical scanning signal voltage and the boosted voltage on the selected gate electrode, and the gate voltage is accumulated in the high-concentration buried layer. A solid-state imaging device, wherein carriers are swept from the high-concentration buried layer. 2. A unit pixel having a light receiving diode and an insulated gate field effect transistor adjacent to the light receiving diode for detecting an optical signal, wherein the insulated gate field effect transistor has a first conductivity type well. A source region of the second conductivity type formed on the surface layer of the region, and a drain region of the second conductivity type formed on the surface layer of the well region,
A channel region between the source region and the drain region, a gate electrode formed on the channel region via a gate insulating film, and formed inside the well region near the source region below the channel region. A solid-state imaging device having a first conductivity type high-concentration buried layer for accumulating carriers generated in the light-receiving diode; and a vertical scanning signal voltage connected to the gate electrode via a vertical scanning signal supply line. A vertical scanning signal drive scanning circuit that outputs a vertical scanning signal drive scanning circuit and a boosting scanning circuit that outputs a boosted voltage higher than a power supply voltage of the vertical scanning signal driving scanning circuit to the source region, By applying a boosted voltage higher than the vertical scanning signal voltage, the gate electrode to which the vertical scanning signal voltage is selectively applied is connected to the source region and the front electrode. A boosted voltage is applied through a capacitance between the gate electrode and the gate electrode to form a gate voltage raised by the vertical scanning signal voltage and the boosted voltage on the selected gate electrode and stored in the high-concentration buried layer. The solid-state imaging device, wherein the generated carriers are swept from the high-concentration buried layer. 3. The solid-state imaging device according to claim 2, further comprising a drain voltage drive scanning circuit connected to the drain region of the insulated gate field effect transistor via a drain voltage supply line, and the insulated gate field effect transistor. 7. A video signal output terminal connected to a source region of an effect transistor via a switch, and a horizontal scanning signal input scanning circuit for turning on or off the switch via a horizontal scanning signal supply line. 2. The solid-state imaging device according to 2. 4. The vicinity of the source region in which the high-concentration buried layer is formed is a partial region in the channel length direction from the drain region to the source region, and is on the source region side. The solid-state imaging device according to claim 2 or 3. 5. The solid-state imaging device according to claim 2, wherein the high-concentration buried layer is formed over the entire region in the channel width direction. 6. The gate electrode of the insulated gate field effect transistor has a ring shape, the source region is formed in a surface layer of the well region surrounded by the gate electrode, and the drain region is formed of the gate electrode. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is formed so as to surround the well region. 7. The solid-state imaging device according to claim 2, wherein the gate electrode of the insulated gate field effect transistor and its periphery are shielded from light. 8. The solid-state imaging device according to claim 2, wherein a load circuit is connected to a source region of the insulated gate field effect transistor to form a source follower circuit. . 9. The solid-state imaging device according to claim 8, wherein the source output of the source follower circuit is connected to the video signal output terminal. 10. The solid-state imaging device according to claim 2, wherein an initialization period for eliminating carriers remaining in the high-concentration buried layer, and a charge generated by light irradiation are applied to the initialization period. A method for driving a solid-state imaging device, wherein an accumulation period for accumulating in a high-concentration buried layer and a reading period for reading out an optical signal based on the photo-generated charges accumulated in the high-concentration buried layer are repeated in this order to read out an optical signal. In the state where the drain voltage supply line, the vertical scanning signal supply line, and the horizontal scanning signal supply line are in a floating state immediately after the readout period in the initialization period,
The boosted voltage is output from the boosted scanning circuit, and the boosted voltage is applied to the source region of the insulated gate field effect transistor, thereby boosting the boosted voltage via the capacitance between the source region and the gate electrode. A method for driving a solid-state imaging device, characterized in that carriers accumulated in the high-concentration buried layer are swept from the high-concentration buried layer by a gate voltage applied to a gate electrode and raised by the boosted voltage.