JP2001160620A - Solid-state image sensing element, its manufacturing method and solid-state image sensing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image sensing element which is capable of meeting requirements such as an improvement in red color sensitivity and a reduction in reset voltage at the same time. SOLUTION: A solid-state image sensing device is equipped with a photodetection diode formed in an opposite conductivity-type second semiconductor layer 15a in certain conductivity-type first semiconductor layers 12 and 32 and an optical signal detecting insulated gate field effect transistor which is formed in an opposite conductivity-type fourth semiconductor layer 15b inside a certain conductivity-type third semiconductor layer 12 and adjacent to the photodetection diode, where a carrier pocket 25 is provided inside the fourth semiconductor layer 15a, and a part of the first semiconductor layers 12 and 32 located under the second semiconductor layer 15a is set thicker than a part of the third semiconductor layer 12 under the fourth semiconductor layer 15b in a depthwise direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, a method for manufacturing the same, and a solid-state imaging device.
Threshold voltage modulation type M used for video cameras, electronic cameras, image input cameras, scanners, facsimile machines, etc.
The present invention relates to a solid-state imaging device using an OS-type image sensor, a method for manufacturing the same, and a solid-state imaging device.

[0002]

2. Description of the Related Art Semiconductor image sensors such as CCD type image sensors and MOS type image sensors are excellent in mass productivity, and have been applied to most image input device devices with the development of finer pattern technology. In particular,
In recent years, the power consumption is smaller than that of a CCD image sensor, and the sensor element and the peripheral circuit element are the same CMOS.
With the advantage that it can be created by technology, MOS
Type image sensors are being reviewed.

In view of such trends in the world, the present applicant has improved a MOS type image sensor, and has applied for a patent application for a sensor element having a carrier pocket (high-concentration buried layer) below a channel region (Japanese Patent Application No. Hei 10 (1998) -108). 186453
To obtain a patent (registration number 2935492).

[0004]

Incidentally, in a MOS type image sensor, spectral sensitivity characteristics, especially red sensitivity, are generally low, and it is desired to improve the sensitivity. The present invention provides an MO transistor capable of improving the red sensitivity while maintaining the performance of an optical signal detection MOS transistor.
An object of the present invention is to provide a solid-state imaging device using an S-type image sensor, a method for manufacturing the same, and a solid-state imaging device.

[0005]

In order to solve the above-mentioned problems, the present invention relates to a solid-state imaging device, and as shown in FIG. 2, a light receiving diode 111 and an insulated gate field effect transistor (MOS) for detecting an optical signal. Transistor) 112
Are adjacent to each other and the first conductive type first under the second semiconductor layer (first well region) 15a in the light receiving diode 111 portion.
The thickness of the semiconductor layers 12 and 32 is the optical signal detecting MOS.
It is characterized in that it is thicker than the thickness of the one conductivity type third semiconductor layer 12 under the fourth semiconductor layer (second well region) 15b in the transistor 112 portion.

The above structure can be manufactured by the manufacturing method of the present invention. As shown in FIG. 11A, the manufacturing method is to introduce a one-conductivity-type impurity into the seventh semiconductor layers 11 and 31 of the opposite conductivity type using the first mask 55, and
Forming a first buried layer 32 of one conductivity type inside the semiconductor layers 11 and 31 of FIG.
The first well region 15a of the opposite conductivity type is formed on the surface of the seventh semiconductor layers 11 and 31 and above the first buried layer 32 by introducing impurities of the opposite conductivity type into the semiconductor layers 11 and 31.
11B, and as shown in FIG. 11B, one conductivity type impurity is introduced into the surface layers of the seventh semiconductor layers 11 and 31 to be connected to the first buried layer 32, and Well region 15
a, and forming the one conductivity type region 12 so as to include the second mask 60 by using the second mask 60 as shown in FIG.
Of the opposite conductivity type is introduced into the inside of the semiconductor layers 11 and 31, and the second buried layer 3 of the opposite conductivity type having a higher impurity concentration than the seventh semiconductor layer 31 below the one conductivity type region 12.
3 and the second mask 60 is used to introduce an impurity of the opposite conductivity type into the surface layer of the one conductivity type region 12 above the second buried layer 33 by the second mask 60 to be connected to the first well region 15a. Forming a second well region 15b of the opposite conductivity type, and using the second mask 60 to form the second well region 15b;
13B, a step of introducing a one conductivity type impurity into the surface layer to form a channel dope layer 15c of one conductivity type, and a third mask 71 as shown in FIG.
b, an impurity of the opposite conductivity type is introduced into the second well region 15b, the impurity concentration being higher than that of the second well region 15b, and a high concentration buried impurity of the opposite conductivity type in the second well region 15b below the channel dope layer 15c. Step of forming layer 25 and FIG.
As shown in FIG. 15B, the step of thermally oxidizing the surface of the semiconductor substrate to form the gate insulating film 18 and the step of covering the high-concentration buried layer 25 as shown in FIG. Gate insulating film 1 such that buried layer 25 is close to the source region side.
Forming a gate electrode 19 on the gate electrode 8; FIG.
As shown in FIG. 3, a source region 16a and a drain region 17a of one conductivity type are formed on the surface layer of the second well region 15b on both sides of the gate electrode 19, and the first well region 15b is formed.
a) forming a one conductivity type impurity region 17 in the surface layer.

In this case, a part of the seventh semiconductor layers 11 and 31 corresponds to the first base layer, and a part of the seventh semiconductor layers 11 and 31 and the second buried layer 33 correspond to the second buried layer 33. The substrate layer (ie,
Substrate 11 and a sixth semiconductor layer), and the first buried layer 3
2 corresponds to a buried layer or a fifth semiconductor layer, the second buried layer 33 corresponds to a sixth semiconductor layer, the one conductivity type region 12 corresponds to a one conductivity type well region, Buried layer 32 and one conductivity type region 12 correspond to a first semiconductor layer (ie, a fifth semiconductor layer and one conductivity type well region), and first well region 15a corresponds to a second semiconductor layer. Correspondingly, the one conductivity type region 12 corresponds to a third semiconductor layer of one conductivity type (that is, a well region of one conductivity type), and the second well region 15b corresponds to a fourth semiconductor layer.

By the way, in order to improve the red sensitivity, the thickness of the n-type epitaxial layer (n-type layer) 12 on the p-type substrate 11 in the structure of the applicant's patent (registered number 2935492) is increased. desirable. However, when the epitaxial layer (n-type layer) 12 is made thicker, it is necessary to increase the reset voltage for initialization for discharging carriers, and the performance of the MOS transistor for detecting an optical signal is reduced. That is, in order to improve the red sensitivity and the reset efficiency, conflicting element structures are required, and it has been difficult to achieve both.

In the present invention, the light receiving diode 11
In one portion, during the accumulation period in which carriers are generated by light and accumulated in the high-concentration buried layer (carrier pocket) 25 of the opposite conductivity type, the impurity region 17 of the one conductivity type and the second conductivity type are accumulated by the applied voltage. The depletion layer extends from the boundary surface with the one well region 15a into the first well region 15a, and is formed between the first base layer 11 of the opposite conductivity type and the first semiconductor layers 12 and 32 of the one conductivity type. The depletion layer extends from the interface into the first semiconductor layers 12 and 32. Therefore, the photo-generated charges generated in the depleted first well region 15a and in the first semiconductor layers 12 and 32 contribute to the detection of the optical signal.

That is, by increasing the thickness of the first semiconductor layers 12 and 32, it is possible to effectively increase the thickness of the light receiving region with respect to light having a long wavelength such as red light. The sensitivity can be improved. On the other hand, in the portion of the MOS transistor 112 for detecting an optical signal, during the period of sweeping out (initialization) of the carriers from the high-concentration buried layer 25 and the second well region 15b, the applied voltage causes the channel region to have one conductivity type. The depletion layer extends from the interface between the channel dope layer 15c and the second well region 15b of the opposite conductivity type to the second well region 15b. Third semiconductor layer 12
The depletion layer extends from the boundary with the third semiconductor layer 12 below the second well region 15b.

Therefore, the electric field from the gate electrode 19 mainly reaches the second well region 15b to be depleted and the third semiconductor layer 12 below the second well region 15b. In the case of the present invention, the third semiconductor layer 12 below the second well region 15b is thin and has one conductivity type.
Is formed adjacent to the substrate 11 side of the second semiconductor layer, and the high-concentration sixth semiconductor layer 33 of the opposite conductivity type is formed. The extension of the depletion layer toward the sixth semiconductor layer 33 is restricted, and the width of the depletion layer extending from the boundary to the third semiconductor layer 12 is reduced. That is, the voltage from the gate electrode 19 is mainly applied to the second well region 15b.

As a result, a sharp potential change suitable for sweeping out carriers occurs in the second well region 15b and a strong electric field is applied, so that the high-concentration buried layer (carrier pocket) 25 and the second Well region 15
The stored carriers can be effectively swept out from b with a low reset voltage, and the reset efficiency can be improved.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to an embodiment of the present invention. FIG.
As shown in FIG.
11 and an optical signal detection MOS transistor 112 are provided adjacent to each other. These are different well regions, that is, a first well region (second semiconductor layer) 15a.
And a second well region (fourth semiconductor layer) 15b,
They are connected to each other. The first well region 15a of the light receiving diode 111 constitutes a part of a region where electric charge is generated by light irradiation, and the second well region 15b of the light signal detecting MOS transistor 112 corresponds to this region 15b.
To form a gate region in which the threshold voltage of the channel can be changed by the potential given to the gate region.

The impurity region 17 of the light receiving diode 111 and the drain region 17a of the MOS transistor 112 for detecting an optical signal are connected to each other in the first and second well regions 1.
5a and 15b are integrally formed so as to cover most of the area on the surface layer. The drain region 17 a is formed so as to surround the outer periphery of the ring-shaped gate electrode 19, and the source region 16 a is formed so as to be surrounded by the inner periphery of the ring-shaped gate electrode 19. Further, the carrier pocket (high-concentration buried layer) 25 which is a feature of the MOS image sensor is provided in the second well region 1 under the gate electrode 19.
5b, it is formed around the source region 16a around the source region 16a.

The drain region 17a is connected to a drain voltage (VDD) supply line 22 through a low-resistance contact layer 17b, and the gate electrode 19 is connected to a vertical scanning signal (VSCA).
N) The source region 16a is connected to the supply line 21, and the source region 16a is connected to the vertical output line 20 through the low-resistance contact layer 16b. The region other than the light receiving window 24 of the light receiving diode 111 is shielded from light by the metal layer (light shielding film) 23.

The element operation for detecting an optical signal in the MOS image sensor described above is repeatedly performed in the order of a sweeping period (initialization), an accumulation period, a reading period, a sweeping period (initialization), and so on. . In the sweep period (initialization), before the photo-generated charges (carriers) are accumulated, the photo-generated charges that have been read out, the acceptors, donors, and the like are neutralized, or holes trapped in the surface states. Residual charges before reading optical signals, such as electrons and electrons, are discharged from the semiconductor to empty the carrier pocket 25. A voltage of about +5 V or more, usually about 7 to 8 V is applied to the source region, the drain region, and the gate electrode.

In the accumulation period, carriers are generated by light irradiation and are moved in the first and second well regions 15a and 15b to be accumulated in the carrier pocket 25. A voltage of approximately +2 to 3 V is applied to the drain region, and a low voltage is applied to the gate electrode so that the MOS transistor 112 maintains the cutoff state. In the reading period, a change in the threshold voltage of the optical signal detection MOS transistor due to the photo-generated charges is read as a change in the source potential. MOS
A voltage of approximately +2 to 3 V is applied to the drain region and a voltage of approximately +2 to 3 V is applied to the gate so that the transistor 112 operates in a saturated state.

Next, the device structure of the MOS type image sensor according to the embodiment of the present invention will be described with reference to sectional views. FIG. 2A is a cross-sectional view corresponding to a cross-sectional view taken along line AA of FIG. 1 and illustrating a device structure of the MOS image sensor according to the embodiment of the present invention. FIG.
(B) is a diagram showing a state of a potential along the surface of the semiconductor substrate.

FIG. 3 is a sectional view taken along line BB of FIG. 1, and FIG. 4 is a sectional view taken along line CC of FIG. FIG.
As shown in (a), an impurity concentration of 1 × 1 is formed on a substrate 11 made of p-type silicon having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more.
An epitaxial layer 31 is formed by epitaxially growing p-type silicon having a thickness of about 0 ¹⁵ cm ⁻³ and a thickness of about 3 μm.
The above constitutes the seventh semiconductor layer of the opposite conductivity type.

A unit pixel 101 comprising a light receiving diode 111 and a MOS transistor 112 for detecting an optical signal is formed on the epitaxial layer 31. Then, adjacent unit pixels 10 are separated so that each unit pixel 101 is separated.
1, the field insulating film 14 on the surface of the epitaxial layer 31 and p over the entire epitaxial layer 31 thereunder.
An element isolation layer 13 which is a high-concentration region of the mold is formed.

Next, details of the light receiving diode 111 will be described with reference to FIGS. The light receiving diode 111 includes an n-type buried layer (one conductivity type buried layer, a first buried layer) 32 embedded in the epitaxial layer 31 and in contact with the substrate 11, and an n-type buried layer 32. A low-concentration n-type well layer (one conductivity type region) 12 formed thereon and a p-type first well region 1 formed on the surface of the n-type well layer 12
5a and an n-type impurity region 17 formed in the surface layer of the n-type well layer 12 so that most of the region overlaps the first well region 15a.

An n-type buried layer 32 having a relatively high impurity concentration is provided in the entire region between the substrate 11 and the n-type well layer 12, and the n-type layer (the first semiconductor layer) under the first well region 15a is formed. ) 1
2 and 32 are characterized by being thicker. FIG. 5 shows the impurity concentration distribution in this case. FIG.
It is a graph which shows the impurity concentration distribution and the corresponding potential distribution in the depth direction along DD line in the center part of the light receiving diode 111. The horizontal axis represents the depth (μm) from the surface of the semiconductor substrate represented by a linear scale, the left vertical axis represents the impurity concentration (cm ⁻³ ) represented by a logarithmic scale, and the right vertical axis represents the linear scale. Potential (arbitrary unit)
Is shown.

As shown in the impurity concentration distribution of FIG. 5, the n-type buried layer 32 has a thickness of about 1 μm, and the thickness of the n-type layer 12 below the first well region 15a is about 0.1 μm. 5 μm
In addition, the thickness of the n-type layers 12 and 32 under the first well region 15a of the light-receiving diode 111 is approximately 1.5 μm.
m. The thickness of the n-type layer 12 and the n-type buried layer 32 below the first well region 15a, the impurity concentration distribution, the peak value thereof, and the depth of the peak position are determined by the fact that the voltage applied during the accumulation period is approximately 2%. It is considered to be optimal at ~ 3V. N-type layer 12 under first well region 15a
In addition, the thickness of the n-type buried layer 32, the impurity concentration distribution, the peak value thereof, and the depth of the peak position mainly depend on the applied voltage during the carrier accumulation period. And the red light receiving sensitivity is set to be sufficiently high. Therefore, these values are applied during the thickness of the first well region 15a, the impurity concentration distribution, the peak value and the depth of the peak position, the attenuation characteristic of red light in the semiconductor, or the carrier accumulation period. It is appropriately changed depending on the voltage level and the like.

In the light receiving diode 111 having the above structure, the impurity region 17 is connected to the drain voltage supply line 22 and is biased to a positive potential during the above-described accumulation period. At this time, the impurity region 17 and the first well region 15
The depletion layer spreads from the boundary surface to the entire first well region 15a, and reaches the n-type well layer 12. On the other hand, the substrate 11
The depletion layer extends from the boundary between the n-type buried layer 32 and the n-type buried layer 32.
2 and the entire n-type well layer 12 thereover and reaches the first well region 15a.

FIG. 5 shows the potential distribution at this time. Since the portion of the light receiving diode 111 has the impurity concentration distribution as described above, the potential of the first well region 15a and the n-type layer 12/32 gradually decreases from the substrate 11 side to the surface side. It becomes a potential distribution. Therefore, the first well region 15a and the n-type layer 1
Holes generated by light within 2/32 are
These regions 15a and the n-type layer 12 /
32. These regions 15a and n
The mold layer 12/32 is a MOS transistor 11 for detecting an optical signal.
Since these holes are connected to the second gate region 15b, these holes generated by light can be effectively used as charges for threshold voltage modulation of the MOS transistor 112 for detecting an optical signal. In other words, the first well region 15a and the entire n-type layer 12/32 become a carrier generation region by light.

As described above, the presence of the n-type buried layer 32 increases the overall thickness of the carrier generation region of the light receiving diode 111. Thus, when light is applied to the light receiving diode 111, the carrier generation region becomes a light receiving portion having high sensitivity to light having a long wavelength reaching deep inside the light receiving portion, such as red light. Further, the light receiving diode 111
Is that a light-generating region is arranged below the impurity region 17 in that
Numeral 1 has an embedded structure for holes generated by light. Accordingly, noise can be reduced without being affected by the surface of the semiconductor layer having many interface trap levels.

Next, the details of the optical signal detecting MOS transistor (nMOS) 112 will be described with reference to FIGS.
And FIG. The MOS transistor 112 of this embodiment has a structure in which the outer periphery of the ring-shaped gate electrode 19 is surrounded by the n + -type drain region 17a. The n + type drain region 17a is formed integrally with the n + type impurity region 17. Further, an n + type source region 16a is formed so as to be surrounded by the ring-shaped gate electrode 19. That is, the gate electrode 19 is formed on the second well region 15b between the drain region 17a and the source region 16a via the gate insulating film 18. The surface layer of the second well region 15b below the gate electrode 19 becomes a channel region.

Furthermore, in order to maintain the channel region in an inverted state or a depletion state at a normal operating voltage, an appropriate concentration of an n-type impurity is introduced into the channel region to form a channel doped layer 15c. In the second well region 15b below the channel region and in a partial region in the channel length direction, that is, in the peripheral portion of the source region 16a, the p + -type carrier pocket is formed so as to surround the source region 16a. (High concentration buried layer) 25 is formed.
The p + type carrier pocket 25 can be formed by, for example, an ion implantation method. Carrier pocket 2
5 is formed in the second well region 15b below the channel region formed on the surface. It is desirable that the carrier pocket 25 be formed so as not to cover the channel region.

In the above p + -type carrier pocket 25, the potential of the photo-generated charges with respect to the photo-generated hole becomes low. Therefore, when a voltage higher than the gate voltage is applied to the drain region 17 a, the photo-generated hole is removed from the carrier pocket. 25 can be collected. FIG. 2B shows a potential diagram in a state in which light generation holes are accumulated in the carrier pocket 25 and electrons are induced in the channel region to generate an inversion region. The threshold voltage of the optical signal detection MOS transistor 112 changes due to the accumulated charge. Therefore, the detection of the optical signal can be performed by detecting the change in the threshold voltage.

FIG. 6 shows an E-channel MOS transistor 112 including the carrier pocket 25 in the MOS transistor 112 for detecting an optical signal.
5 is a graph showing an impurity concentration distribution in a depth direction along a line E and a corresponding potential distribution. The horizontal axis represents the depth (μm) from the surface of the semiconductor substrate represented by a linear scale, the left vertical axis represents the impurity concentration (cm ⁻³ ) represented by a logarithmic scale, and the right vertical axis represents the linear scale. The potential (arbitrary unit) is shown.

As shown in the impurity concentration distribution diagram of FIG. 6, a p-type buried layer (second buried layer) 33 having a high impurity concentration is provided between the substrate 11 and the n-type well layer 12. I have. That is, the n-type layer (third semiconductor layer) under the second well region 15b matches the n-type well layer 12 and is approximately 0.8 μm from the surface in the depth direction. There is a border. The thickness of the n-type layer below the second well region 15b is about 0.4 μm,
Layer (first semiconductor layer) 1 under well region 15a
2 and 32 are thinner than the thickness of about 1.5 μm.

The peak position of the impurity concentration of the p-type buried layer 33 is about 1.1 μm, and the impurity concentration at the peak position is about 5 × 10 ¹⁶ cm ⁻³ . N-type layer 12 below second well region 15b
And the thickness of the p-type buried layer 33, the impurity concentration distribution, the peak value thereof, and the depth of the peak position, the reset voltage is about 7 to
It is considered to be optimal at 8V. The impurity concentration distribution and the depth of the n-type layer 12 and the p-type buried layer 33 are mainly such that the depletion layer is p-type during the carrier sweeping period (initialization).
The electric field is set so as to spread not in the mold buried layer 33 but in the second well region 15b to concentrate the electric field. Accordingly, the thickness of the second well region 15b, the impurity concentration distribution in the region 15b, the peak value and the depth of the peak position, or the voltage (reset voltage) applied during the carrier sweep period (initialization). Is appropriately changed depending on the value of.

The carrier pocket 25 is formed at a depth of about 0.2 μm, and has a peak impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ . The thickness of the carrier pocket 25, the peak value of the impurity concentration thereof, and the depth of the peak position are set so that the carrier pocket 25 has a potential to sufficiently accumulate the carrier in the carrier pocket 25 mainly during the accumulation period and the readout period, and during the readout period. The setting is made so that the accumulation state of the carriers in the pocket 25 can sufficiently affect the channel region. Therefore, it is appropriately changed according to the state of the impurity concentration distribution of the first well region 15a serving as the background of the carrier pocket 25, the impurity concentration of the channel dope layer, the applied voltage during the accumulation period, the applied voltage during the reading period, and the like. .

By the way, during the above-described carrier sweeping period, a high voltage is applied to the gate electrode 19, the source region 16a, and the drain region 17a, and the electric field generated thereby causes the carriers remaining in the second well region 15b to be removed from the substrate 11 by the electric field. Sweeping out to the side. In this case, the applied voltage causes the depletion layer to spread from the boundary between the channel dope layer 15c in the channel region and the second well region 15b to the second well region 15b, and the p-type buried layer 33 and the n-type A depletion layer extends from the interface with the well layer 12 to the n-type well layer 12 below the second well region 15b.

Therefore, the range of the electric field by the voltage applied to the gate electrode 19 is mainly the second well region 15.
b and n-type well layer 12 under second well region 15b
Over. In the case of the present invention, the thickness of the n-type well layer 12 below the second well region 15b is small, and a high-concentration p-type buried layer 33 is formed adjacent to the n-type well layer 12 on the substrate 11 side. Have been. Therefore, the thickness of the depletion layer extending from the boundary between the p-type buried layer 33 and the n-type well layer 12 to the n-type well layer 12 during the sweeping period is reduced.

That is, as shown in the potential distribution diagram of FIG. 6, the voltage from the gate electrode 19 is mainly applied to the second well region 15b. In other words, a strong electric field that sweeps holes toward the substrate 11 due to a sudden potential change in the second well region 15b is mainly applied to the second well region 15b.
Carriers accumulated in the second well region 15b can be more reliably swept out of the second well region 15b with a low reset voltage, thereby improving reset efficiency.

Next, the overall configuration of a MOS image sensor using the unit pixels having the above structure will be described with reference to FIG. FIG. 8 shows an MO according to the embodiment of the present invention.
1 shows a circuit configuration diagram of an S-type image sensor. As shown in FIG. 8, the MOS image sensor has a two-dimensional array sensor configuration, and the unit pixels having the above-described structure are arranged in a matrix in a column direction and a row direction.

A driving scanning circuit 102 for vertical scanning signals (VSCAN) and a driving scanning circuit 103 for drain voltage (VDD) are arranged on the left and right sides of the pixel region. The vertical scanning signal supply lines 21a and 21b are provided one by one from the driving scanning circuit 102 of the vertical scanning signal (VSCAN) for each row. Each of the vertical scanning signal supply lines 21a and 21b is connected to the gate of the MOS transistor 112 in every unit pixel 101 arranged in the row direction.

The drain voltage supply lines (VDD supply lines) 22a and 22b are provided one by one from the drive scanning circuit 103 of the drain voltage (VDD) for each row. The drain voltage supply lines (VDD supply lines) 22a and 22b are connected to the drains of the optical signal detection MOS transistors 112 in all the unit pixels 101 arranged in the row direction. Also,
Different vertical output lines 20a and 20b are provided for each column,
Each of the vertical output lines 20a and 20b is connected to the source of the MOS transistor 112 in each of the unit pixels 101 arranged in the column direction.

Further, M as a switch different for each column
OS transistors 105a and 105b are provided, and each of the vertical output lines 20a and 20b is connected to one of drains (light detection signal input terminals) 28a and 29a of each of the MOS transistors 105a and 105b. Gates (horizontal scanning signal input terminals) 28b and 29b of the switches 105a and 105b are connected to a driving scanning circuit 104 for horizontal scanning signals (HSCAN).

The sources (light detection signal output terminals) 28c and 29c of the switches 105a and 105b are connected to a video signal output terminal 1 through a common constant current source (load circuit) 106.
07. That is, M in each unit pixel 101
The source of the OS transistor 112 is connected to the constant current source 106 to form a source follower circuit for each pixel. Therefore, the potential difference between the gate and the source and the potential difference between the bulk and the source of each MOS transistor 112 are determined by the connected constant current source 106.

The vertical scanning signal (VSCAN) and the horizontal scanning signal (HSCAN) are used to sequentially turn on the MOS of each unit pixel.
By driving the transistor 112, a video signal (Vout) proportional to the amount of incident light is read out. FIG. 9 shows a timing chart of each input / output signal for operating the MOS image sensor according to the present invention. p-type well region 1
5a, 15b, and an optical signal detecting transistor 1
This is applied when 12 is an nMOS.

As described above, the element operation is performed in a sweeping period (initialization) -an accumulation period-a reading period-a sweeping period (initialization).
-It is repeated as follows. Next, a light detection operation of a series of solid-state imaging devices will be briefly described with reference to FIGS. First, charges remaining in the carrier pocket 25 and the well regions 15a and 15b are discharged by an initialization operation. That is, a high positive voltage of about 6 V is applied to the drain of the optical signal detection MOS transistor 112 through the VDD supply lines 22a and 22b and to the gate through the VSCAN supply lines 21a and 21b, respectively. At this time, the n-type well layer 12 under the second well region 15b is formed.
Is thin, and the high-concentration p-type buried layer 33 is in contact with the n-type well layer 12 on the substrate 11 side.
The voltage applied to 9 applies only to the second well region 15b and a region very close to the second well region 15b. In other words, a strong electric field that sweeps holes toward the substrate 11 due to a sudden potential change in the second well region 15b is mainly applied to the second well region 15b, so that carriers can be more reliably swept with a low reset voltage. Therefore, the reset efficiency can be improved.

Next, a low gate voltage is applied to the gate electrode 19 of the MOS transistor for detecting an optical signal, and a voltage (VDD) of about 2 to 3 V required for the operation of the transistor is applied to the drain region 17a. At this time, the first well region 15a, the n-type well layer 12, and the n-type buried layer 32 are depleted, and the second well region 15b is depleted. Then, from the drain region 17a to the source region 16a
An electric field is generated toward.

Next, the light receiving diode 111 is irradiated with light. At this time, the entire thickness of the carrier generation region in the portion of the light receiving diode 111 is thick, so that even light with a long wavelength reaching deep inside the light receiving portion, such as red light, can be efficiently subjected to electron-positive. Hole pairs (photo-generated charges) can be created. Due to the electric field, the light-generating holes of the light-generated charges are converted into the optical signal detecting MOS transistor 1.
12 and the carrier pocket 2
5 is stored. As a result, the width of the depletion layer extending from the channel region to the gate region 15b thereunder is limited, and the potential near the source region 16a is modulated, so that the threshold voltage of the MOS transistor 112 for light signal detection changes.

Here, a gate voltage of about 2 to 3 V at which the MOS transistor 112 can operate in a saturated state is applied to the gate electrode 19, and a voltage VDD of about 2 to 3 V at which the MOS transistor 112 can operate is applied to the drain region 17a. Apply. As a result, a low electric field inversion region is formed in a part of the channel region above the carrier pocket 25, and a high electric field region is formed in the remaining part. At this time, the optical signal detection M
The drain voltage-current characteristics of the OS transistor 112 are as follows:
As shown in FIG. 7, a saturation characteristic is shown.

Further, the constant current source 106 is connected to the source region 16 of the MOS transistor 112 so that a constant current flows. As a result, the MOS transistor 112 forms a source follower circuit, and the
The source potential changes following the change in the threshold voltage of the S transistor, resulting in a change in the output voltage. In this manner, a video signal (Vout) proportional to the light irradiation amount can be obtained.

As described above, according to the embodiment of the present invention, in a series of processes of the sweeping operation (initialization), the storage operation, and the reading operation, when the light generation hole moves, the semiconductor surface or the channel An ideal photoelectric conversion mechanism that does not interact with a noise source in the region can be realized. Further, the transistor can be operated in a saturated state as shown in FIG. 7 by the charge accumulation in the carrier pocket 25,
In addition, since the source follower circuit is formed, a change in the threshold voltage due to the photo-generated charges can be detected as a change in the source potential. Therefore, photoelectric conversion with good linearity can be performed.

Next, a method of manufacturing the solid-state imaging device having the above structure will be described with reference to FIGS. The actual circuit configuration is complicated and differs from the planar arrangement of the elements described below. However, in FIGS. 10 to 18, for convenience of explanation of the manufacturing method, of all the elements used in this circuit, The different main elements are taken out and schematically shown so as to show how different element structures are created in a series of manufacturing steps. From the left side of the figure, the type of the selected element is p-CMOS (C
VMIS as an optical sensor, and p-channel MOS among the n-MOSs, n-CMOS (the n-channel MOS among the CMOS), enhancement n-MOS, and depletion n-MOS.

First, as shown in FIG. 10A, a substrate 1 made of p-type silicon having an impurity concentration of about 4 × 10 ¹⁸ cm ⁻³ is used.
A p-type silicon having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ is epitaxially grown on 1 to form an epitaxial layer 31 having a thickness of about 3 μm. The substrate 11 forms the entire first base layer and a part of the second base layer, and the epitaxial layer 31
Constitutes a part of the second base layer.

Next, as shown in FIG.
The field insulating film 14 is formed in the element isolation region by COS (LOCal Oxidation of Silicon). Subsequently, the pad insulating film 5 is formed in the element formation region surrounded by the element isolation region.
Form one. Next, openings 53a and 53b are respectively provided in an element isolation region between the enhancement n-MOS and the depletion n-MOS and in an element isolation region between the depletion n-MOS and the VMIS. n
-Form a resist mask 52 having an opening 53c over the entire CMOS formation region. Subsequently, a p-type impurity is ion-implanted through the openings 53a, 53b, 53c of the resist mask 52 and the field insulating film 14. Thereby, between the enhancement n-MOS and the depletion n-MOS, and between the enhancement n-MOS and the depletion n-MOS
A p-type element isolation layer 13 reaching the substrate 11 is formed in the epitaxial layer 31 below the field insulating film 14 between the substrate 11 and the VMIS, and the epitaxial layer 31 covering the entire region of the n-CMOS formation region is formed on the substrate 11. A p-type well layer 54 is formed to reach.

Next, as shown in FIG.
A resist mask (first mask) 55 having an opening 56 is formed in the formation region of the light receiving diode 111 in the S formation region. Subsequently, through the opening 56 of the resist mask 55, P over the pad insulating film 51, which becomes an n-type impurity, is formed.
31+ is deeply implanted, and B11 + which is a p-type impurity is implanted shallowly through the same opening 56 twice. Thereby, as shown in FIG. 5, the peak position is about 1.5 μm and the peak impurity concentration is about 1 × 10 ¹⁷ cm.
^-3 , an n-type buried layer (first buried layer) 32 in contact with the substrate 11, and a first well region (second (Semiconductor layer), peak position about 0.3 μm, peak impurity concentration about 6 × 10 ¹⁶
A p-type well layer 15a having a cm ⁻³ , a peak position of about 0.55 μm, and a peak impurity concentration of about 2 × 10 ¹⁶ cm ⁻³ is formed. Note that the n-type buried layer 32 forms a part of the first semiconductor layer.

Next, as shown in FIG.
A resist mask 57 having an opening 58 over the entire IS formation region is formed. Then, the resist mask 5
7 is ion-implanted through the opening 58.
Thereby, the peak position including the entire first well region 15a and reaching the n-type buried layer 32 at the lower end reaches a peak position of about 0.5.
An n-type well layer (opposite conductivity type region) 12 having a thickness of 5 μm and a peak impurity concentration of about 3 × 10 ¹⁶ cm ⁻³ is formed. The n-type well layer 12 constitutes a part of the first semiconductor layer and the entire third semiconductor layer.

After the step shown in FIG. 11B, the gate insulating film can be formed by removing the pad insulating film 51 and reoxidizing the surface of the semiconductor substrate. In the drawing, the same reference numeral 51 indicates both the pad insulating film and the gate insulating film formed by reoxidation. In this case, the thickness of the gate insulating film is preferably 60 nm or less. If the thickness is more than this, it is difficult to obtain a sharp impurity concentration distribution when the high concentration buried layer 25 is formed by ion implantation in the step of FIG.

Next, as shown in FIG. 12A, an opening 6 is formed over the entire depletion n-MOS formation region.
1b and the MO for optical signal detection in the VMIS formation region
A resist mask (second mask) 60 having an opening 61a in a region where the S transistor 112 is formed is formed. Subsequently, B11 + which is a p-type impurity is deeply ion-implanted through the openings 61a and 61b of the resist mask 60,
Further, B11 + which is a p-type impurity is ion-implanted shallowly through the same openings 61a and 61b. Further, As + which is an n-type impurity is ion-implanted shallowly through the same openings 61a and 61b.

Thus, in the depletion n-MOS formation region, a p-type buried layer 62, a p-type well layer 63 and a channel dope layer 64 are formed. On the other hand, in the VMIS forming region, as shown in FIG. 6, p-type buried layer peak positions about 1.2 [mu] m, the peak impurity concentration of about 5 × 10 ¹⁶ cm ^-3 (second
Buried layer) 33 and second well region 15 having a peak position of about 0.1 μm and a peak impurity concentration of about 1.2 × 10 ¹⁷ cm ⁻³ .
b and an n-type channel dope layer 15c having a surface concentration of about 2 × 10 ¹⁷ cm ⁻³ are formed. Note that the p-type buried layer 33 constitutes a part of the second base layer.

Next, as shown in FIG.
CMOS, n-CMOS and enhancement n-MOS
A resist mask 65 having an opening 66 is formed over the entire formation region. Subsequently, p-type impurities are ion-implanted shallowly through the openings 66 of the resist mask 65. As a result, p-type channel doped layers 67a to 67c are formed.

Next, as shown in FIG.
Resist mask 6 having opening 69 in MOS formation region
8 is formed. Subsequently, the opening 6 of the resist mask 68 is formed.
N-type impurities are ion-implanted through 9 to form an n-type well layer 70. Next, as shown in FIG.
A resist mask (third mask) 71 having an opening 72 in a region to be a carrier pocket (high-concentration buried layer) 25 of a MOS transistor for optical signal detection in a VMIS formation region.
To form Subsequently, the opening 72 of the resist mask 71 is formed.
B11 +, which is a p-type impurity, is ion-implanted.
As a result, as shown in FIG.
c, a peak position of about 0.2
A p + -type high-concentration buried layer 25 of μm and a peak impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ is formed.

Next, as shown in FIG.
A resist mask 73 having an opening 74 is formed over the entire formation region of MOS, n-CMOS, enhancement n-MOS, and depletion n-MOS.
Subsequently, the gate oxide film 51 is removed through the opening 74 of the resist mask 73, and the original gate insulating film 51 is left in the VMIS formation region.

Next, as shown in FIG. 14B, after removing the resist mask 73, the surface of the semiconductor substrate is thermally oxidized. Thereby, p-CMOS, n-CMOS, enhancement n-MOS, and depletion n-MOS
Gate oxide films 75a to 75d having a small thickness are formed in the formation region, and an oxide film is added to the surface of the VMIS formation region in addition to the oxide film thickness left in the previous step.
A thick gate insulating film 18 is formed. By increasing the thickness of the gate insulating film 18 in the VMIS formation region, the gate capacitance can be reduced, and the detection sensitivity of the photo-generated charges accumulated in the high-concentration buried layer, and thus the detection sensitivity of the optical signal, can be improved.

Next, as shown in FIG. 15A, a polysilicon film 76 is formed on the entire surface. Next, FIG.
As shown in the figure, the polysilicon film 76 is patterned,
The gate electrodes 76a to 76e, 19
To form Next, as shown in FIG.
A resist mask 77 having an opening 78 over the entire MOS formation region is formed. Subsequently, p-type impurities are ion-implanted through the opening 78 of the resist mask 77 and using the gate electrode 76e as a mask. This allows
The n-type well layer 70 on both sides of the gate electrode 76e has a source /
Drain regions 79a and 79b are formed.

Next, as shown in FIG.
After forming a resist mask 80 having an opening 81 over the entire formation region of CMOS, enhancement n-MOS, depletion n-MOS, and VMIS, the resist mask 80 is passed through the opening 81 and the gate electrodes 76b to 76d. , 19 are used as a mask to ion-implant an n-type impurity. As a result, the source / drain regions 82a and 82b, 82c and 82d, 82e and 8 are formed on both sides of the gate electrodes 76b to 76d and 19 in each forming region.
2f, 16a and 17a are formed.

Next, as shown in FIG. 17A, after removing the resist mask 80, a CVD (Chemical Vapor
An insulating film is formed by a Deposition method or the like. Subsequently, anisotropic etching is performed, and gate electrodes 76a to 76a are formed.
e, side walls 83 are formed on the side surfaces of 19; Next, as shown in FIG. 17B, a resist mask 84 having an opening 85 in a p-CMOS formation region is formed.
Subsequently, a p-type impurity is ion-implanted through the opening 85 of the resist mask 84 and using the gate electrode 76e and the sidewall 79 as a mask. Thus, contact layers 86a and 86b are formed in source / drain regions 79a and 79b, respectively.

Next, as shown in FIG.
An opening 88 is formed over the entire region where the MOS, enhancement n-MOS, and depletion n-MOS are formed, and an opening 88 is formed in the portion of the MOS transistor 112 for light signal detection and the portion of the light receiving diode 111 in the VMIS formation region. A resist mask 87 is formed. After that, an n-type impurity is ion-implanted through the opening 88 of the resist mask 87. Thereby, the source / drain regions 82a and 82b, 82c and 82d of each formation region,
82e and 82f, contact layers 89a and 89b, 89c and 89d, 89e and 89 in 16a and 17a.
f, 16b and 17b are formed.

Next, as shown in FIG. 18B, after removing the resist mask 87, the first interlayer insulating film 9 is formed.
0 is formed. Subsequently, the source / drain regions 82a and 82 of each MOS formation region are formed on the first interlayer insulating film 90.
2b, 82c and 82d, 82e and 82f, 79a and 79b, 16a and 17a.
The gate wiring layer 21 connected to the drain electrode or wiring layers 91a and 91b, 91c and 91d, 91e and 91f, 91g and 91h, 20 and 22 and the gate electrode 19 in the VMIS formation region is formed.

Subsequently, after the second interlayer insulating film 92 is formed, the source / drain electrodes or wiring layers 91a and 91b, 91c and 91d, 9 under the respective MOS formation regions are formed.
Upper source / drain electrodes or wiring layers 91a and 91 connected to 1e and 91f, 91g and 91h, 20
b, 91c and 91d, 91e and 91f, 91g and 91h, 20 are formed on the second-layer interlayer insulating film 92.

Next, after the third interlayer insulating film 93 is formed, a light shielding film 23 having an opening (light receiving window) 24 in the light receiving diode 111 is formed thereon. Thereafter, when a cover insulating film 94 covering the entire element surface is formed, a solid-state imaging device is completed. As described above, according to the embodiment of the present invention, since the unit pixel 101 includes the light receiving diode 111 and the MOS transistor 112, the pixel portion can be formed using the CMOS technology. Therefore, the pixel portion and the peripheral circuits such as the drive scanning circuits 102 to 104 and the constant current source 106 can all be formed on the same semiconductor substrate.

Thus, the manufacturing process can be simplified, and the size of the solid-state imaging device can be reduced by integrating circuit components. Examples of the solid-state imaging device include a video camera, a digital still camera, an image input camera scanner, and a facsimile. As described above, the present invention has been described in detail by the embodiment. However, the scope of the present invention is not limited to the example specifically shown in the above embodiment, and the scope of the present invention is not limited to the scope of the present invention. Modifications of the form are included in the scope of the present invention.

For example, the first well region 15a and the second well region 15b are formed separately, but they may be formed integrally at one time. Also, the p-type substrate 11
Although the p-type epitaxial layer 31 is formed on the p-type substrate 11, an n-type epitaxial layer may be formed on the p-type substrate 11. Also in this case, the n-type layer (first semiconductor layer) under the first well region 15a is formed thick and the n-type layer (third semiconductor layer) under the second well region 15b is formed thin. Is the same as in the above embodiment.

Further, although the p-type substrate 11 is used,
An n-type substrate may be used. In this case, carriers to be accumulated in the carrier pocket 25 are electrons out of electrons and holes. In order to obtain the same effect as in the above embodiment,
What is necessary is just to reverse all the conductivity types of each layer and each region described in the above embodiment and the like. The impurity concentration and thickness of the n-type buried layer (first buried layer) 32 are determined by the voltage applied between the impurity region 17 and the substrate 11 during the accumulation period.
The concentration and the thickness may be such that the depletion layer spreads from the interface between the n-type buried layer 32 and the entire surface of the n-type buried layer 32.

Further, a p-type buried layer (second buried layer) 33
The impurity concentration and the thickness of the n-type well layer mainly depend on the interface between the p-type buried layer 33 and the n-type well layer 12 by the voltage applied between the gate electrode 19 and the substrate 11 during the carrier sweeping period. It is sufficient that the concentration and the thickness are such that the depletion layer spreads toward 12 and the depletion layer does not spread much toward the p-type buried layer 33.

The order of the steps described in the embodiment of the method of manufacturing a solid-state imaging device is merely a typical example, and a device equivalent to a desired element structure obtained by the above-described manufacturing method can be obtained. Within the range, the order of the steps of the manufacturing method of the embodiment can be appropriately changed.

[0073]

As described above, according to the present invention, the light receiving diode and the MOS transistor for detecting an optical signal are adjacent to each other.
The thickness of the first semiconductor layer under the first well region (second semiconductor layer) of the light-receiving diode portion is equal to the thickness of the second well region (fourth semiconductor layer) of the optical signal detection MOS transistor portion. It is thicker than the lower third semiconductor layer.

In the light receiving diode portion, by increasing the thickness of the first semiconductor layer under the first well region, it is effective for light having a long wavelength such as red light during the carrier accumulation period. Accordingly, the thickness of the light receiving region can be increased, and therefore, the red sensitivity can be improved. On the other hand, in the optical signal detection MOS transistor portion, the third semiconductor layer below the second well region is thinned,
In addition, since the high-concentration second buried layer is formed adjacent to the third semiconductor layer on the substrate side, the voltage from the gate electrode is not so much in the second semiconductor layer during the carrier sweeping period. And mainly covers the second well region. This allows
Since a strong electric field is applied in the second well region, accumulated carriers can be effectively swept out from the high concentration buried layer (carrier pocket) and the second well region with a low reset voltage, and the reset efficiency is improved. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a plan view showing an element layout in a unit pixel of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2A is a cross-sectional view taken along the line AA of FIG. 1, showing a structure of a device in a unit pixel of the solid-state imaging device according to the embodiment of the present invention. (B) is a diagram showing a state of potential in a state where light generation holes are accumulated in a carrier pocket and electrons are induced in a channel region to generate an inversion region.

FIG. 3 is a cross-sectional view taken along the line BB of FIG. 1, showing a structure of a light-receiving diode in a unit pixel of the solid-state imaging device according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view taken along the line CC of FIG. 1, showing a structure of an optical signal detecting MOS transistor in a unit pixel of the solid-state imaging device according to the embodiment of the present invention;

FIG. 5 is a graph showing the impurity concentration distribution and the potential distribution in the depth direction along the line DD in FIG. 2 in the light receiving diode portion of the solid-state imaging device according to the embodiment of the present invention.

FIG. 6 shows an impurity concentration distribution and a potential distribution in a depth direction along a line EE in FIG. 2 including a carrier pocket in a MOS transistor portion for detecting an optical signal of the solid-state imaging device according to the embodiment of the present invention. It is a graph.

FIG. 7 is a graph showing drain current-voltage characteristics of an optical signal detection MOS transistor of the solid-state imaging device according to the embodiment of the present invention.

FIG. 8 is a diagram showing an overall circuit configuration of the solid-state imaging device according to the embodiment of the present invention.

FIG. 9 is a timing chart when the solid-state imaging device of FIG. 8 is operated.

FIGS. 10A and 10B are cross-sectional views (part 1) illustrating a method for manufacturing a solid-state imaging device according to an embodiment of the present invention.

FIGS. 11A and 11B are cross-sectional views (part 2) illustrating a method for manufacturing a solid-state imaging device according to an embodiment of the present invention.

FIGS. 12A and 12B are cross-sectional views (part 3) illustrating a method for manufacturing a solid-state imaging device according to an embodiment of the present invention;

FIGS. 13A and 13B are cross-sectional views (part 4) illustrating a method for manufacturing a solid-state imaging device according to an embodiment of the present invention;

FIGS. 14A and 14B are cross-sectional views (part 5) illustrating a method for manufacturing a solid-state imaging device according to an embodiment of the present invention;

FIGS. 15A and 15B are cross-sectional views (part 6) illustrating the method of manufacturing the solid-state imaging device according to the embodiment of the present invention;

FIGS. 16A and 16B are cross-sectional views (part 7) illustrating a method for manufacturing a solid-state imaging device according to an embodiment of the present invention;

17A and 17B are cross-sectional views (No. 8) illustrating the method of manufacturing the solid-state imaging device according to the embodiment of the present invention;

FIGS. 18A and 18B are cross-sectional views (No. 9) illustrating the method of manufacturing the solid-state imaging device according to the embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 11 substrate (first and second base layers, seventh semiconductor layer) 12 n-type well layer (first and third semiconductor layers, one conductivity type region) 15a first well region (second semiconductor layer) 15b 2nd well region (fourth semiconductor layer) 15c channel dope layer 16a source region 17 impurity region 17a drain region 18 gate insulating film 19 gate electrode 25 carrier pocket (high concentration buried layer) 31 epitaxial layer (seventh layer) 32) n-type buried layer (one conductivity type buried layer, first semiconductor layer, first buried layer, fifth semiconductor layer) 33 p-type buried layer (opposite conductivity type buried layer) 55 first mask 60 second mask 71 third mask 101 unit pixel 106 constant current source (load circuit) 107 image Signal output terminal 111 Light receiving Diode 112 optical signal detecting insulated gate field effect transistor (optical signal detection MOS transistor)

Claims (12)

[Claims] 1. A light-receiving diode formed in a second semiconductor layer of an opposite conductivity type in a first semiconductor layer of one conductivity type, and a fourth photodiode of an opposite conductivity type in a third semiconductor layer of one conductivity type. A solid-state imaging device comprising: an insulated gate field effect transistor for detecting an optical signal adjacent to the light receiving diode formed in the semiconductor layer of claim 1; A conductive type impurity region, wherein the insulated gate field effect transistor portion includes a source region and a drain region of one conductivity type in a surface layer of the fourth semiconductor layer, and a channel region between the source region and the drain region. A high concentration buried layer of the opposite conductivity type inside the fourth semiconductor layer near the source region below the channel region, and formed on the channel region via a gate insulating film Game played An electrode, wherein the impurity region is connected to the drain region, the first semiconductor layer is connected to the third semiconductor layer, and the second semiconductor layer is connected to the fourth semiconductor layer. And a portion of the first semiconductor layer below the second semiconductor layer is thicker in a depth direction than a portion of the third semiconductor layer below the fourth semiconductor layer. Solid-state imaging device. 2. The semiconductor device according to claim 1, wherein the first semiconductor layer has a first conductivity type opposite to the first conductivity type.
And the third semiconductor layer is formed on the first
2. The solid-state imaging device according to claim 1, wherein said solid-state imaging device is formed on a second base layer of the opposite conductivity type connected to said base layer. 3. The semiconductor device according to claim 1, wherein the first base layer is formed of a substrate of an opposite conductivity type semiconductor, and the first semiconductor layer includes a fifth semiconductor layer including a buried layer of one conductivity type, and the fifth semiconductor layer. The second base layer comprises a substrate of the opposite conductivity type semiconductor and a sixth semiconductor layer including a buried layer of the opposite conductivity type on the substrate. 3. The solid-state imaging device according to claim 2, wherein said third semiconductor layer is made of said one conductivity type well region. 4. The vicinity of the source region where the high-concentration buried layer is formed is a partial region in the channel length direction from the drain region to the source region, and is on the source region side. The solid-state imaging device according to claim 1. 5. The solid-state imaging device according to claim 1, wherein the high-concentration buried layer is formed over an entire region in a channel width direction. 6. The gate electrode of the insulated gate field effect transistor has a ring shape, the source region is formed on a surface of the fourth semiconductor layer surrounded by the gate electrode, and the drain region is The solid-state imaging device according to claim 1, wherein the solid-state imaging device is formed on a surface of the fourth semiconductor layer so as to surround a gate electrode. 7. The solid-state imaging device according to claim 1, wherein a gate electrode of the insulated gate field effect transistor and its periphery are shielded from light. 8. The solid-state imaging device according to claim 1, wherein a load circuit is connected to a source region of said insulated gate field effect transistor to form a source follower circuit. . 9. The solid-state imaging device according to claim 8, wherein a source output of said source follower circuit is connected to a video signal output terminal. 10. An impurity of one conductivity type is introduced into a seventh semiconductor layer of the opposite conductivity type by a first mask to form a first buried layer of one conductivity type inside the seventh semiconductor layer. And a step of introducing an impurity of the opposite conductivity type into the seventh semiconductor layer by the first mask to form a second impurity of the opposite conductivity type on the surface of the seventh semiconductor layer and above the first buried layer. Forming one well region; and introducing one conductivity type impurity into a surface layer of the seventh semiconductor layer so as to connect to the first buried layer so as to include the first well region. Forming a conductivity type region, introducing an opposite conductivity type impurity into the seventh semiconductor layer by a second mask, and forming the seventh conductivity type region under the one conductivity type region.
Forming a second buried layer of the opposite conductivity type having a higher impurity concentration than that of the semiconductor layer; and forming a second buried layer of the one conductivity type above the second buried layer by the second mask. An impurity of the opposite conductivity type is introduced into the surface layer, and the second impurity of the opposite conductivity type connected to the first well region.
Forming a well region of the second well region, introducing a one-conductivity-type impurity into the surface layer of the second well region by the second mask, and forming a one-conductivity-type channel dope layer; An impurity of the opposite conductivity type is introduced into the second well region, the impurity concentration is higher than that of the second well region, and an opposite conductivity type impurity is introduced into the second well region below the channel dope layer. Forming a high concentration buried layer; thermally oxidizing a semiconductor substrate surface to form a gate insulating film; and covering the high concentration buried layer so that the high concentration buried layer is on the source region side. Forming a gate electrode on the gate insulating film so as to be closer to the first well region; forming a source region and a drain region of one conductivity type in a surface layer of a second well region on both sides of the gate electrode; On the surface Method for manufacturing a solid-state imaging device characterized by a step of forming a net things region. 11. The gate electrode has a ring shape, the source region is formed in a surface layer of the second well region surrounded by the gate electrode, and the drain region is formed so as to surround the gate electrode. The method for manufacturing a solid-state imaging device according to claim 10, wherein the method is formed on a surface layer of the second well region. 12. A solid-state imaging device comprising the solid-state imaging device according to claim 1.