KR100788483B1 - Pixel structure of image sensor and manufacturing method - Google Patents

Abstract

According to an aspect of the present invention, in a transistor constituting an image sensor, a semiconductor substrate constituting the base of the transistor, a hole formed by being recessed in a predetermined portion of the semiconductor substrate, a gate formed in a predetermined portion of the lower surface of the hole An oxide layer, a gate formed on the gate oxide layer so that there is no step difference between the semiconductor substrate, a gate sidewall formed of an insulating material around the gate in the semiconductor substrate, and a source and a drain formed on both sides of the gate. The implanted low concentration of n− ions may include a high concentration of doped n + ions.

Image sensor, transistor

Description

Pixel structure of image sensor and manufacturing method thereof

1 is a unit pixel circuit diagram of a conventional 4-T (4-Transistor) structure.

2 is a diagram illustrating a manufacturing process of a transistor constituting a conventional image pixel.

3 is a cross-sectional view of a transistor constituting an image sensor according to an embodiment of the present invention;

4 is a view showing a manufacturing process of a transistor constituting the image sensor according to an embodiment of the present invention.

5 is a cross-sectional view of a transistor constituting an image sensor according to another embodiment of the present invention;

6 is a view showing a manufacturing process of a transistor constituting an image sensor according to another embodiment of the present invention.

FIG. 7 is a plan view illustrating a transistor constituting the image sensor shown in FIG. 6; FIG.

<Description of the symbols for the main parts of the drawings>

11,121: semiconductor substrate 12,122: insulating film

13,124: gate oxide film 14,126: gate

15: oxide film 16128: n-ion

18,129: n + ion 123: hole

125: sidewall 127: gate sidewall

The present invention relates to a semiconductor device constituting an image pixel, and more particularly, to a pixel structure of an image sensor and a method of manufacturing the same.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal and includes a charge coupling device and a CMOS. The charge coupled device (CCD) is a device in which charge carriers are stored and transported in a capacitor while individual metal-oxide-silicon (MOS) capacitors are located in close proximity to each other, and a MOS image sensor It adopts a switching method that uses a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to make as many MOS transistors as the number of pixels, and then sequentially detects the output using them. Device to be used.

These image sensors are mainly used in digital cameras, digital camcorders, mobile communication means and scanners, and their use is increasing rapidly. Image information used in image sensors can be called light information, which can be expressed by brightness and color. Do. In the image sensor, several pixels are arranged in a two-dimensional structure, and each pixel converts it into an electrical signal according to the brightness of light entering the pixel. When the electrical signal is measured, the amount of light entering each pixel is known. This can be used to construct an image in units of pixels. These image sensors consist of a pixel array of hundreds of thousands to millions of pixels, a device that converts analog data sensed by pixels into digital data, and hundreds to thousands of storage devices.

In general, a CMOS image sensor having a 4TR structure is composed of four transistors and two capacitance structures, and is composed of a photodiode (PD) as a light sensing means and four NMOSFETs. Of the four NMOSFETs, the transfer transistor Tx is responsible for transporting the photocharges generated by the photodiode PD to the floating diffusion node FD, and the reset transistor Rx is the floating diffusion node FD for signal detection. The drive transistor Dx serves as a source follower, and the select transistor Sx is a device for switching and addressing. The other transistor LD is a load transistor driven by a bias voltage V b.

1 is a diagram illustrating a unit pixel circuit diagram of a conventional 4-T (4-Transistor) structure.

Referring to FIG. 1, a unit pixel includes one photo diode (PD) and four NMOS transistors that convert light into electrons. The four NMOS transistors include a reset transistor Rx for resetting the potential of the photodiode in response to the reset gate signal, a transfer transistor Tx for passing electrons charged in the photodiode to the floating diffusion region in response to the transfer signal, and floating. The drive transistor Dx changes the output voltage of the unit pixel by changing the current of the source follower circuit according to the change of the electrode voltage of the diffusion region, and the unit pixel generated according to the voltage change of the floating certain region corresponding to the selection gate signal. It consists of a select transistor Sx which outputs an output voltage analogously.

More specifically, the gate of the transfer transistor Tx is formed while overlapping a predetermined width in an active region in which the photodiode PD is to be formed on one side thereof, and the floating diffusion node FD in the active region under the other side of the gate of the transfer transistor Tx. ) Is formed. Here, the photodiode PD has a relatively large area, and the area of the photodiode PD becomes narrow while giving a bottle neck effect from the photodiode PD to the floating diffusion node FD. The active region in which the reset transistor Rx, the drive transistor Dx, and the select transistor Sx are formed extends in a clockwise direction around the floating diffusion node FD. Here, the gates of the transistors are arranged while crossing the upper portion of the active region at predetermined intervals. The above pixel has five contacts M1CT, which are 'Tx CT' for applying the control signal Tx to the gate of the transfer transistor Tx, and connecting the gate of the floating diffusion node FD and the drive transistor Dx. There are 'FD CT' and 'Dx CT' for this, 'VDD CT' for supplying power voltage, and 'output CT' for pixel output stage.

2 is a view illustrating a manufacturing process of a transistor constituting a conventional image pixel.

Generally, the optical receiver of the sensor is formed as a gate of a large area transistor. The optical receiver is often referred to as a source-drain connection of a photo-gate or metal oxide semiconductor transistor. The process of forming a photo-gate transistor requires that light pass through the transistor's silicon gate to convert light into electrical energy. As a result, the formation process of the photo-gate transistor reduced the sensitivity. In addition, the depletion region is generally thin (less than 1 micron), which reduces the collection effect introduced by red light absorption. The formation process of conventional photo-gate transistors is sensitive to noise produced by surface recombination.

The source-drain connection has a connection suitable for the operation of the transistor. It has a thin connection that ineffectively collects carriers introduced by red light. A disadvantage of forming source-drain junctions is that the junctions are formed in densely doped regions (greater than 10 ¹⁶ atoms / cm 3) that limit the width of the junction depletion region. Thus, the collection effect of carriers introduced by the red light absorption is reduced. In addition, forming connections in these densely doped regions results in large capacitances that reduce the amount of charge transferred from the photosensitive device to other electronic devices.

Referring to FIG. 2, as shown in FIG. 2A, a nitride film is deposited on the semiconductor substrate 11 to form an insulating film 12, and the nitride film of a region to form a trench is removed. Next, a trench is formed in the semiconductor substrate 11 to a depth corresponding to the depth of n-ion 16 using the nitride film as a mask, and impurities (not shown) are formed in the semiconductor substrate 11 under the trench to prevent short channel phenomenon. Inject. Next, as shown in FIG. 2B, an oxide process is performed to oxidize the semiconductor substrate 11 in the trench to form a gate oxide film 13, and thick polysilicon is deposited on the entire surface of the trench and the insulating film 12, whereby the nitride film is exposed. It is etched back to a degree to form a gate 14 made of polysilicon. As shown in FIG. 2C, the low concentration n-type source and drain regions 16 are formed by implanting and doping n-ions 16 into the semiconductor substrate 11. Subsequently, the insulating film 12 is removed and an oxidation process is performed to oxidize the exposed portion of the polysilicon and the semiconductor substrate 11 to form the oxide film 15. As shown in FIG. 2D, the entirety of the gate 14 and the semiconductor substrate 11 are oxidized to form the oxide film 15, and then the oxide film 15 is etched by anisotropic etching. At this time, since a thicker oxide film 15 is formed around the polysilicon due to the difference in oxidation rate, the oxide film 15 remains only around the polysilicon gate 14 after etching. As shown in FIG. 2E, an n + type epitaxial layer is grown by an epitaxial process to form a high concentration of source and drain regions 18.

The capacitor having the largest capacitance in the floating diffusion node FD is a capacitor generated by the transistor of the source follower connected to the floating diffusion node FD. Basically, the transistor using the LDD structure has a large capacitance between the gate 14 and the drain, and the gate 14 and the source. The amount of charge transferred from the source to the drain has a problem in that convergence gain is inevitably reduced due to the large capacitance formed in the drain portion.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel structure of an image sensor, and to fabricating a pixel structure of an image sensor for maximizing conversion gain of charge by minimizing a capacitor of a transistor electrically connected to a floating diffusion node (FD) region. It is an object to provide a method.

In order to achieve the above object, according to an aspect of the present invention, in the manufacturing process of the transistor constituting the image sensor, forming a gate on a semiconductor substrate; Forming a sidewall formed of an insulating material around the gate; And doping low concentrations of n- ions and high concentrations of n + ions in the lower portion of the semiconductor substrate, wherein the low concentrations of n- ions doped in the lower portion of the semiconductor substrate are each at different angles to include high concentrations of n + ions. And a transistor manufacturing process comprising implanted.
According to another aspect of the invention, in the manufacturing process of the transistor constituting the image sensor, after depositing a nitride film on a semiconductor substrate, a portion of the nitride film is patterned to expose the semiconductor substrate to form a nitride film mask, the nitride film mask Etching the semiconductor substrate to form holes; Forming sidewalls on sidewalls of the holes; Etching the semiconductor substrate to a predetermined depth and forming an ion layer under the semiconductor substrate; Forming a gate oxide layer on a surface of the hole and forming a gate on the hole; Removing the sidewall and forming a gate sidewall formed of an insulating film; And doping low concentrations of n- ions and high concentrations of n + ions in the lower portion of the semiconductor substrate.
Here, the step of doping the low concentration of n- ions and high concentration of n + ions in the lower portion of the semiconductor substrate, by repeatedly implanting a low concentration of n- ions and a high concentration of n + ions in the lower portion of the semiconductor substrate n times Ions can be implanted deeply below the semiconductor substrate.
In addition, a low concentration of n − ions and a high concentration of n + ions may be repeatedly injected four times in a lower portion of the semiconductor substrate.
In addition, the step of doping low concentration n- ions and high concentration n + ions in the lower portion of the semiconductor substrate, by injecting the low concentration n- ions and high concentration n + ions in the lower portion of the semiconductor substrate through different angles And reduce the capacitance between the source or the gate and the drain, or the low concentration of n- ions can be achieved by implanting at a higher energy than the high concentration of n + ions.
According to still another aspect of the present invention, there is provided a manufacturing method of a transistor constituting an image sensor, the method comprising: forming a gate on a semiconductor substrate; Forming a sidewall formed of an insulating material around the gate; And doping a low concentration of n- ions and a high concentration of n + ions in the lower portion of the semiconductor substrate. The low concentration of n- ions doped in the lower portion of the semiconductor substrate is implanted with a greater energy than the high concentration of n + ions. To provide a transistor manufacturing process.
According to another aspect of the invention, a transistor constituting the image sensor, comprising: a semiconductor substrate constituting the base of the transistor; A gate formed on the semiconductor substrate such that there is no step with the semiconductor substrate; A gate sidewall formed of an insulating material around the gate; And a source and a drain formed at both sides of the gate, wherein the low concentration of n− ions implanted into the source and drain is implanted at different angles to contain a high concentration of doped n + ions. Can be provided.
According to another aspect of the invention, a transistor constituting the image sensor, comprising: a semiconductor substrate constituting the base of the transistor; Holes formed in the semiconductor substrate by recessed portions; A gate oxide film formed on a predetermined portion of the lower surface of the hole; A gate formed on the gate oxide layer such that there is no step with the semiconductor substrate; A gate sidewall formed of an insulating material around the gate in the semiconductor substrate; And a source and a drain formed on both sides of the gate, wherein a low concentration of n− ions injected into the source and drain includes a high concentration of doped n + ions.
The transistor may be a drive transistor Dx connected to a floating diffusion node FD.
According to another aspect of the invention, a transistor constituting the image sensor, comprising: a semiconductor substrate constituting the base of the transistor; A gate formed on the semiconductor substrate such that there is no step with the semiconductor substrate; A gate sidewall formed of an insulating material around the gate; And a source and a drain formed at both sides of the gate, wherein the low concentration of n− ions implanted into the source and drain is implanted with greater energy than a high concentration of n + ions. Can provide.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments presented below, and the same scope of the invention will be presented by the addition, limitation, deletion, addition, etc. of components within the scope obvious to those skilled in the art. Could be.

Hereinafter, a semiconductor substrate is etched to form holes based on FIGS. 3 to 4, and a manufacturing process and a configuration of a transistor in which a gate is formed in the hole is described. The gate is formed on a flat semiconductor substrate based on FIGS. 5 to 6. The manufacturing process and configuration of the transistor to be formed will be described.

3 is a cross-sectional view of a transistor constituting an image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a p-type substrate, which is a single crystal silicon wafer serving as a support for the entire circuit, a heavily doped n + ion 129 region, a lightly doped n− ion 128 region, and a substrate A thin (0.02-0.1 μm ² ) silicon dioxide (SiO ₂ ) layer with good electrical insulating properties is grown on the surface, and the layer covers the area between the source and drain regions. Metal is deposited on the oxide layer to form a gate electrode 126 of the device. An outer sidewall of the gate 126 is surrounded by an oxide film.

The heavily doped n + ion 129 region is formed to be contained in the lightly doped n− ion 128 region, thereby greatly reducing the capacitance between the gate 126 and the drain, the gate 126, and the source. Will be reduced. This will be described in detail below.

The image sensor includes a lower p-type substrate formed by the semiconductor substrate 121 and an enhancement layer (not shown) formed thereon. A well is formed in a portion of the lower substrate of the image sensor. The surface doping concentration of the wells is at least 1 × 10 ¹⁶ atoms / cm ³ . In general, to form other CMOS devices in the p-type substrate, the depth of the well is generally formed thinner than the depth of the enhancement layer. The depth of the enhancement layer is on the order of about 2-4 microns.

The light sensing device or the image capturing device of the image sensor includes an n-type conductive region. The n-type conductive region forms a p-type lower substrate and a p-n connection portion. The p-n junction is formed about 0.5 microns from the surface of the substrate to easily detect light in the red wavelengths. The n-type conductive region includes a portion lightly doped with n− ions 128 and a portion heavily doped with n + ions 129, and fabrication of the n + ions 129 and n− ions 128 region. Depending on the process, the capacitance between the gate 126 and the drain, the gate 126 and the source is changed.

The transfer transistor Tx, i.e., the CMOS transistor, is formed in the vicinity of the n-type conductive region. Therefore, one portion of the n-type conduction region forms the source of the transistor. The n-type conductive region is formed through a mask operation. The mask includes a portion of the gate 126 of the transistor and has a hole that exposes a portion of the surface of the portion leading to the gate 126 of the transistor.

Since the transistor of the LDD structure implants LDD n- ions 128 before sidewall formation, the capacitance between the gate 126-the drain or the gate 126-the source becomes large. In order to solve this problem, in the step of implanting n + ions 129 after the sidewall formation, the n-ions 128 are deeply injected below the gate 126 or the n- ions are continuously injected four times. If the implant angle of (128) is relatively large, and the n + ions 129 are implanted according to the existing conditions, the gate 126 and the drain, the gate 126 and the source are maintained while maintaining the physical characteristics of the transistor manufactured by the conventional process. Overlap capacitance of the liver can be greatly reduced. Therefore, the total capacitor of the floating diffusion node (FD) region is also greatly reduced. As the total capacitor of the floating diffusion node (FD) region decreases, the conversion gain can be greatly increased.

In particular, in order to minimize capacitance generated in the drive transistor Dx connected to the floating diffusion node FD, the drive transistor Dx implants n + ions 129 instead of adopting a transistor manufacturing process having a typical LDD structure. In this step, n + ions 129 and n− ions 128 are implanted into the semiconductor substrate 121 to reduce the capacitance between the gate 126, the drain gate 126, and the source. In the case of implanting ions having a low concentration in the n + ion 129 and n- ion 128 implantation steps, the implantation is performed by increasing the energy or increasing the tilt angle than the implantation of ions having a high concentration. In this case, the overlap with the gate 126 is minimized under low concentration.

4 is a view illustrating a manufacturing process of a transistor constituting an image sensor according to an embodiment of the present invention.

Referring to FIG. 4, after forming the insulating film 122 by depositing a nitride film on the semiconductor substrate 121 as shown in FIG. 4A, an LDD length is longer than that of the gate 126 region to form a gate 126 pattern. A wide area photoresist pattern is formed on the insulating film 122, and the insulating film 122 under the pattern is etched to expose the semiconductor substrate 121 using the pattern as a mask to form an insulating film mask. Therefore, the semiconductor substrate 121 is exposed to the outside of the predetermined gate 126 region and the region of the gate 126 region combined by twice the LDD length. Since the gate pattern is formed to be longer than the actual length (2 × LDD length), the gate 126 manufactured after the completion of the process may be formed to a size much smaller than the limit of the photo process. After removing the photoresist, the exposed portion of the semiconductor substrate 121 is etched to a predetermined depth using an insulating film mask to form a hole 123. The hole 123 is formed by etching the semiconductor substrate 121 on the exposed portion by the junction depth of the substrate and the n− ions 128 / n + ions 129, and the etching depth is about 0.1 μm.

Next, an oxide film is deposited on the semiconductor substrate 121 including the surface of the hole 123 by CVD and then etched back to increase the sidewall 125 higher than the insulating layer 122 along the sidewall of the hole 123. ). Therefore, only a portion of the semiconductor substrate 121 where the gate 126 in the center of the hole 123 is formed is exposed by the side wall 125.

Subsequently, the sidewall 125 is used to recess-etch the bottom of the hole 123 of the semiconductor substrate 121 to a depth of about 0.1 μm to form a new hole 123. If the hole 123 is formed to have a width of the etching limit of the device, the new hole 123 formed by recess etching the bottom of the hole 123 of the semiconductor substrate 121 using the sidewall 125 is formed. It may have a width less than the etching limit of.

Then, ion implantation is performed to form a punch-through stop ion layer to form an ion layer (not shown) in the region where the gate 126 is to be formed, that is, under the hole 123 of the semiconductor substrate 121. . At this time, since the ion implantation for punch-through stop is performed only in the channel region, the parasitic capacitance (n + / p) does not occur below the n + ion (129). Next, a gate oxide film 124 is formed on the surface of the hole 123 and the side wall 125 through an oxidation process.

4B, the gate 126 is formed higher than the surface of the semiconductor substrate 121 by filling polysilicon in the hole 123. In this case, since the gate 126 is formed in the recess etched hole 123 having a width less than the etching limit of the equipment, the length of the gate 126 may have a width less than the etching limit of the equipment.

As shown in FIG. 4C, the nitride layer 122 and the oxide sidewall 125 on the substrate are sequentially removed by wet etching. In this case, a groove is formed in a portion where the oxide side wall 125 is removed.

The next step is to form a gate sidewall 127 structure with an oxide film in the groove. Although the gate sidewall 127 is formed after the n-ion 128 is implanted, capacitance between the gate 126 and the drain, the gate 126, and the source is increased. By forming first, the total capacitance can be minimized.

The next step is to implant a low concentration of n-type impurities into the semiconductor substrate 121 to form a low concentration source and drain region 128 in the n-ion 128 region forming an LDD structure on the bottom of the groove. Finally, n + ions 129 are implanted to form a high concentration source and drain region 129.

The present invention can reduce the junction capacitance by changing the fabrication process of the transistor. That is, the operation speed of the device can be improved by reducing the parasitic capacitance under the semiconductor substrate 121 doped with n ions through the manufacturing process of the transistor according to the spirit of the present invention.

5 is a cross-sectional view of a transistor constituting an image sensor according to another exemplary embodiment of the present invention.

Referring to FIG. 5, a p-type substrate, which is a single crystal silicon wafer that is the basis of the entire circuit, a highly doped n + ion 129 region, a lightly doped n− ion 128 region, and a surface of the substrate A thin (0.02 to 0.1 µm) ² silicon dioxide (SiO ₂ ) layer with good electrical insulating properties is grown on the top. A gate electrode 126 element is formed on the oxide layer, and an outer surface of the gate 126 element is surrounded by a gate sidewall 127 as an oxide film.

The heavily doped n + ion 129 region is formed to be included in the lightly doped n− ion 128 region, thereby greatly reducing the capacitance between the gate 126 and the drain, the gate 126, and the source. Will be reduced.

The light sensing device or the image capturing device of the image sensor includes an n-type conductive region. The n-type conductive region forms a p-type lower substrate and a p-n connection portion. The p-n junction is formed about 0.5 microns from the surface of the substrate to easily detect light within the red wavelengths.

The n-type conductive region includes a portion lightly doped with n− ions 128 and a portion heavily doped with n + ions 129, and fabrication of the n + ions 129 and n− ions 128 region. Depending on the process, the capacitance between the gate 126 and the drain, the gate 126 and the source is changed.

One side of the n-type conductive region forms a source of a transistor, and the other side forms a drain. The transistor of the LDD structure implants LDD n- ions 128 into the semiconductor substrate 121 before the gate sidewall 127 is formed, so that the capacitance between the gate 126-the drain or the gate 126-the source is increased. Is bound to grow. In order to solve this problem, the present invention rotates the n− ions 128 below the gate 126 while performing four consecutive rotations in the step of implanting n + ions 129 after the gate sidewall 127 is formed. If the implantation is deeply implanted or the implantation angle of the n− ion 128 is relatively large, and the n + ion 129 is implanted according to the existing conditions, the gate 126 and the gate 126 may be maintained while maintaining the physical characteristics of the transistor manufactured through the conventional process. Overlap capacitance between the drain, gate 126 and the source can be greatly reduced. Therefore, the total capacitor of the floating diffusion node (FD) region is also greatly reduced. As the total capacitor of the floating diffusion node (FD) region decreases, the conversion gain can be greatly increased.

In particular, in order to minimize capacitance generated in the drive transistor Dx connected to the floating diffusion node FD, the drive transistor Dx implants n + ions 129 instead of adopting a transistor manufacturing process having a typical LDD structure. In this step, n + ions 129 and n− ions 128 are implanted into the semiconductor substrate 121 to reduce the capacitance between the gate 126, the drain gate 126, and the source.

In the case of implanting ions having a low concentration in the n + ion 129 and n- ion 128 implantation steps, the implantation is performed by increasing the energy or increasing the tilt angle than the implantation of ions having a high concentration. In this case, the overlap with the gate 126 is minimized under low concentration. The n + ions 129 are formed to be included in the n− ions 128, and the n− ions 128 include the n + ions 129 not only in depth but also in width.

 6 is a view illustrating a manufacturing process of a transistor constituting an image sensor according to another exemplary embodiment of the present invention.

Referring to FIG. 6, the gate 126 is formed on the semiconductor substrate 121 without etching the semiconductor substrate 121 as shown in FIG. 6A. Next, as shown in FIG. 6B, gate sidewalls 127 are formed on sidewalls of the gate 126 formed on the semiconductor substrate 121. Subsequently, a high concentration of n + ions 129 and a low concentration of n− ions 128 are implanted into the bottom of the gate sidewall 127 as shown in FIG. 6C. As a result, an ion layer is formed under the gate 126 of the semiconductor substrate 121. Although the gate sidewall 127 is formed after the n-ion 128 is implanted, capacitance between the gate 126 and the drain, the gate 126, and the source is increased. The total capacitance can be minimized by first forming and implanting n + ions 129 and n− ions 128.

That is, n-type impurities are implanted at low concentration into the semiconductor substrate 121 to form a low concentration source and drain region 128 in the n-ion 128 region forming an LDD structure on the bottom of the groove. Finally, n + ions 129 are implanted to form a high concentration source and drain region 129.

FIG. 7 is a plan view illustrating a transistor constituting the image sensor shown in FIG. 6.

Referring to FIG. 7, a heavily doped n + ion 129 region and a lightly doped n− ion 128 region are formed on a p-type substrate which is a single crystal silicon wafer. The n + ions 129 are formed to be included in the n− ion 128 not only in depth but also in width, wherein the n− ions 128 coincide with an active region under the substrate. . A gate electrode 126 element is formed on the active region, and an outer surface of the gate 126 element is surrounded by a gate sidewall, which is an oxide film.

The lightly doped n− ion 128 region may have a deeper implantation depth than the heavily doped n + ion region 129, and may have a deeper junction depth, as shown in FIG. 7. do.

The present invention can reduce the junction capacitance by changing the fabrication process of the transistor. That is, the operation speed of the device can be improved by reducing the parasitic capacitance under the semiconductor substrate 121 doped with n ions through the manufacturing process of the transistor according to the spirit of the present invention.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel structure of an image sensor, and to fabricating a pixel structure of an image sensor for maximizing conversion gain of charge by minimizing a capacitor of a transistor electrically connected to a floating diffusion node (FD) region. It has the effect of providing a method.

Claims (10)

In the manufacturing process of the transistor constituting the image sensor, Forming a gate on the semiconductor substrate; Forming a sidewall formed of an insulating material around the gate; And Doping low concentrations of n- ions and high concentrations of n + ions into the lower portion of the semiconductor substrate—low concentrations of n- ions doped into the lower portion of the semiconductor substrate are implanted at different angles to include high concentrations of doped n + ions being- Transistor manufacturing process comprising a. In the manufacturing process of the transistor constituting the image sensor, Depositing a nitride film on a semiconductor substrate, patterning a portion of the nitride film to expose the semiconductor substrate to form a nitride mask, and etching the semiconductor substrate using the nitride mask to form holes; Forming sidewalls on sidewalls of the holes; Etching the semiconductor substrate to a predetermined depth and forming an ion layer under the semiconductor substrate; Forming a gate oxide layer on a surface of the hole and forming a gate on the hole; Removing the sidewall and forming a gate sidewall formed of an insulating film; And Doping a low concentration of n- ions and a high concentration of n + ions into the lower portion of the semiconductor substrate Transistor manufacturing process comprising a. The method according to claim 1 or 2, Doping low concentration n- ions and high concentration n + ions into the lower portion of the semiconductor substrate may include repeating injection of low concentration n- ions and high concentration n + ions into the lower portion of the semiconductor substrate a plurality of times in succession. Transistor manufacturing process, characterized in that deeply injected into the lower portion of the semiconductor substrate. The method of claim 3, wherein And sequentially injecting low concentrations of n- ions and high concentrations of n + ions into the semiconductor substrate four times in succession. The method of claim 2, Doping a low concentration of n- ions and a high concentration of n + ions into the lower portion of the semiconductor substrate may include injecting the low concentration of n- ions and high concentration of n + ions into the lower portion of the semiconductor substrate through different angles. Or reducing the capacitance between the gate and the drain, or by injecting a low concentration of n− ions to a greater energy than the high concentration of n + ions. In the manufacturing process of the transistor constituting the image sensor, Forming a gate on the semiconductor substrate; Forming a sidewall formed of an insulating material around the gate; And Doping a low concentration of n- ions and a high concentration of n + ions in the lower portion of the semiconductor substrate-the low concentration of n- ions doped in the lower portion of the semiconductor substrate is implanted with a greater energy than the high concentration of n + ions - Transistor manufacturing process comprising a. In the transistor constituting the image sensor, A semiconductor substrate constituting the base of the transistor; A gate formed on the semiconductor substrate; A gate sidewall formed of an insulating material around the gate; And Sources and drains formed on both sides of the gate, wherein low concentrations of n- ions implanted into the source and drain are implanted at different angles to contain highly doped n + ions. Transistor comprising a. In the transistor constituting the image sensor, A semiconductor substrate constituting the base of the transistor; Holes formed in the semiconductor substrate by recessed portions; A gate oxide film formed on a predetermined portion of the lower surface of the hole; A gate formed on the gate oxide layer; A gate sidewall formed of an insulating material around the gate in the semiconductor substrate; And Source and drain formed on both sides of the gate, wherein the low concentration of n− ions implanted into the source and drain comprises a high concentration of doped n + ions; Transistor comprising a. The method according to claim 7 or 8, And the transistor is a drive transistor (Dx) connected to a floating diffusion node (FD). In the transistor constituting the image sensor, A semiconductor substrate constituting the base of the transistor; A gate formed on the semiconductor substrate; A gate sidewall formed of an insulating material around the gate; And Source and drain formed on both sides of the gate, wherein the low concentration of n− ions implanted into the source and drain is implanted with greater energy than the high concentration of n + ions; Transistor comprising a.

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