JP2003506926A - Multi photo detector unit cell - Google Patents

Abstract

(57) Abstract: A multi-cell cluster (12) including a plurality of photodetection unit cells (14) and one charge storage and readout circuit (27). Each cell typically produces a charge corresponding to the detected light. This circuit can be shared by a plurality of unit cells, and is used to read charges in real time. The cluster (12) includes switches corresponding to each unit cell, and each switch connects the corresponding unit cell to a circuit. The switches can also be controlled in a time division multiplexed manner. Each unit may include a photodetector (22), a photodiode, or a photogate. The circuit may include a shared storage device, a shared reset circuit, or a read circuit (27). Typically, a shared storage device can be used to store charge at the focal plane. By using the apparatus described above, it is possible to easily trade off the resolution and sensitivity of a static or dynamic or partial or total image.

Description

Detailed Description of the Invention

FIELD OF THE INVENTION The present invention relates to a cell array structure of an image sensor, and more particularly to a multi-photodetector unit cell and its control method.

BACKGROUND conventional image sensor of the present invention, a photodiode alone or active device transistor elements and combinations thereof, or a charge coupled device (CCD) technology have been used. Over the past three decades, CCD has been the dominant image sensor technology.

CCDs have many advantages, including small pixel size, high sensitivity, and the ability to produce high-fidelity images. At the same time, it is disadvantageous in that a special manufacturing process is required, power consumption is high, another function such as processing cannot be incorporated on the same chip, and a control circuit is complicated. There are also points. Furthermore, CCDs are manufactured by only a few manufacturers and are difficult to access due to their dedicated housing.

One of the competing technologies is active pixel sensor (APS) technology based on complementary metal oxide semiconductor (CMOS) manufacturing technology. This APS technology has advantages such as low output, a sensor and a control circuit can be incorporated on the same chip, and a larger sensor array can be formed. The great advantage achieved by the APS structure is that the pixels can be sized comparable to the pixels of a CCD and the S / N ratio is large. APS unit cells contain several active device transistors, thus making the pixel small is difficult. In order to increase the S / N ratio, it is necessary to collect as many photon-generated electrons as possible in the storage capacitor. This requires long-term storage for weak photocurrents and large capacitance capacitors occupying pixel space.

Various studies have been conducted to reduce the size of APS pixels and to improve the fill factor and quantum efficiency. An example of this is D. Scheffer et al., "Random
addressable 2048 X 2048 active pixel image sensor, "IEEE Trans. Elec. D
ev. Vol. 44, no. 10, October 1997, pp. 1716-1720, and in Y. Iida et al., "A 1
/ 4-inch 330k square pixel progressive scan CMOS active pixel image senso
r, "IEEE JSSC, Vol. 32, no. 11, November 1997, pp. 2042-2047.

A list of alternative non-standard techniques and alternative standard techniques to achieve the above improvements is provided below.

Non-standard technology Since the standard technology could not cope with a special new application, the non-standard technology was devoted to the development of the non-standard technology. Studies of amorphous silicon photoconductors, photodiodes, or phototransistors have improved the fill factor by reducing the unit cell size by reducing the vertical dimension of the photodetector on top of the active read circuit. The quantum efficiency approaches 100%, and the dark current can be made lower than that of the single crystal material. However, amorphous silicon photodetectors have a drawback of high fixed pattern noise (FPN) due to charge trapping and special structure of the material. In the case of the backlight illumination photodetector technology, in both CCD and APS systems, the sampling unit and the reading unit are located on the front surface, and the photodetector occupies the back surface of the image sensor. The image sensor is illuminated from the back. Therefore, it is possible to bring the fill factor and the quantum efficiency close to 100%.

However, in order to manufacture a backside illuminated photodetector, a process called wafer thinning is required, which process is complicated and expensive. Therefore, the back-illuminated image sensor is limited to a special scientific field, an aerospace field, or the like without consideration of cost. In addition, the wafer thinning process causes significant crystal defects near the surface of the wafer, and recombination of the surfaces causes considerable noise. MOS type phototransistor (Charge modulation de
The structure of the vices (CMD) technology is extremely simple. Due to the simple structure (only one transistor), it is possible to make the pixel very small.
This makes it possible to realize a huge format arrangement. However, since the CMD image sensor has low sensitivity to short wavelengths of light, a special manufacturing process is required.

Standard CMOS Process Various studies have been conducted to implement a high performance image sensor using a standard CMOS manufacturing process. This research is extremely important in that it can reduce the manufacturing cost of an on-chip camera by using an easily available technology. High performance AP
In order to manufacture the S image sensor, the following points are necessary.

In a passive photodiode detector image sensor, a photodiode is used as a detection element. 1 pixel element for passive photodiode system
Research was conducted in the 960s. These pixels are quite simple with one diode and one transistor. This passive pixel structure allowed the highest fill factor for a given pixel size, ie the smallest pixel size for a given fill factor.

However, this method has the disadvantage that the read noise is relatively high. Also, in the array of image sensors, the full column capacitance is sent directly from the passive unit cells. Since this capacitance is directly proportional to the number of pixels in a column, the read speed is limited, which significantly increases the read noise.
Therefore, the passive pixel method is not suitable for the structure of an image sensor having a large format array.

In the active pixel photodiode type image sensor, the photodiode type APS image sensor is characterized by having high quantum efficiency for red, green and blue wavelength photons. The name "active pixel sensor" comes from the fact that each unit cell contains at least one active transistor. This transistor performs an amplifying or buffering function.

There are various types of active circuits. A simple active circuit contains up to three transistors in a unit cell. The fill factor of the APS photodetector is limited by the size of the fixed unit cell. In other words, the maximum unit cell size is limited by the fixed fill factor. The main goal is to simplify the entire unit cell to achieve high resolution, high fill factor, and high quantum efficiency.

It should be noted that reducing the pixel size reduces the column capacitance, which reduces read noise and improves read speed.
Structure with the minimum number of transistors and extremely small pixel size (
5.6 × 5.6 μm) was achieved, but the fill factor was extremely small (15
． 8%).

The purpose of the active pixel photogate type image sensor is to provide a circuit that combines detection and charge storage functions. The front side illumination transistor collects charge in proportion to the light intensity under the photogate. The charge collected and stored under the photogate is sent to the floating diffusion node during reading. This floating diffusion node is connected to the input of the source follower circuit. This source follower protects the floating diffusion from the columns of the array that have high capacitance.

In general, the structure of a photogate pixel includes five transistors including a photogate detection / charge storage device. Various studies have been carried out to improve the photogate-type structure, since the small readout noise and the absence of image delay in the photogate structure are important advantages. This work resulted in the development of relatively small pixels (10 × 10 μm) using 0.5 μm CMOS fabrication technology. However, this method has low quantum efficiency for blue wavelength photons, since blue wavelength photons are absorbed by the polysilicon plated photogate.

In order to solve this problem, various technologies have been applied to develop an APS sensor that combines a structure of a photogate and a photodiode. This structure used a photogate section to collect blue and green wavelength photons and a photodiode section to collect blue wavelength photons.

Variable Resolution Function The ability to change the resolution of the image sensor is defined as the variable resolution function. By applying the variable resolution feature, it is possible to trade off high resolution for improved video frame rate or image processing. More importantly, the variable resolution feature allows a trade-off between resolution and S / N ratio. This is especially important when the electrical signal, which is proportional to the light intensity, is extremely weak. This increases noise and reduces image quality. However, there are cases where an image with low noise and low noise is preferable.

"CMOS Active Pixel Sensor Array with Programmable Mul by S. Kemeny et al.
tiresolution Readout "(JPL, California Institute of Technology, Pasadena
CA 91109 USA, 1994) and R. Paniacci et al., "Programmable multiresoluti.
One method described in "on CMOS active-pixel sensor" (SPIE Vol. 2654) is used to trade off resolution and speed. This method is based on pixel singal block averaging. This method is complicated and a high S / N ratio cannot be obtained.

"Frame-Transfer CMOS Active Pixel Sensor with Pixel" by Zhimin Zhou et al.
Binning "(IEEE Trans. Elec. Dev., Vol. 44, No. 16, Oct. 1997, pp. 1764-
The second method described in 1768) is capable of adding the charges accumulated in a plurality of pixels. The accumulated charge addition first samples the charge accumulated in the memory cell during charge accumulation and then adds the charges sent to the vertical and horizontal charge accumulation amplifiers (CIAs). To be achieved.

Since the charge addition is linear, but the noise addition is the square root of the noise energy, the S / N ratio can be improved by the pixel charge addition.

[0022] SUMMARY An object of the present invention, the combination of sensitivity and S / N ratio is substantially optimal, and to provide a relatively high fill factor CMOS image sensor structure. In accordance with one embodiment of the present invention, there is provided a multi-cell cluster that can include multiple photo-detecting unit cells and circuits. Normally, each cell produces a charge corresponding to the detected light. The circuit can be shared by multiple unit cells and is used to read the charge in real time.

The cluster may also include a switch for each unit cell that connects the corresponding unit cell to the circuit. The switches can also be controlled in a time division multiplexed manner. Each unit cell can include either a photodetector, a photodiode, or a photogate. This circuit may include a shared storage device, a shared reset circuit, or a read circuit. Generally, a shared storage device can be used to store the charge in the focal plane.

In accordance with one embodiment of the present invention, a detection array is provided that includes multiple clusters, sampling lines, and detection lines. A cluster may include multiple unit cells and circuits. The unit cell can detect light and generate a charge corresponding to the light. The circuit can be shared by the unit cells and can control the operation of the unit cells. The circuit may also store charge. Each sampling line may be connected to a row of clusters to sample the accumulated charge in the row. Each detection line can be connected to a column of clusters to detect the sampled charge in the column. The sampling line and detection line may also carry programming signals to control the plurality of unit cells.

According to an embodiment of the present invention, a method of operating an image sensor is provided. The method includes the steps of accumulating charge in one or more unit cells of the cluster, and adding the charge at the focal plane of at least one unit cell between the accumulating charges. The method may also include the step of reading the added charge. The one or more unit cells may be pre-programmed unit cells and the reading step may include reading the added charge in real time.

The step of accumulating may include the step of accumulating charges in a time division multiplex manner or the step of accumulating charges of each unit cell separately. Alternatively, this step of accumulating may include accumulating charges of two or more unit cells simultaneously, or accumulating charges of all unit cells of the cluster simultaneously. The method may also include the step of combining the readouts into an image.

The method may include dynamically controlling the selection of the number of unit cells in the step of storing charge. This dynamically controlling step may include selecting the number of unit cells according to light conditions. All steps can be performed in real time.

The method may also include increasing the number of unit cells in the step of accumulating charges to improve the S / N ratio of the image sensor. This is because the amount of added charge increases linearly, while the increase in noise is a little gradual as a function of the square root, so the number of unit cells can be increased to improve the S / N ratio. . The method may also include the step of reading each cell separately to improve the resolution of the image sensor in a time division multiplexed manner.

DETAILED DESCRIPTION OF THE INVENTION The invention will be better understood by the following description, which makes use of the accompanying drawings.

The present invention discloses a variable resolution sensor that uses a time division multiplexing method to change the charge addition method of a cluster having unit cells. This cluster is supported by a simple shared circuit, which collects charge and time division multiplexes, thus eliminating the need for complex charge summing circuits. The new variable resolution sensor allows for smaller pixels and improved pixel fill factor. Further, the method of the present invention allows for a tradeoff between image sensor resolution and S / N ratio or sensitivity to select the optimal illumination for each scene.

Structure of Sensor 10 Referring to FIG. 1, an active pixel sensor (APS) 10 is illustrated. The APS 10 includes an array 8, a line decoder 16 and a sense amplifier / readout multiplexer 18. The array 8 includes a number of multi-photodetector clusters 12. Each cluster 12 includes n unit cells 14.

Array 8 further includes a number of column detect lines and a number of row read lines. The column detect lines are shown as CloSense1-CloSenseH and the row read lines are RdRw1-Rd.
Shown as RwV. These lines carry corresponding signals, eg the row read line RdRw carries the row read signal RdRw. The charge accumulation or exposure of the unit cell 14 is controlled by the corresponding charge signal Int. This accumulated signal Int is transmitted by an integrated line indicated as Int. The clusters 12 are arranged in an array 8 of H columns and V rows.

In the illustrated embodiment, adjacent row read lines RdRw, such as rows i, i + 1, for example.
Share one row read line. Therefore, the read line is labeled with two symbols, such as RdRw1,2. Similarly, the column detection line CloSense _{j, j + 1} includes the photodetector cells connected to the column j and the column j +.
It is designed to be shared with the photodetector cell connected to 1.
Similarly, it is attached with two symbols. Thus, pairing elements offers the advantage of saving space.

Structure of Cluster 12 Referring to FIG. 2, there is shown a schematic diagram of a possible embodiment of cluster 12 useful for understanding the present invention. Each unit cell 14 includes a corresponding photodetector 22 and a corresponding transistor 24. The operation of cluster 12 is usually based on a direct injection circuit.

Specifically, cluster 12 includes four cells 14, shown as 14A-14D. However, the cluster 12 could alternatively be a unit cell of 8 or 16 pixels and is within the scope of the invention.
For clarity purposes, unit cells 14A-14D and corresponding elements are each A
Shown as -D.

Due to the novel structure of the present invention, the accumulated charges accumulated by the group of unit cells 14 can be added individually or in any combination, thus improving the resolution and the S / N ratio, that is, the sensitivity. It is possible to select the optimal balance of. The operation of the cluster 12 will be described below.

In the cluster 12, all the four unit cells 14 are clustered and one reset / read circuit 27 is shared. The circuit 27 includes a reset transistor 26, a storage capacitor 28, and a read transistor 30. With this configuration, the number of read transistors per one transistor 24 is 1/4 on average, the pixel pitch is reduced, and / or the cell factor for each unit cell 14 is increased, and The storage capacitance can be increased.

Therefore, by using a shared charge storage / readout circuit and a shared read / detect line, the structure of the cluster 12 is relatively simple and space can be saved.

The novel structure of the present invention can be used with other non-standard and standard techniques as well as circuit design techniques. Furthermore, the clustering of photodetectors can be applied to any type of APS image sensor and any type of active circuit to narrow the pixel pitch and improve the fill factor. Similarly, the present invention may be used in any semiconductor manufacturing process. In the particular embodiment shown in FIG. 2, transistor 24 is P-channel due to the polarity and process of the selected signal. However, considering other aspects, N
It is also possible to select channel type transistors to perform a common gate amplifier function.

Description will be made using the example shown in FIG. FIG. 3 illustrates an alternative cluster 112 that includes unit cells 114. In contrast to FIG. 2, the unit cell 1 of FIG.
14 includes N-channel transistor 104 which performs the same function as transistor 24 of FIG. Elements similar to those in FIG. 2 are designated by similar reference numerals, and description thereof will be omitted.
Referring to FIG. 4, an alternative clustered unit cell embodiment illustrating a four photogate cluster 212 is shown. Elements similar to those described above are designated by similar reference numerals, and their description is omitted.

The cluster 212 includes four unit cells 214 and a reset transistor 2
6, a buffer 108, and a read transistor 30. Each unit cell 2
Reference numeral 14 denotes the corresponding photogate sensor 102 and N-channel type transistor 10.
Including 4.

Similar to the principle described with reference to FIGS. 2 and 3, the four photogates 102 are
By sharing the reset, the source follower buffer 108, and the read transistor 30, the average number of transistors for one photogate sensor 102 is reduced.

Although only three embodiments have been described herein, other combinations of unit cells and shared circuits, such as photogates and P-channel transistors, are possible within the scope of the invention. I want you to understand.

The operation of the sensor 10 The detection of an image on the level of the sensor 10 is as follows (see FIG. 1).
. The associated storage signal Int in series is sent to the cluster 12 where the charge is stored. Normally, charges are accumulated in the storage capacitor in proportion to the charge accumulation time and the light intensity at that portion (not shown in FIG. 1).

Operation of Cluster 12 The operation of the cluster 12 will be described below (see FIG. 2). Cluster 112 (
The operation of FIG. 3) and cluster 212 (FIG. 4) are similar and are within the scope of the principles described below. Only the different operation of cluster 112 and cluster 212 will be described.

Operation Cycle The flow of the image detection and read cycle on the level of the cluster 12 in FIG. 2 will be described below. The cycle first activates the reset signal Rst,
The reset transistor 26 is made conductive, and the remaining capacitor 2 of the previous cycle
Flush 8 charges.

The photodetector 22, which is exposed to light, carries a corresponding photocurrent I _ph , denoted as I _ph-A −I _ph-D . Corresponding accumulation signals Int-A, Int-D are sent to the corresponding transistor 24, and the corresponding transistor 24 is opened, whereby the photocurrent I _ph flows from the corresponding photodetector 22.

The transistor 24 acting as a general gate amplifier separates the photodetector 22 and the capacitor 28, and can supply the photocurrent I _ph without being affected by the change in the voltage of the capacitor 28. Further, the transistor 24 transmits the photocurrent I _ph from the photodetector 22 to the capacitor 28.

[0049]   The accumulated signal Int becomes “high”, the corresponding transistor 24 is disconnected, and the photocurrent I _PH The charge storage cycle ends when the current flow is limited. The row read signal RdRw is
“High”, the read transistor 30 becomes conductive and is stored in the storage capacitor 28.
Charge is read out. Due to the conduction of the read transistor 30, the capacitor 2
The charge accumulated in 8 is transferred to the detection amplifier (not shown) via the column detection array ColSense.
Sent. The charge on capacitor 28 is then flushed and the cycle repeats.
Be done.

Note that transistor 26 is optional because the reset function can alternatively be performed by read transistor 30. In some read circuits, the residual charge remaining on capacitor 28 may be negligible, but is preferably flushed before the next storage subcycle.

Sub-cycle The image detection cycle includes a plurality of sub-cycles of the same length. Each sub-cycle includes resetting, accumulating and reading out the corresponding unit cell 14. Therefore, the total of four subcycles includes one subcycle for the unit cell 14A, one subcycle for the unit cell 14B, one subcycle for the unit cell 14C, and one subcycle for the unit cell 14D.

It should be noted that by setting the cluster 12 it is possible to program the time and number of sub-cycles. Therefore, it is possible to change the sampling of charge storage of the unit cell 14 to change the time and content of the sub-cycle. Also, the number of sub-cycles in one cycle can be changed.

As an example, four unit cells 14 can be individually sampled and one cycle can be divided into a total of four sub-cycles. Alternatively, the four unit cells 14 may be sampled in pairs to divide one cycle into a total of two subcycles. Further, it is also possible to sample four unit cells 14 simultaneously at one time so that one cycle is made up of one sub cycle.

Different levels of resolution and sensitivity can be obtained with each sampling method. The lowest sensitivity at the highest resolution can be achieved in four subcycles and the highest sensitivity at the lowest resolution can be achieved in one subcycle.

It should be noted that if the cluster 12 comprises eg 6 or 8 or 16 unit cells 14, the number of sub-cycles and the resulting image performance can be changed accordingly.

An operation example of each sub-cycle (each unit cell 14 is individually sampled) will be described below with reference to FIG. When the accumulated signals Int-B, Int-C, and Int-D go high, the photocurrent flow from the transistors 24B-24D is cut off. At this time, the accumulation signal Int-A becomes the V _bias voltage, that is, the "low" level, and the transistor 24A becomes conductive. The photocurrent I _ph-A from the photodetector 20A corresponds to the corresponding transistor 2
It is stored in the capacitor 28 through 4A. Next, the accumulated signal I _ph-A goes "high", and the flow of photocurrent from the transistor 24A is cut off. Next, the charges accumulated in the capacitor 28 are read out.

Next, the next sub-cycle is executed, and the accumulation signals Int-A, Int-C, and Int-D are set to "
Goes high and the accumulated signal Int-B goes low. This operation is similarly repeated for the unit cells 14C and 14B, and all the sub-cycles of the four unit cells 14 are completed, and all the sampling and reading of the image sensor 10 are completed.

It is possible to control the timing of the accumulation signals Int-A-Int-D to simultaneously turn on one or a plurality of transistors 24 and read out one or a plurality of corresponding unit cells 14 at the same time. Those of ordinary skill in the art will readily understand. As an example, two sub-cycles corresponding to the accumulation signals Int-A and int-B operate simultaneously, so that the photocurrents from the unit cells 14A and 14B are added simultaneously. By doing so, the spatial resolution in one direction is halved, the S / N ratio is √2 (representing the square root of 2), and the sensitivity is doubled.

As another example, in the simultaneous sub-cycle, the corresponding storage signals Int-A-Int-D operate simultaneously and photocurrents from all four unit cells 14 are added simultaneously. By doing so, the spatial resolution in each direction is halved, but the S / N ratio and sensitivity are significantly improved.

Therefore, by applying the photodetector clustering of the present invention,
It is possible to provide an efficient variable resolution function capable of making a trade-off between resolution and sensitivity.

The operation of the cluster 212 will be described with reference to FIG. In contrast to the example above, each photogate 102 stores charge in its own capacitor (not shown). Therefore, all photogates 102 accumulate charge and the charge accumulation time is not limited by using time division multiplexed sampling / reading. Cluster 2
12 also has a variable resolution capability, as described below with reference to FIGS. 5-8, but the accumulation time of cluster 212 remains constant. The improvement in S / N ratio is proportional to the number of photogates simultaneously sampled, and the resolution is inversely proportional.

Timing Diagram Referring to FIG. 5, there is shown a timing diagram showing the individual sub-cycles for each of the four unit cells 14, which is useful for understanding the operation of the embodiment shown in FIG. is there.

The signal polarities shown are for illustrative purposes and, if the polarities are reversed, may be applied to the embodiment shown in FIG. Referring to FIG. 5, elements similar to those already described are designated by similar reference numerals, and further description will be omitted.

For the purpose of clarifying the following description of the drawings, the reference numerals of the actions performed by the specific elements are designated by subscripts, and the description of the general actions are designated by subscripts. I don't. As an example, the photocurrent I _ph from transistor 22A is shown as photocurrent I _ph-A , and the photocurrent for general description purposes is shown as photocurrent I _ph .

In FIG. 5, four subcycles are shown as T _A , T _B , T _C , and T _D , respectively. In each sub-cycle T, the corresponding unit cell 14 goes through all cycles of reset, sampling, and reading. For example, in the sub cycle T _A , resetting, sampling, reading and the like in the photo detector 22A are performed.

Further, FIG. 5 shows the timings of the reset signal Rst, the four accumulation signals Int-A-Int-D, the capacitor photocurrent I _C , the capacitor voltage V _C , and the four row read signals RdRW _AD , respectively. ing.

The cycle shown in FIG. 5 begins at point 42 of subcycle T _A. At point 42, the reset signal Rst goes "high", thereby discharging the charge on the storage capacitor 28. Note that when the reset signal Rst is "high", all other signals (accumulation and Readlow) are "low".

[0068]   As shown at point 44, the reset signal Rst causes the capacitor voltage V _C Capacitor 28 is depleted of charge, as shown by next,
The reset signal Rst goes "low" and the transistor 26 is switched off.

Next, all accumulated signals Int-A-Int-D go “high” and the photodetector 22 is disconnected from the capacitor 28 for a short period of time, shown as period 46.

When the accumulation signal Int-A becomes the voltage V _bias , the charge accumulation sub-period T _int-A starts,
Transistor 24A acts as a common pre-gate amplifier, whereby the photocurrent I _ph-A from photodetector 22A flows to capacitor 28 during the charge storage sub-period T _int-A . During this period, the accumulation signals Int-C-Int-D are maintained at "high", so that the flow of photocurrent from the photodetectors 22B-22D is limited.

Therefore, since only the photocurrent I _ph from the transistor 22A flows, the capacitor photocurrent IC is equal to the photocurrent I _ph-A during the charge storage sub-period T _int-A . Furthermore, since the storage capacitor 28 is linear and is not expected to change with voltage, the voltage on the capacitor V _C rises linearly with time as shown by the slope 48.
Therefore, the end of I _c = I _ph-A and V _C = V _CA accumulation sub-period T _int-A is shown as the peak voltage V _CA. When the accumulation sub-period T _int-A ends, the read period T _Rd-A begins. Readout is continuously performed for each line of the array, and read-out signals RdRW _1,2 , RdRW _3,4 , ..., RdRW _{V-3, V-2} , which perform sampling of charges accumulated in the capacitor 28, R
Controlled by dRW _{V-1, V.}

Although sampling of the storage capacitor 28 causes the capacitor to be flushed as shown as drop 50, there may be some residual charge left on the capacitor 28 as shown by level 52.

Next, the reset signal Rst becomes "high", the sub-cycle T _B is initiated, capacitor beam current I _C is discharged from the storage capacitor 28. Each step performed in sub-cycle T _A is repeated in sub-cycle T _B -T _D with the appropriate signal for the corresponding unit cell 14.

Unless the image sensor enables individual tuning of the charge storage time for each unit cell 14, the storage period T _int and the read period T _rd of all photodetectors 22 in the cluster 12 are typically the same.
Therefore, the sub-cycle is T _A = T _B = T _C = T _D , and the total sampling / reading cycle T of the image sensor is 4 × T _A.

Other timings for charge storage sampling are possible. In the example shown in FIG. 6, a dual sub-cycle of simultaneously sampling photodetectors 22A and 22B is followed by simultaneous sampling of photodetectors 22C and 22D. Elements similar to those described above will be numbered similarly and further description will be omitted.

For example, as illustrated in FIG. 6, when the condenser photocurrent is I _c = I _ph-A + I _ph-B , and the photocurrents I _ph-A −I _ph-D are the same, I _c = 2I _ph-A = 2I _ph-D . Furthermore, the dual sub-cycle T _{A + B} + T _{C + D} = T _A + T _B + T _C + T _D.

As shown in FIG. 6, the time of the dual read sub-period T _{Rd-A + B} is approximately equal to the individual read period T _Rd-A . Therefore, the real time for the dual accumulation sub-period T _{int-A + B} will be longer and the capacitor voltage V _C , or V <sub>CA
+ B.</sub> Is considerably higher.

Referring to FIG. 7, simultaneous sampling of photodetectors 22A and 22C, followed by simultaneous sampling of photodetectors 22B and 22D is shown. The result of this sampling is similar to the result of the sampling illustrated in FIG.

Referring to FIG. 8, simultaneous sampling of all four photodetectors 22 is illustrated. This sampling method has the highest sensitivity but the lowest resolution. Calculations of S / N ratio and storage time are given in the Appendix.

Application Example of Sensor As will be apparent to those skilled in the art, the S / N ratio and resolution according to the embodiment illustrated in FIG. 5 are different from those in FIG. The S / N ratio is improved as the square root of the accumulation time, and since the accumulation time exceeds twice (because it is half the readout time for the same frame rate), the photocurrent signal of FIG. 6 is smaller than that of FIG. Over 2 times, the dual S / N ratio is more than √2 times better than the individual S / N ratio in the case of dual storage.

In contrast, the photodetectors 22A and 22B are in the same row and the photodetectors 22C and 22D are in the row below it, resulting in reduced horizontal resolution for the continuous sampling shown in FIG. . Therefore, in the case of the dual sub-cycle, the S / N ratio is improved but the resolution is lowered.

In the timing diagram of FIG. 7, the photodetectors 22A and 22C are
Are in the same column, but the photodetectors 22B and 22D are in the column to the right, which improves the signal-to-noise ratio but reduces the vertical resolution.

Finally, referring to FIG. 8, simultaneous sub-cycles reduce the resolution in both horizontal and vertical directions by half. However, the S / N ratio is significantly improved.

By analyzing the operation of FIGS. 5-8, it should be understood that the present invention can select a suitable resolution and a suitable S / N ratio depending on the application.

Those skilled in the art will appreciate that the present invention can be used with various conventional techniques. As an example, a backlit image sensor can be combined with a multi-photodetector unit cell to implement small pixels.

Those skilled in the art will appreciate that the present invention is not limited to the above description. The scope of the invention is limited only by the claims.

Appendix Formulas The trade-off between resolution and S / N ratio is described by the following set of formulas. The sum of the photocurrent I _{ph in} the capacitor is given by the following equation,

[0088]

[Equation 1]

The total of the current noise I _n is shown by the following equation.

[0090]

[Equation 2]

Where I _c is the total current stored in the capacitor at one time, I _ph-j is the individual current flowing from the jth photodetector into the capacitor,
i _n is the total current noise from the photodetectors, i _nj is the current noise of the jth photodetector, and K is the number of photodetectors that are conducting at the same time.

It should be noted from the above equation that the noise due to the photodetector is the main one and the other noise such as reset noise due to the switching transistor and 1 / f noise is negligible.

[0093]   The S / N ratio is defined as the following formula.

[0094]

[Equation 3]

In this case, if all photodetectors have the same photocurrent I _ph drop, the same noise is generated during the charge accumulation time, and other noise can be ignored, the thermal noise is given by the following equation.

[0096]

[Equation 4]

Here, S / N is S / N for one photodetector that charges the storage capacitor.
Is the N ratio, and (S / N) _K is the S / N ratio when the K photodetectors simultaneously charge the storage capacitor.

Therefore, as an example, when K = 4 and the charge accumulation time is constant, the S / N ratio is improved to double.

Under normal conditions, the photocurrent I _ph is usually very small, and the transistor operates in the weak inversion region. At this time, assuming that the storage capacitor is linear and does not change with voltage, the following formula is established.

[0100]

[Equation 5]

[0101]

[Equation 6]

Where I _C is the current from the capacitor and t is the accumulated sub-period. For example, if t is equal to the accumulated sub-period T _int , then the value of the capacitor voltage V _c can be expressed as:

[0103]

[Equation 7]

Further, when T _A is the sub-cycle of the photodetector A, T _int-A is the accumulation period of the photodetector A, and T _rd-A is the readout time of the photodetector A, the following formula is established.

[0105]

[Equation 8]

Normally, the accumulation period T _{i nt} and the reading period T _rd for all photodetectors in the cluster are the same, and the subcycle time T is also the same,

[0107]

[Equation 9]

Therefore, the total sampling / reading cycle T of the image sensor can be expressed by the following equation.

[0109]

[Equation 10]

Substituting equation (10) into equation (8), the maximum individual storage subcycle T _{int-max-individual} for one photodetector is

[0111]

[Equation 11]

It becomes Maximum dual storage subcycle T _{i nt-dual} also for one photodetector is greater than 2 times higher than the maximum individual storage sub-period T _int.

[0113]

[Equation 12]

From the equation (4), if the individual sub-cycles are changed to the dual sub-cycles, the S / N
The ratio improves as the square root of the integration time, doubling the photocurrent signal. Equations (4) and (12
), The S / N ratio of the dual sub-cycle can be expressed by the following equation.

[0115]

[Equation 13]

When all four photodetector currents I _ph are added to the storage capacitor at the same time, the horizontal and vertical resolutions are halved, but as shown in the following equation, S
The / N ratio is significantly improved.

[0117]

[Equation 14]

Example 1: When T = 33.33 ms and T _rd = 4 ms, the dual S / N ratio is individual S
3.4 times better than the / N ratio.

Example 2: When T = 33.33 ms and T _rd = 4 ms, the S / N ratio when all the photodetectors are added at the same time is improved by 10.4 times as compared with the case where the photodetectors are individually added.

[Brief description of drawings]

FIG. 1 illustrates an active pixel sensor (APS) image sensor structure embodied on a monolithic piece of semiconductor material, constructed and operative in accordance with a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram of a four-piece photodetector unit cell based on a direct injection (ID) circuit for use with the structure of FIG.

FIG. 3 is a schematic diagram of a four-photodetector unit cell similar to the unit cell of FIG. 2 and operating with opposite polarity signals.

FIG. 4 is a schematic diagram of an alternative four-element photodetector unit cell based on an N-channel photogate transistor.

5 is a timing diagram illustrating successive timings of individual control signals when implemented with the structure illustrated in FIG.

FIG. 6 is a timing diagram illustrating a sequence of control signals for a pair of simultaneously sampled horizontal photodetectors.

FIG. 7 is an imming diagram showing a sequence of control signals for a pair of vertical photodetectors sampled simultaneously.

FIG. 8 is a timing diagram showing a sequence of control signals for four photodetectors sampled simultaneously.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, C A, CH, CN, CR, CU, CZ, DE, DK, DM , DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, K E, KG, KP, KR, KZ, LC, LK, LR, LS , LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, R U, SD, SE, SG, SI, SK, SL, TJ, TM , TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW F-term (reference) 4M118 AA01 AA10 AB01 BA14 CA03                       CA07 DB09 DD11 DD12 FA06                       FA33 FA34                 5C024 CX03 CX41 GX02 GY31 GY38                       HX02 HX28

Claims (21)

[Claims] 1. A multi-cell cluster including a plurality of photodetection unit cells and a circuit, wherein each cell generates an electric charge corresponding to light detected, and the circuit is shared by the plurality of unit cells. A multi-cell cluster, wherein the readout of the charges is performed in substantially real time in the circuit. 2. The switch includes a switch corresponding to each unit cell, the corresponding unit cell is connected to the circuit by each switch, and each switch is controlled by a time division multiplexing method. The cluster according to claim 1, wherein 3. The cluster according to claim 1, wherein each unit cell includes one of a photodetector, a photodiode, or a photogate. 4. The cluster of claim 1, wherein the circuit includes a shared storage device for storing the charge at a focal plane. 5. The cluster of claim 1, wherein the circuit includes a shared reset circuit. 6. The cluster of claim 1, wherein the circuit comprises a shared read circuit. 7. A detection array comprising a plurality of clusters, a sampling line and a detection line, wherein the plurality of clusters detect light and generate a charge corresponding to the light. And a circuit shared by the unit cells for controlling the operation of the unit cells and for accumulating the charges, each sampling line for sampling the accumulated charges in a row of a cluster. To the row of the cluster, the detection line being connected to the column of the cluster for detecting the sampled charge in the column of the cluster. 8. The array of claim 7, wherein each line carries a programming signal to control the plurality of unit cells. 9. A method of operating an image sensor, the method comprising: accumulating charge from one or more unit cells of a cluster, and a focal plane from the at least one unit cell between the accumulating steps. A step of adding the charges in the step of: and reading the added charges. 10. The method of claim 9, wherein the one or more unit cells are programmed unit cells. 11. The method of claim 9, wherein the reading step includes reading the added charge in real time. 12. The method of claim 9, wherein the accumulating step comprises accumulating in a time division multiplexed manner. 13. The method of claim 9, wherein the storing step comprises separately storing charge from each of the unit cells. 14. The method of claim 9, wherein the storing step comprises the step of storing charge from two or more of the unit cells substantially simultaneously. 15. The method of claim 9, wherein the storing step comprises the step of storing charges from all the unit cells in the cluster at substantially the same time. 16. The method of claim 9, further comprising combining the readouts into an image. 17. The method according to claim 9, further comprising the step of dynamically controlling the selection of the number of the one or more unit cells in the step of accumulating the charges. 18. The method according to claim 17, wherein the dynamically controlling step includes the step of selecting the number of the one or more unit cells according to a light condition. 19. The method of claim 17, wherein all of the steps are performed in substantially real time. 20. The method of claim 9, further comprising increasing the number of the one or more cells in the storing step to improve the S / N ratio of the image sensor. 21. The method of claim 9, wherein the resolution of the image sensor is improved by performing the reading of each cell separately in a time division multiplexed manner.