JP2016131246A - 多層基板 - Google Patents

多層基板 Download PDF

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Publication number
JP2016131246A
JP2016131246A JP2016004551A JP2016004551A JP2016131246A JP 2016131246 A JP2016131246 A JP 2016131246A JP 2016004551 A JP2016004551 A JP 2016004551A JP 2016004551 A JP2016004551 A JP 2016004551A JP 2016131246 A JP2016131246 A JP 2016131246A
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Japan
Prior art keywords
semiconductor substrate
conductive particles
substrate
hole
holes
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Pending
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JP2016004551A
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English (en)
Japanese (ja)
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JP2016131246A5 (enExample
Inventor
誠一郎 篠原
Seiichiro Shinohara
誠一郎 篠原
恭志 阿久津
Yasushi Akutsu
恭志 阿久津
朋之 石松
Tomoyuki Ishimatsu
朋之 石松
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Dexerials Corp
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Dexerials Corp
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Publication of JP2016131246A publication Critical patent/JP2016131246A/ja
Publication of JP2016131246A5 publication Critical patent/JP2016131246A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
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    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
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    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01212—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps at a different location than on the final device, e.g. forming as prepeg
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    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01304—Manufacture or treatment of die-attach connectors using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
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    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01361—Chemical or physical modification, e.g. by sintering or anodisation
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    • H10W72/07221—Aligning
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    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07253—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in shapes
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    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
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    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07321—Aligning
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    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07332—Compression bonding, e.g. thermocompression bonding
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    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H10W72/07338—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/224—Bumps having multiple side-by-side cores
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/225—Bumps having a filler embedded in a matrix
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/234—Cross-sectional shape, i.e. in side view
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W72/241—Dispositions, e.g. layouts
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    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/251—Materials
    • H10W72/255—Materials of outermost layers of multilayered bumps, e.g. material of a coating
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    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
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    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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Landscapes

  • Non-Insulated Conductors (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Adhesive Tapes (AREA)
  • Combinations Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Laminated Bodies (AREA)
JP2016004551A 2015-01-13 2016-01-13 多層基板 Pending JP2016131246A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015004596 2015-01-13
JP2015004596 2015-01-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2020161100A Division JP7207383B2 (ja) 2015-01-13 2020-09-25 多層基板

Publications (2)

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JP2016131246A true JP2016131246A (ja) 2016-07-21
JP2016131246A5 JP2016131246A5 (enExample) 2019-02-21

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ID=56405861

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JP2016004551A Pending JP2016131246A (ja) 2015-01-13 2016-01-13 多層基板
JP2020161100A Active JP7207383B2 (ja) 2015-01-13 2020-09-25 多層基板

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2020161100A Active JP7207383B2 (ja) 2015-01-13 2020-09-25 多層基板

Country Status (6)

Country Link
US (1) US11901325B2 (enExample)
JP (2) JP2016131246A (enExample)
KR (1) KR102094725B1 (enExample)
CN (1) CN107210287B (enExample)
TW (2) TWI806814B (enExample)
WO (1) WO2016114320A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107210287B (zh) * 2015-01-13 2020-04-14 迪睿合株式会社 多层基板
JPWO2017149977A1 (ja) * 2016-02-29 2018-12-20 パナソニックＩｐマネジメント株式会社 非水電解質二次電池
WO2020133421A1 (zh) * 2018-12-29 2020-07-02 深南电路股份有限公司 多样化装配印刷线路板及制造方法
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