JP2015521795A - メモリセル、半導体デバイス構造、メモリシステムおよび作製方法 - Google Patents
メモリセル、半導体デバイス構造、メモリシステムおよび作製方法 Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/3218—Exchange coupling of magnetic films via an antiferromagnetic interface
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
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- H10N50/00—Galvanomagnetic devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
- H01F10/329—Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect
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Abstract
Description
Claims (20)
- 半導体デバイスであって、
少なくとも1つのメモリセルであって、前記少なくとも1つのメモリセルは、
磁気材料およびカプラー材料の交互の構造を含む磁気領域であって、前記磁気領域は垂直磁気配向を示す。
を含む、少なくとも1つのメモリセル、
を含む、半導体デバイス。 - 前記磁気材料およびカプラー材料の交互の構造は、前記磁気材料の磁気サブ領域と、前記カプラー材料のカプラーサブ領域とを含む、請求項1に記載の半導体デバイス。
- 前記磁気材料およびカプラー材料の交互の構造は、前記磁気材料の少なくとも3つの磁気サブ領域と、前記カプラー材料の少なくとも2つのカプラーサブ領域とを含む、請求項2に記載の半導体デバイス。
- 前記磁気サブ領域はそれぞれ、前記カプラーサブ領域のうちの1つにより、前記磁気サブ領域のうち別の磁気サブ領域から間隔を空けて配置される、請求項2に記載の半導体デバイス。
- 前記磁気サブ領域はそれぞれ、前記磁気サブ領域の隣接する磁気サブ領域が示す垂直磁気配向と反対方向に方向付けられた垂直磁気配向を示す、請求項2に記載の半導体デバイス。
- 前記磁気サブ領域はそれぞれ、約4オングストローム(4Å)(0.4nm)未満の高さを規定する、請求項2に記載の半導体デバイス。
- 前記少なくとも1つのメモリセルは、少なくとも2つの磁気領域を含み、前記少なくとも2つの磁気領域は、前記磁気領域および別の磁気領域を含む、請求項2に記載の半導体デバイス。
- 前記少なくとも2つの磁気領域は、自由領域および固定領域を含む、請求項7に記載の半導体デバイス。
- 前記少なくとも2つの磁気領域のうち少なくとも2つは、前記カプラーサブ領域を含む、請求項7に記載の半導体デバイス。
- 前記少なくとも2つの磁気領域のうち1つは、前記少なくとも2つの磁気領域のうちの別の磁気領域と異なる数のカプラーサブ領域を含む、請求項9に記載の半導体デバイス。
- 前記カプラー材料は、前記磁気材料の直接的に隣接するサブ領域とのRuderman Kittel Kasuya Yosida(RKKY)相互作用が得られるように、製剤および配置される、請求項1に記載の半導体デバイス。
- 前記カプラー材料は、前記磁気材料の隣接する磁気サブ領域を反強磁性的に接続するように、製剤される、請求項1に記載の半導体デバイス。
- 前記磁気領域は、白金およびパラジウムを含まない、請求項1〜12のうちいずれか1つに記載の半導体デバイス。
- 前記磁気材料は、実質的にコバルトからなる、請求項1〜12のうちいずれか1つに記載の半導体デバイス。
- 前記カプラー材料は、ルテニウムおよびロジウムのうち少なくとも1つを含む、請求項1〜12のうちいずれか1つに記載の半導体デバイス。
- 前記少なくとも1つのメモリセルは、複数のメモリセルをアレイ内に含み、
前記半導体デバイスは、前記少なくとも1つの磁気メモリセルと動作可能に通信する少なくとも1つの周辺デバイスをさらに含む、
請求項1〜12のうちいずれか1つに記載の半導体デバイス。 - メモリセルの形成方法であって、
磁気領域を形成することであって、
垂直磁気配向を示す磁気サブ領域を形成することと、
前記磁気サブ領域上にカプラーサブ領域を形成することと、
前記カプラーサブ領域上に別の磁気サブ領域を形成することであって、前記別の磁気サブ領域は、前記磁気サブ領域によって示される前記垂直磁気配向と反対方向に方向付けられた別の垂直磁気配向を示す、ことと、
前記別の磁気サブ領域上に別のカプラーサブ領域を形成することと、
を含むこと、
を含む、方法。 - 磁気領域を形成することは、前記メモリセルの固定領域、前記メモリセルの自由領域および前記メモリセルの基準領域のうちの1つを形成することを含む、請求項17に記載の方法。
- 別の磁気領域を形成することであって、さらなるカプラーサブ領域により相互に間隔を空けて配置されたさらなる磁気サブ領域を形成することを含む、ことをさらに含む、請求項17に記載の方法。
- 前記磁気領域と前記別の磁気領域との間に配置された非磁気領域を形成することをさらに含む、請求項19に記載の方法。
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US13/527,262 | 2012-06-19 | ||
US13/527,262 US9054030B2 (en) | 2012-06-19 | 2012-06-19 | Memory cells, semiconductor device structures, memory systems, and methods of fabrication |
PCT/US2013/045119 WO2013191958A2 (en) | 2012-06-19 | 2013-06-11 | Memory cells, semiconductor device structures, memory systems, and methods of fabrication |
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US (6) | US9054030B2 (ja) |
EP (1) | EP2862173B1 (ja) |
JP (1) | JP6096290B2 (ja) |
KR (1) | KR101749840B1 (ja) |
CN (1) | CN104395964B (ja) |
TW (1) | TWI512721B (ja) |
WO (1) | WO2013191958A2 (ja) |
Cited By (1)
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JP2015207593A (ja) * | 2014-04-17 | 2015-11-19 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 磁気抵抗素子 |
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