JP2013538460A - 冗長シリコン貫通ビアを伴う半導体チップ - Google Patents
冗長シリコン貫通ビアを伴う半導体チップ Download PDFInfo
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- JP2013538460A JP2013538460A JP2013528332A JP2013528332A JP2013538460A JP 2013538460 A JP2013538460 A JP 2013538460A JP 2013528332 A JP2013528332 A JP 2013528332A JP 2013528332 A JP2013528332 A JP 2013528332A JP 2013538460 A JP2013538460 A JP 2013538460A
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Abstract
【選択図】図2
Description
Claims (22)
- 第1の端部(127)および第2の端部(129)を含む第1の複数の導電ビア(115、120、125)を、第1の半導体チップ(15)の層(80)内に形成するステップと、
第1の導体パッド(65)を、前記第1の複数の導電ビアの前記第1の端部(127)とオーミック接触するように形成するステップと、
を含む製造方法。 - 第3の端部および第4の端部を含む第2の複数の導電ビア(130、135、140)を、前記層(80)内に形成するステップと、
第2の導体パッド(70)を、前記第3の端部とオーミック接触するように形成するステップと、
を含む請求項1に記載の方法。 - 導体構造(90)を、前記第1の複数の導電ビアの前記第2の端部とオーミック接触するように形成するステップを含む、請求項1に記載の方法。
- 前記導体構造は、再配線層構造を備える、請求項3に記載の方法。
- 入力/出力構造(40)を、前記第1の導体パッドに結合するステップを含む、請求項1に記載の方法。
- 前記入力/出力構造は、はんだバンプ(40)または導電ピラー(240)を備える、請求項5に記載の方法。
- 第2の半導体チップ(25)を前記第1の半導体チップ上に積層するステップを含む、請求項1に記載の方法。
- 前記第1の半導体チップを回路基板(20)上に実装するステップを含む、請求項1に記載の方法。
- 前記第1の複数の導電ビアは、トレンチ(200、205、210)を前記第1の半導体チップ内に形成し、前記トレンチ内に導電材料を配置することにより形成される、請求項1に記載の方法。
- 第1の端部(127)および第2の端部(129)を含む第1の複数の導電ビア(115、120、125)を、第1の側面(112)および第2の対向する側面(113)を有する第1の半導体チップ(15)の層(80)内に形成するステップと、
第1の導体構造(65)を、前記第1の側面に隣接させ、かつ、前記第1の複数の導電ビアの前記第1の端部とオーミック接触させて形成するステップと、
第2の導体構造(90)を、前記第2の側面に隣接させ、かつ、前記第1の複数の導電ビアの前記第2の端部とオーミック接触させて形成するステップと、
を含む製造方法。 - 前記第1の導体構造は導体パッドを備え、前記第2の導体構造は再配線層構造を備える、請求項10に記載の方法。
- 入力/出力構造(40)を、前記第1の導体構造に結合するステップを含む、請求項10に記載の方法。
- 前記入力/出力構造は、はんだバンプ(40)または導電ピラー(240)を備える、請求項12に記載の方法。
- 第2の半導体チップ(25)を前記第1の半導体チップ上に積層するステップを含む、請求項10に記載の方法。
- 層(80)を含む第1の半導体チップ(15)と、
前記第1の半導体チップに結合された第1の導体パッド(65)と、
前記層を縦貫し、第1の端部(127)および第2の端部(129)を有する第1の複数の導電ビア(115、120、125)であって、前記第1の端部が前記第1の導体パッドとオーミック接触する導電ビアと、を備える装置。 - 前記第1の半導体チップに結合された第2の導体パッド(70)と、
前記層を縦貫し、第3および第4の端部を有する第2の複数の導電ビア(130、135、140)とを備え、
前記第3の端部は、前記第2の導体パッドとオーミック接触する、請求項15に記載の装置。 - 前記第1の複数の導電ビアの前記第2の端部とオーミック接触する導体構造(90)を備える、請求項15に記載の装置。
- 前記導体構造は、再配線層構造を備える、請求項17に記載の装置。
- 前記第1の導体パッドに連結された、はんだバンプ(40)または導電ピラー(240)を備える、請求項15に記載の装置。
- 前記第1の半導体チップ上に積層された第2の半導体チップ(25)を備える、請求項15に記載の装置。
- 前記第1の半導体チップに結合された回路基板(20)を備える、請求項15に記載の装置。
- 層(80)を含む第1の半導体チップ(15)と、
前記第1の半導体チップに結合された第1の導体パッド(65)と、
前記層を縦貫し、第1の端部(127)および第2の端部(129)を有する第1の複数の導電ビア(115、120、125)であって、前記第1の端部が前記第1の導体パッドとオーミック接触する導電ビアとを備える、
コンピュータ読取可能媒体に格納された命令として具現化される装置。
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US12/878,542 US9437561B2 (en) | 2010-09-09 | 2010-09-09 | Semiconductor chip with redundant thru-silicon-vias |
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JP6013336B2 (ja) | 2016-10-25 |
US20230031099A1 (en) | 2023-02-02 |
WO2012034034A1 (en) | 2012-03-15 |
US9437561B2 (en) | 2016-09-06 |
CN103098204A (zh) | 2013-05-08 |
KR20130097766A (ko) | 2013-09-03 |
US20160365335A1 (en) | 2016-12-15 |
US11469212B2 (en) | 2022-10-11 |
US20120061821A1 (en) | 2012-03-15 |
KR101850121B1 (ko) | 2018-04-19 |
EP2614523A1 (en) | 2013-07-17 |
EP2614523B1 (en) | 2020-11-25 |
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