CN103098204A - 具有冗余穿硅通孔的半导体芯片 - Google Patents

具有冗余穿硅通孔的半导体芯片 Download PDF

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Publication number
CN103098204A
CN103098204A CN2011800433407A CN201180043340A CN103098204A CN 103098204 A CN103098204 A CN 103098204A CN 2011800433407 A CN2011800433407 A CN 2011800433407A CN 201180043340 A CN201180043340 A CN 201180043340A CN 103098204 A CN103098204 A CN 103098204A
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semiconductor chip
conductive
hole
conductive pad
ohmic contact
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CN103098204B (zh
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布莱恩·布莱克
迈克尔·Z·苏
贾迈尔·里法伊-艾哈迈德
乔·西格尔
塞思·普雷让
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ATI Technologies ULC
Advanced Micro Devices Inc
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ATI Technologies ULC
Advanced Micro Devices Inc
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Abstract

公开了一种具有导电通孔的半导体芯片及其制造方法。所述方法包括在第一半导体芯片（15）的一层（80）中形成第一多个导电通孔（115、120、125）。所述第一多个导电通孔包括第一末端（127）和第二末端（129）。第一导体垫（65）形成为与所述第一多个导电通孔的所述第一末端（127）欧姆接触。

Description

具有冗余穿硅通孔的半导体芯片
技术领域
本发明大致涉及半导体处理，且更具体地涉及并入穿硅通孔的半导体芯片及其制作方法。
发明背景
一段时间之前，半导体芯片设计者开始将多个半导体晶粒（dice）（即“晶粒（dies）”）垂直堆叠以获得更多功能，而无所需封装基板或电路板区域的相应增大。多种技术已被用于将邻近晶粒电连接为这种堆叠配置。一种技术涉及使用从一个晶粒上的接触垫引导至邻近晶粒上的相应接触垫的线接合。更近期引进的另一种技术涉及使用所谓的穿硅通孔（TSV）。典型的TSV是取决于芯片的一个或另一主表面上的任意中介导体垫的存在或不存在而延伸几乎或可能完全穿过半导体芯片的导电通孔。
典型的传统TSV提供半导体芯片的相对主表面之间的电布线。在一侧上，传统TSV连接至某些类型的输入/输出结构（I/O），其通常是被设计来在倒装芯片回流焊期间形成与封装基板焊接接合的焊块。TSV未直接连接至焊块而是连接至一些中介结构，诸如如块垫的最外金属化结构。TSV的另一端或背侧端通常透过一些中间导体结构连接至某些形式的背侧I/O结构。传统的TSV配置包括冶金接合至单个块垫的单个TSV。
传统TSV遭受焦耳加热及电迁移问题，其强度取决于功率电平、热管理、晶粒大小和其它因素而变化。一对一的TSV至块垫配置依据这种环境考虑。
本发明涉及一个或多个上述缺点的效应的克服或减小。
发明概要
根据本发明的一个方面，提供包括在第一半导体芯片的一层中形成第一多个导电通孔的制造方法。第一多个导电通孔包括第一末端和第二末端。第一导体垫形成为与第一多个导电通孔的第一末端欧姆接触。
根据本发明的另一个方面，提供包括在第一半导体芯片的一层中形成第一多个导电通孔的制造方法。第一多个导电通孔包括第一末端和第二末端。第一半导体芯片具有第一侧和第二及相对侧。第一导体垫形成为邻近第一侧且与第一多个导电通孔的第一末端欧姆接触。第二导体形成为邻近第二侧且与第一多个导电通孔的第二末端欧姆接触。
根据本发明的另一个方面，提供一种设备，其包括第一半导体芯片，所述第一半导体芯片具有一层和耦合至所述第一半导体芯片的第一导体垫。第一多个导电通孔穿过所述层且具有第一末端和第二末端。第一末端与第一导体垫欧姆接触。
附图简述
在阅读下文详细描述及参考附图时可了解本发明的上述和其它优点，其中：
图1是包括安装在电路板上的半导体芯片的半导体芯片装置的示例性实施方案的分解图示；
图2是在截面2-2上取得的图1的截面图；
图3是在截面3-3上取得的图2的截面图；
图4是如图3但连接至下伏导体垫的多个TSV的替代示例性实施方案的截面图；
图5是如图3但其中多个TSV连接至下伏导体垫的替代示例性实施方案的截面图；
图6是如图2但其中多个TSV是多组件的半导体芯片的替代示例性实施方案的截面图；
图7是经历示例性光刻处理的半导体芯片的截面图；
图8是如7但描绘TSV沟槽的示例性形成的截面图；
图9示出更大放大率下描绘图8的部分的截面图；
图10是如图8但描绘示例性TSV形成的截面图；
图11是如图10描绘半导体芯片的示例性薄化的截面图；
图12是如图11描绘薄化后的半导体芯片的截面图；和
图13是如图2但描绘并入具有导电柱输入/输出的多个TSV的替代示例性半导体芯片的截面图。
具体实施方式
本文中描述包括两个或更多个堆叠基板的半导体芯片装置的不同实施方案。一个实例包括具有多个TSV的至少一个半导体芯片。但是，多个TSV形成为与给定导体结构（诸如块或柱垫）欧姆接触。在具有冗余TSV至垫连接的情况下，给定TSV的故障不会使垫断路。现将描述附加详情。
在下述附图中，参考数字通常在相同元件出现在多个附图中的情况下重复。现参考附图且特别参考图1，其中示出包括安装在电路板20上的半导体芯片15的半导体芯片装置10的示例性实施方案的分解图示。半导体芯片15调适为具有一个或多个其它半导体芯片，其一示出并且标注为25，在其上安装为堆叠配置。半导体芯片15可经由多个互连结构（其可为导电柱、焊点或其它类型的互连）而与电路板20电介接。在这个说明性实施方案中，半导体芯片15可经由可包括冶金接合至电路板20的相应焊料结构30的半导体芯片15的对应焊料结构（不可见）的多个焊点与电路板20介接。电路板20可接着经由多个输入/输出结构与另一个电子装置（诸如另一个电路板或其它装置）电介接。在这个说明性实施方案中，输入/输出结构包括焊球35阵列。但是，熟练技工应了解也可使用其它类型的互连结构，诸如引脚栅格阵列、接点栅格阵列或其它互连结构。
本文公开的半导体芯片15的示例性结构不依赖于特定电子功能。因此，半导体芯片15和半导体芯片25可为电子装置中所使用的无数不同类型的电路装置的任意一种，诸如，例如微处理器、图形处理器、组合微处理器/图形处理器、专用集成电路、存储器装置、主动光学装置，诸如激光或类似物并且可为单核或多核或甚至侧向堆叠有附加晶粒。此外，半导体芯片15和25之一或两者可配置为具有或不具有一些逻辑电路的中介层。因此，术语“芯片”包括中介层。半导体芯片15和25可由块状半导体（诸如硅或锗）或绝缘体上半导体材料（诸如绝缘体上硅材料或其它芯片材料）组成。
本文公开的半导体芯片15的示例性结构不依赖于特定电子电路板功能。因此，电路板20可以是半导体芯片封装基板、电路卡或实际上任意其它类型的印刷电路板。虽然单片结构可用作电路板20，但是更典型的配置可使用积层设计。在此方面，电路板20可包括其上形成一个或多个积层且在其下方形成附加的一个或多个积层的中心层。中心层本身可包括一或多层的堆叠。如果实施为半导体芯片封装基板，那么电路板20中的层数可从四层变化为十六层或更多，但是可使用小于四层。也可使用所谓“无中心层”设计。电路板20层可包括散布有金属互连件的绝缘材料，诸如各种已知环氧树脂。可使用除积层以外的多层配置。任选地，电路板20可由已知陶瓷或适用于封装基板或其它印刷电路板的其它材料组成。电路板20设有许多导体迹线和通孔和其它结构（不可见）以提供半导体芯片15和25与另一个装置，诸如例如另一个电路板之间的电力、接地和信号传送。电路板20可经由输入/输出阵列诸如所描绘的球栅阵列电连接至另一个装置（未示出）。球栅阵列包括冶金接合至对应球垫（未示出）的上述多个焊球35。球垫（未示出）经由多个互连迹线和通孔和未示出的其它结构互连至电路板20中的不同导体垫。
半导体芯片15的补充细节将结合图2描述，所述图2是沿着截面2-2取得的图1的截面图。在讨论图2之前，注意图1的截面2-2穿过半导体芯片15的小部分。在所述背景下，现参考图2。如上文简述，半导体芯片15可包括被设计为与电路板20的互连结构30冶金接合的多个输入/输入结构。一对这种示例性互连结构可包括对应焊块40和45。焊块40和45可由不同类型的焊料，诸如无引线或基于引线的焊料组成。适当的无引线焊料的实例包括锡-银（大约97.3%Sn2.7%Ag）、锡-铜（大约99%Sn1%Cu）、锡-银-铜（大约96.5%Sn3%Ag0.5%Cu）或类似物。基于引线的焊料的实例包括低共熔比例或近低共熔比例的锡引线焊料或类似物。如上所述，焊球40和45可根据需要用导电柱或其它类型的互连结构取代。本文中，焊块40和45分别耦合至块下金属化（UBM）结构50和55。UBM结构50和55形成在钝化结构60上及钝化结构60中，其可为绝缘材料的单片或叠层膜。UBM结构50和55接着连接至导体结构或垫65和70。导体垫65和70可包括实际形成作为包括层间介电和金属层（未示出）的金属化层75的部分的导体垫。应了解图2是本质上稍微示意性的，因为导体垫65和70和金属化层75未按比例示出。在任何情况下，用作金属互连层75的层间介电层（未示出）可包括已知二氧化硅、其它类型的硅酸盐玻璃、低K介电膜或类似物。层75以及金属垫65和70和UBM结构50和55中的金属化结构可由不同导体组成，诸如铜、银、镍、铂、金、铝、钯或这些材料的合金或叠层或类似物。导体垫65和70可通过已知材料放置和图案化技术形成，诸如电镀、化学气相沉积（CVD）或类似技术及用化学蚀刻激光烧蚀或类似技术的光刻形成。
半导体芯片15是多层结构，即可能存在块状层80、其中可形成大量晶体管、电容器和其它电路装置的装置层85和金属化层75。金属化层75可形成为夹在连续堆积在装置层85上的层间介电层之间的一系列金属化层。因为半导体芯片15被设计为具有堆叠其上的另一个半导体芯片，诸如半导体芯片25，所以提供背侧金属化方案。在此方面，再分布层（RDL）90可形成在半导体层80上。RDL90可为与可处于相同或不同水平的一个或多个RDL金属化结构交织的一层或多层堆积或另外沉积的绝缘材料的单片或叠层结构。在这个说明性实施方案中，RDL金属化结构95和100可见。RDL90顶端具有绝缘或钝化层105和多个输入/输出结构110。钝化层105可为单片的或多个绝缘膜的叠层并且可由用于本文其它部分所述的钝化结构层60的相同类型的材料组成。输入/输出结构110可能是导电柱、垫、焊点或类似物并且用于建立与图2所描绘的半导体芯片25的电介接。互连结构110可由不同导体组成，诸如铜、银、镍、铂、金、铝、钯、这些材料的合金或叠层、焊料或类似物。RDL结构95和100可连接至互连结构110的一个或多个。
为了建立半导体芯片15的相对侧112与113之间及更具体地RDL结构95和100与导体垫65和70之间的导电路径，多个TSV（其三个可见并且标注为115、120和125）可形成在半导体层80中以延伸穿过装置层85和金属化层75并且将RDL结构95接合至导体垫65。以此方式，TSV的对应末端127接触导体垫65且其相对末端129接触RDL结构95。类似多个TSV130、135和140可将RDL结构100电接合至导体垫70。应了解术语“TSV”和“半导体”在本文中一般地使用，即半导体层80可由硅以外的材料及甚至绝缘材料（诸如二氧化硅、四乙基邻硅酸盐或其它材料）组成。与每个焊垫使用单个TSV的传统半导体芯片设计不同，本文所公开的实施方案针对给定导体垫使用多个TSV，诸如TSV115、120和125以及导体垫65。针对给定导体垫使用多个TSV提供改进的热应力散布并且降低电流密集及因此焦耳加热，其可增强电迁移存在时间。在使用连接至给定导体垫的多个TSV的情况下，因例如应力迁移断裂的TSV之一的故障可由其它剩余TSV补偿。TSV115、120、125、130、135和140可由多种材料组成，诸如铜、钨、石墨、铝、金、钯、这些材料的合金或类似物。设想覆层结构。
TSV115、120和125的补充细节现可通过参考图3了解，所述图3是沿着截面3-3取得的图2的截面图。在认真参考截面3-3之前，应注意截面3-3穿过导体垫65附近的TSV115、120和125。现参考图3。注意因截面3-3的位置，TSV115、120和125出现在截面中但下伏导体垫65被金属化层75遮挡且因此示作虚线。连接至导体垫65的TSV可比三个TSV115、120和125更多且在本文中实际上可包括共同标注为145的另外六个TSV。在这个说明性实施方案中，TSV115、120、125和145可配置为大致追踪下伏导体垫65的印迹的阵列。但是，熟练技工应了解连接至给定导体垫的TSV的实际空间配置可呈现如导体垫65可呈现的多种不同形状。还注意TSV115、120、125和145的构造可能大致是单片的。但是及如结合图4所描绘的替代实施方案所述，还可使用其它配置。
现参考图4，其是如图3但连接至下伏导体垫65的多个TSV115'的替代示例性实施方案的截面图。本文中，导体垫65再次示作虚线，因为其实际定位在金属化层75下方。如刚才所述，除单片配置以外的配置可用作给定TSV。因此，TSV115'可包括护套150和聚合物芯155。护套150可由铜、钨、石墨、铝、铂、金、钯、这些材料的合金或类似物组成。聚合物芯155可根据需要由导电或不导电的多种聚合物组成。实例包括Namics119、已知环氧树脂或类似物。这些所谓环形TSV可通过经由在电镀过程期间紧密控制电场生成的仔细定制电镀而形成。
如上所述，系至给定导体垫的TSV的配置可遭受大变化。在此方面，现参考图5，其是如图3但其中多个TSV115''连接至下伏导体垫65（其再次因其在金属化层75下方的位置而示作虚线）的替代示例性实施方案的截面图。本文中，TSV115''配置为不一定与导体垫65的稍微矩形印迹匹配的十字形配置。再次，可使用许多种配置并且仍实现系至给定导体垫的多个TSV的技术好处。
在上述说明性实施方案中，不同TSV制作为从顶部至底部的连续结构，即穿过图2所示的半导体装置层85和金属化层75。但是，熟练技工应了解多层结构可用作TSV。在此方面，现参考图6，其是如图2但可实质配置如本文其它部分所述的半导体芯片15但具有一些明显例外的半导体芯片15'的替代示例性实施方案。本文中，多个TSV160、162和164可连接至UBM结构50且多个TSV166、168和169可连接至UBM结构55。但是，TSV160和164经由对应TSV延伸部170和172连接且TSV166和169经由对应TSV延伸部174和176连接。本文中，TSV延伸部170、172、174和176可透过钝化结构60形成。
形成多个TSV的示例性过程现可通过参考图7、图8、图9、图10、图11和图12并且最初参考图7了解，所述图7是处于处理的初始阶段的半导体芯片15的截面图。在此阶段中，装置层85已使用许多已知处理步骤制作。金属化层75也可在TSV形成前全部或部分完成或未完成。此时，半导体芯片15具有主要被半导体层80占据的厚度Z，其大于如图2所示形成TSV和RDL90后的最终厚度。此时，适当光刻掩模178可施加至装置层85并且光刻图案化以建立开口180、184、188、192、196和198，其对应于后续形成的TSV115、120、125、130、135和140的所要位置。掩模178可由正调或负调的已知光阻材料组成。任选地，可使用非接触或甚至硬掩模。
现参考图8，在掩模178图案化之后，材料移除过程可用于在半导体层80中形成深沟槽200、205、210、215、220和225。沟槽200、205、210、215、220和225可通过具有或不具有等离子增强的化学蚀刻或其它材料移除技术形成。可使用激光烧蚀，但是应注意避免过度加热。当然，掩模178中的开口180、184、188、192、196和198被图案化为具有最终形成的沟槽200、205、210、215、220和225的所要印迹。取决于随后形成的TSV的组成，可能需要在沟槽200、205、210、215、220和225中形成内衬膜以促进至半导体层80的粘着以及防止TSV的原子、分子或较大部分迁移至半导体层80和装置层85中。图9示出以较大放大率示出的沟槽200的截面图。内衬层230可形成在沟槽200中并且不仅涂布沟槽200的侧壁而且涂布装置层85的侧壁。内衬层230可由多种材料组成，诸如二氧化硅。具有或不具有等离子增强的已知CVD技术可用于沉积内衬层230。相同过程可针对其它沟槽205、210、215、220和225完成。图8所示的掩模178可在内衬层230形成之前或之后通过灰化、溶剂反萃取或类似技术移除或在使用非接触掩模的情况下剥离。
在移除图7和图8所示的蚀刻掩模178后，TSV115、120、125、130、135和140可如图10所示形成在对应沟槽200、205、210、215、220和225中。如本文其它部分所述，TSV115、120、125、130、135和140可根据需要在对应沟槽200、205、210、215、220和225中形成为完整形成列或环形TSV。电镀过程根据需要可以是单步骤偏移电镀过程或可以是未偏移晶种层电镀过程，之后是偏移电镀过程。
为了使TSV115、120、125、130、135和140能建立与图2所示的后续形成RDL90中的结构的欧姆接触，半导体层80可如图11所示薄化。本文中，半导体层80的部分227可有利地通过化学机械平坦化（CMP）移除，但是可取代或结合CMP使用其它材料移除技术。在TSV115、120、125、130、135和140如图12所示暴露的情况下，图2所描绘的RDL90可使用可取决于RDL90的复杂性而计入多层的已知绝缘材料沉积和导体材料沉积和图案化技术制作。类似地，钝化结构95和互连结构110的制作可在RDL90形成之后。
再次参考图1，半导体芯片25可堆叠在半导体芯片15上并且取决于所使用的芯片至芯片界面类型而通过回流焊、压缩接合或其它技术电连接至其上。熟练技工应了解半导体芯片25可根据需要按晶圆级或晶粒级堆叠在半导体芯片15上。半导体芯片15和25可单个或整体安装至电路板20。
本文所公开的任意示例性实施方案可具体体现为安置在计算机可读介质（诸如，例如半导体、磁盘、光盘或其它存储介质）中的指令或计算机数据信号。指令或软件可能能够合成和\或模拟本文所公开的电路结构。在示例性实施方案中，电子设计自动化程序，诸如Cadence APD、Cadence Spectra、Encore或类似程序可用于合成所公开的电路结构。所得代码可用于制作所公开的电路结构。
虽然本发明可能具有不同修改和替代形式，但是特定实施方案已在附图中经由举例而示出并且已在其中详细描述。但是，应了解本发明不旨在受限于所公开的特定形式。而是，本发明将覆盖属于如下文附属权利要求所定义的本发明的精神和范围内的所有修改例、等效例和替代例。

Claims (22)

1.一种制造方法，其包括：
在第一半导体芯片（15）的一层（80）中形成第一多个导电通孔（115、120、125），所述第一多个导电通孔包括第一末端（127）和第二末端（129）；和
使第一导体垫（65）形成为与所述第一多个导电通孔的所述第一末端（127）欧姆接触。
2.根据权利要求1所述的方法，其包括在所述层（80）中形成第二多个导电通孔（130、135、140），所述第二多个导电通孔包括第三末端和第四末端，和使第二导体垫（70）形成为与所述第三末端欧姆接触。
3.根据权利要求1所述的方法，其包括使导体结构（90）形成为与所述第一多个导电通孔的所述第二末端欧姆接触。
4.根据权利要求3所述的方法，其中所述导体结构包括再分布层结构。
5.根据权利要求1所述的方法，其包括将输入/输出结构（40）耦合至所述第一导体垫。
6.根据权利要求5所述的方法，其中所述输入/输出结构包括焊块（40）或导电柱（240）。
7.根据权利要求1所述的方法，其包括将第二半导体芯片（25）堆叠在所述第一半导体芯片上。
8.根据权利要求1所述的方法，其包括将所述第一半导体芯片安装在电路板（20）上。
9.根据权利要求1所述的方法，其中所述第一多个导电通孔通过在所述第一半导体芯片中形成沟槽（200、205、210）并且将导体材料放置在所述沟槽中而形成。
10.一种制造方法，其包括：
在第一半导体芯片（15）的一层（80）中形成第一多个导电通孔（115、120、125），所述第一多个导电通孔包括第一末端（127）和第二末端（129），该第一半导体芯片具有第一侧（112）和第二及相对侧（113）；
使第一导体结构（65）形成为邻近所述第一侧并且与所述第一多个导电通孔的所述第一末端欧姆接触；和
使第二导体结构（90）形成为邻近所述第二侧并且与所述第一多个导电通孔的所述第二末端欧姆接触。
11.根据权利要求10所述的方法，其中所述第一导体结构包括导体垫且所述第二导体结构包括再分布层结构。
12.根据权利要求10所述的方法，其包括将输入/输出结构（40）耦合至所述第一导体。
13.根据权利要求12所述的方法，其中所述输入/输出结构包括焊块（40）或导电柱（240）。
14.根据权利要求10所述的方法，其包括将第二半导体芯片（25）堆叠在所述第一半导体芯片上。
15.一种设备，其包括：
第一半导体芯片（15），其包括一层（80）；
第一导体垫（65），其耦合至所述第一半导体芯片；和
第一多个导电通孔（115、120、125），其穿过所述层且具有第一末端（127）和第二末端（129），所述第一末端与所述第一导体垫欧姆接触。
16.根据权利要求15所述的设备，其中所述设备包括耦合至所述第一半导体芯片的第二导体垫（70）和穿过所述层且具有第三末端和第四末端的第二多个导电通孔（130、135、140），所述第三末端与所述第二导体垫欧姆接触。
17.根据权利要求15所述的设备，其包括与所述第一多个导电通孔的所述第二末端欧姆接触的导体结构（90）。
18.根据权利要求17所述的设备，其中所述导体结构包括再分布层结构。
19.根据权利要求15所述的设备，其包括耦合至所述第一导体垫的焊块（40）或导电柱（240）。
20.根据权利要求15所述的设备，其包括堆叠在所述第一半导体芯片上的第二半导体芯片（25）。
21.根据权利要求15所述的设备，其包括耦合至所述第一半导体芯片的电路板（20）。
22.一种设备，其包括：
第一半导体芯片（15），其包括一层（80）；
第一导体垫（65），其耦合至所述第一半导体芯片；
第一多个导电通孔（115、120、125），其穿过所述层且具有第一末端（127）及第二末端（129），所述第一末端与所述第一导体垫欧姆接触；和
其中所述设备具体体现为存储在计算机可读介质中的指令。
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