JP2013008435A - 半導体装置の駆動方法 - Google Patents
半導体装置の駆動方法 Download PDFInfo
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- JP2013008435A JP2013008435A JP2012111824A JP2012111824A JP2013008435A JP 2013008435 A JP2013008435 A JP 2013008435A JP 2012111824 A JP2012111824 A JP 2012111824A JP 2012111824 A JP2012111824 A JP 2012111824A JP 2013008435 A JP2013008435 A JP 2013008435A
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- 239000012528 membrane Substances 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 229910001510 metal chloride Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium atom Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- KZUNJOHGWZRPMI-UHFFFAOYSA-N samarium atom Chemical compound [Sm] KZUNJOHGWZRPMI-UHFFFAOYSA-N 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- FRNOGLGSGLTDKL-UHFFFAOYSA-N thulium atom Chemical compound [Tm] FRNOGLGSGLTDKL-UHFFFAOYSA-N 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
【解決手段】酸化物半導体を用いた書き込み用トランジスタ、該トランジスタと異なる半導体材料を用いた読み出し用のトランジスタ及び容量素子を含む不揮発性のメモリセルを有する半導体装置を提供する。メモリセルへの書き込みは、書き込み用トランジスタをオン状態として、書き込み用トランジスタのソース電極と、容量素子の電極の一方と、読み出し用トランジスタのゲート電極とが電気的に接続されたノードに電位を供給した後、書き込み用トランジスタをオフ状態として、ノードに所定量の電位を保持させることで行う。メモリセルの読み出しは、ビット線にプリチャージ電位を供給した後ビット線への電位の供給を止め、ビット線の電位がプリチャージ電位に保たれるか、または電位が下がるか、により行う。
【選択図】図1
Description
本実施の形態では、開示する発明の一態様に係る半導体装置の回路構成およびその動作について、図1乃至図11を参照して説明する。なお、回路図においては、酸化物半導体を用いたトランジスタであることを示すためにOSの符号を併せて付す場合がある。なお、本発明の一態様の主旨は著しく低いオフ電流を特徴とするトランジスタを用いた半導体装置を提案することにある。そのため、酸化物半導体を用いたトランジスタに代えて、酸化物半導体以外の材料を用いたオフ電流が小さいトランジスタを用いてもよい。
はじめに、最も基本的な回路構成およびその動作について、図1を参照して説明する。図1(A−1)に示す半導体装置において、ソース線SLとトランジスタ160のソース電極(またはドレイン電極)とは、電気的に接続され、ビット線BLとトランジスタ160のドレイン電極(またはソース電極)とは、電気的に接続されている。また、信号線Sとトランジスタ162のソース電極(またはドレイン電極)とは、電気的に接続され、書き込みワード線OSGと、トランジスタ162のゲート電極とは、電気的に接続されている。そして、トランジスタ160のゲート電極と、トランジスタ162のドレイン電極(またはソース電極)は、容量素子164の電極の一方と電気的に接続され、容量線Cと、容量素子164の電極の他方は電気的に接続されている。
図2は、図1(A−1)に示すメモリセルを2行×2列のマトリクス状に配置したメモリセルアレイの回路図である。図2におけるメモリセル170の構成は、図1(A−1)と同様である。図2(A)においては、それぞれのメモリセルにソース線SL、ビット線BL、信号線S、書き込みワード線OSG、容量線Cが電気的に接続されている。また、図2(B)においては、ビット線BLが信号線Sを兼ね、またソース線SLが2列のメモリセルにおいて共通化された構造を有している。
次に、図1に示す回路を応用したより具体的な回路構成について、図3を参照して説明する。なお、以下の説明においては、書き込み用トランジスタ(トランジスタ162)にnチャネル型トランジスタを用い、読み出し用トランジスタ(トランジスタ160)にpチャネル型トランジスタを用いる場合を例に説明する。なお、図3の回路図において、斜線を有する配線は、複数の信号線を含む配線である。
図4乃至図11に、図2(B)に係る半導体装置の書き込み、保持、及び読み出し動作に係るタイミングチャートの例を示す。タイミングチャート中のOSG、C等の名称は、タイミングチャートに示す電位が与えられる配線を示しており、同様の機能を有する配線が複数ある場合には、配線の名称の末尾に、1、m、n等を付すことで区別している。なお、開示する発明は以下に示す配列に限らない。
本実施の形態では、開示する発明の一態様に係る半導体装置の構成およびその作製方法について図12乃至図30を参照して説明する。
図12は、半導体装置の構成の一例である。図12(A)には、半導体装置の断面を、図12(B)には、半導体装置の平面を、それぞれ示す。ここで、図12(A)は、図12(B)のA1−A2およびB1−B2における断面に相当する。図12(A)および図12(B)に示す半導体装置は、下部に第1の半導体材料を用いたトランジスタ160を有し、上部に第2の半導体材料を用いたトランジスタ162を有する。ここで、第1の半導体材料と第2の半導体材料とは異なる材料とすることが望ましい。例えば、第1の半導体材料を酸化物半導体以外の半導体材料とし、第2の半導体材料を酸化物半導体とすることができる。酸化物半導体以外の半導体材料としては、例えば、シリコン、ゲルマニウム、シリコンゲルマニウム、炭化シリコン、またはガリウムヒ素等を用いることができ、単結晶半導体を用いることが好ましい。他に、有機半導体材料などを用いてもよい。このような半導体材料を用いたトランジスタは、高速動作が容易である。一方で、酸化物半導体を用いたトランジスタは、その特性により長期間の電位保持を可能とする。図12に示す半導体装置は、メモリセルとして用いることができる。
(a―A)2+(b―B)2+(c―C)2≦r2
を満たすことをいい、rは、例えば、0.05とすればよい。他の酸化物でも同様である。
次に、上記半導体装置の作製に用いられるSOI基板の作製方法の一例について、図13を参照して説明する。
次に、上記のSOI基板を用いた半導体装置の作製方法について、図14乃至図17を参照して説明する。
はじめに下部のトランジスタ160の作製方法について、図14および図15を参照して説明する。なお、図14および図15は、図13に示す方法で作成したSOI基板の一部であって、図12(A)に示す下部のトランジスタに相当する断面工程図である。
次に、上部のトランジスタ162の作製方法について、図16および図17を参照して説明する。
本実施の形態では、上述の実施の形態で説明した半導体装置を電子機器に適用する場合について、図31を用いて説明する。本実施の形態では、コンピュータ、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯情報端末(携帯型ゲーム機、音響再生装置なども含む)、デジタルカメラ、デジタルビデオカメラなどのカメラ、電子ペーパー、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)などの電子機器に、上述の半導体装置を適用する場合について説明する。
122 絶縁層
122a ゲート絶縁層
124 マスク
126 不純物領域
128a ゲート電極
128b 導電層
130 不純物領域
132 不純物領域
134 チャネル形成領域
136 絶縁層
138 絶縁層
140 絶縁層
142a ソース電極
142b ドレイン電極
144 酸化物半導体層
146 ゲート絶縁層
148a ゲート電極
148b 導電層
150 絶縁層
154 配線
156 絶縁層
160 トランジスタ
162 トランジスタ
164 容量素子
170 メモリセル
180 昇圧回路
182 駆動回路
184 駆動回路
186 駆動回路
190 駆動回路
192 駆動回路
194 駆動回路
500 半導体基板
510 単結晶半導体基板
512 酸化膜
514 脆化領域
516 単結晶半導体層
518 単結晶半導体層
701 筐体
702 筐体
703 表示部
704 キーボード
711 本体
712 スタイラス
713 表示部
714 操作ボタン
715 外部インターフェイス
720 電子書籍
721 筐体
723 筐体
725 表示部
727 表示部
731 電源
733 操作キー
735 スピーカー
737 軸部
740 筐体
741 筐体
742 表示パネル
743 スピーカー
744 マイクロフォン
745 操作キー
746 ポインティングデバイス
747 カメラ用レンズ
748 外部接続端子
749 太陽電池セル
750 外部メモリスロット
761 本体
763 接眼部
764 操作スイッチ
765 表示部
766 バッテリー
767 表示部
770 テレビジョン装置
771 筐体
773 表示部
775 スタンド
780 リモコン操作機
2101 下地絶縁膜
2102 絶縁膜
2103a 半導体領域
2103b 半導体領域
2103c 半導体領域
2104 ゲート絶縁膜
2105 ゲート
2106a 側壁絶縁膜
2106b 側壁絶縁膜
2107 絶縁膜
2108a ソース
2108b ドレイン
Claims (7)
- ビット線に第1のトランジスタのソース電極が電気的に接続され、ソース線に前記第1のトランジスタのドレイン電極が電気的に接続され、前記第1のトランジスタのゲート電極と、第2のトランジスタのドレイン電極と、容量素子の一方の電極が電気的に接続され、電位が保持されるノードが構成されるメモリセルを有する半導体装置の駆動方法であって、
データ読み出し期間において、
前記ソース線を接地電位とし、
前記ビット線をプリチャージ電位供給配線と接続し、前記ビット線をプリチャージ電位とした後、
前記ビット線と前記プリチャージ電位供給配線を接続解除することで、前記ビット線の電位が前記ノードに保持された電位に応じて変動させ、
前記変動を読み取ることにより、前記ノードに保持された電位を読み出す、半導体装置の駆動方法。 - 複数の信号線と、複数のビット線と、複数のソース線と、複数の容量線と、複数のメモリセルを含むメモリセルアレイと、を有し、
前記メモリセルの各々において、
前記複数のビット線の一に第1のトランジスタのソース電極が電気的に接続され、前記複数のソース線の一に前記第1のトランジスタのドレイン電極が電気的に接続され、前記第1のトランジスタのゲート電極と、第2のトランジスタのドレイン電極と、容量素子の一方の電極が電気的に接続され、前記容量素子の他方の電極が前記複数の容量線の一に電気的に接続され、第2のトランジスタのソース電極と複数の信号線の一に電気的に接続され、
前記第1のトランジスタのゲート電極と、前記第2のトランジスタのドレイン電極と、前記容量素子の一方の電極との間に、前記複数の信号線の一から与えられた電位が保持されるノードが構成される半導体装置の駆動方法であって、
データ読み出し期間において、
前記複数のメモリセルの一に接続する前記複数の容量線の一を接地電位としてメモリセルを選択し、
選択のメモリセルに接続する前記複数のソース線の一を接地電位とし、
選択のメモリセルに接続する前記複数のビット線の一をプリチャージ電位供給配線と電気的に接続し、前記複数のビット線の一をプリチャージ電位とした後、
前記複数のビット線の一と前記プリチャージ電位供給配線の接続を解除することで、前記複数のビット線の一の電位を前記ノードに保持された電位に応じて変動させ、
前記変動を読み取ることにより、前記選択のメモリセルの前記ノードに保持された電位を読み出す、半導体装置の駆動方法。 - 複数のビット線と、少なくとも1本のソース線と、複数の容量線と、複数のメモリセルを含むメモリセルアレイと、を有し、
前記メモリセルの各々において、
前記複数のビット線の一に第1のトランジスタのソース電極が電気的に接続され、前記ソース線に前記第1のトランジスタのドレイン電極が電気的に接続され、前記第1のトランジスタのゲート電極と、第2のトランジスタのドレイン電極と、容量素子の一方の電極が電気的に接続され、前記容量素子の他方の電極が前記複数の容量線の一に電気的に接続され、
前記第1のトランジスタのゲート電極と、前記第2のトランジスタのドレイン電極と、前記容量素子の一方の電極との間に、前記複数のビット線の一から与えられた電位が保持されるノードが構成される半導体装置の駆動方法であって、
データ読み出し期間において、
前記複数のメモリセルの一に接続する前記複数の容量線の一を接地電位としてメモリセルを選択し、
前記ソース線を接地電位とし、
選択のメモリセルに接続する前記複数のビット線の一をプリチャージ電位供給配線と電気的に接続し、前記複数のビット線の一をプリチャージ電位とした後、
前記複数のビット線の一と前記プリチャージ電位供給配線の接続を解除することで、前記複数のビット線の一の電位を前記ノードに保持された電位に応じて変動させ、
前記変動を読み取ることにより、前記選択のメモリセルの前記ノードに保持された電位を読み出す、半導体装置の駆動方法。 - 前記データ読み出し期間において、
非選択とするメモリセルの一の前記ソース線を前記プリチャージ電位供給配線と接続する、請求項2または請求項3に記載の半導体装置の駆動方法。 - 前記第1のトランジスタはpチャネル型トランジスタである、請求項1乃至請求項3のいずれか一に記載の半導体装置の駆動方法。
- 前記第1のトランジスタはnチャネル型トランジスタである、請求項1乃至請求項3のいずれか一に記載の半導体装置の駆動方法。
- 前記第2のトランジスタのチャネル形成領域は、酸化物半導体を含む請求項1乃至請求項6のいずれか一に記載の半導体装置の駆動方法。
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Also Published As
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US8649208B2 (en) | 2014-02-11 |
US20120294070A1 (en) | 2012-11-22 |
JP6013682B2 (ja) | 2016-10-25 |
TW201301287A (zh) | 2013-01-01 |
TWI570731B (zh) | 2017-02-11 |
KR101930542B1 (ko) | 2018-12-18 |
KR20120130059A (ko) | 2012-11-28 |
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