JP2012114148A5 - - Google Patents
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- Publication number
- JP2012114148A5 JP2012114148A5 JP2010260117A JP2010260117A JP2012114148A5 JP 2012114148 A5 JP2012114148 A5 JP 2012114148A5 JP 2010260117 A JP2010260117 A JP 2010260117A JP 2010260117 A JP2010260117 A JP 2010260117A JP 2012114148 A5 JP2012114148 A5 JP 2012114148A5
- Authority
- JP
- Japan
- Prior art keywords
- conductive portion
- forming
- insulating layer
- manufacturing
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010260117A JP2012114148A (ja) | 2010-11-22 | 2010-11-22 | 半導体装置の製造方法 |
| US13/193,569 US20120129335A1 (en) | 2010-11-22 | 2011-07-28 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010260117A JP2012114148A (ja) | 2010-11-22 | 2010-11-22 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2012114148A JP2012114148A (ja) | 2012-06-14 |
| JP2012114148A5 true JP2012114148A5 (enExample) | 2013-09-19 |
Family
ID=46064737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010260117A Pending JP2012114148A (ja) | 2010-11-22 | 2010-11-22 | 半導体装置の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20120129335A1 (enExample) |
| JP (1) | JP2012114148A (enExample) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8431478B2 (en) * | 2011-09-16 | 2013-04-30 | Chipmos Technologies, Inc. | Solder cap bump in semiconductor package and method of manufacturing the same |
| CN104241148B (zh) * | 2013-06-19 | 2017-08-25 | 中芯国际集成电路制造(上海)有限公司 | 一种在cpi测试中防止衬垫剥离的方法以及产生的器件 |
| JP6377894B2 (ja) * | 2013-09-03 | 2018-08-22 | 信越化学工業株式会社 | 半導体装置の製造方法、積層型半導体装置の製造方法、及び封止後積層型半導体装置の製造方法 |
| US20150179602A1 (en) * | 2013-12-20 | 2015-06-25 | Zigmund Ramirez Camacho | Integrated circuit packaging system with conductive ink and method of manufacture thereof |
| US9472515B2 (en) * | 2014-03-11 | 2016-10-18 | Intel Corporation | Integrated circuit package |
| US9691723B2 (en) * | 2015-10-30 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connector formation methods and packaged semiconductor devices |
| US9624094B1 (en) | 2015-11-13 | 2017-04-18 | Cypress Semiconductor Corporation | Hydrogen barriers in a copper interconnect process |
| ITUB20160027A1 (it) * | 2016-02-01 | 2017-08-01 | St Microelectronics Srl | Procedimento per produrre dispositivi a semiconduttore e corrispondente dispositivo |
| US10103114B2 (en) * | 2016-09-21 | 2018-10-16 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
| JP2018061018A (ja) * | 2016-09-28 | 2018-04-12 | ローム株式会社 | 半導体装置 |
| US10453816B2 (en) | 2016-09-28 | 2019-10-22 | Rohm Co., Ltd. | Semiconductor device |
| KR102077455B1 (ko) * | 2017-07-04 | 2020-02-14 | 삼성전자주식회사 | 반도체 장치 |
| IT201700087318A1 (it) | 2017-07-28 | 2019-01-28 | St Microelectronics Srl | Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici e suo metodo di preparazione |
| IT201700087201A1 (it) | 2017-07-28 | 2019-01-28 | St Microelectronics Srl | Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore |
| IT201700087174A1 (it) | 2017-07-28 | 2019-01-28 | St Microelectronics Srl | Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore |
| KR102029535B1 (ko) * | 2017-08-28 | 2019-10-07 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
| KR102486561B1 (ko) * | 2017-12-06 | 2023-01-10 | 삼성전자주식회사 | 재배선의 형성 방법 및 이를 이용하는 반도체 소자의 제조 방법 |
| US11469194B2 (en) | 2018-08-08 | 2022-10-11 | Stmicroelectronics S.R.L. | Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer |
| US11276632B2 (en) | 2018-12-24 | 2022-03-15 | Nepes Co., Ltd. | Semiconductor package |
| KR102240409B1 (ko) * | 2018-12-24 | 2021-04-15 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
| CN111354700A (zh) * | 2018-12-24 | 2020-06-30 | Nepes 株式会社 | 半导体封装件 |
| KR102877704B1 (ko) * | 2020-09-09 | 2025-10-28 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
| TW202528441A (zh) * | 2023-11-13 | 2025-07-16 | 日商富士軟片股份有限公司 | 樹脂組成物、硬化物、積層體、硬化物之製造方法、積層體之製造方法、半導體元件之製造方法、半導體元件及樹脂之製造方法 |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940010510B1 (ko) * | 1988-11-21 | 1994-10-24 | 세이꼬 엡슨 가부시끼가이샤 | 반도체 장치 제조 방법 |
| JP2679388B2 (ja) * | 1990-04-25 | 1997-11-19 | 富士電機株式会社 | 半導体装置の製造方法 |
| JPH04208531A (ja) * | 1990-08-10 | 1992-07-30 | Seiko Instr Inc | バンプ電極の製造法 |
| JPH06177127A (ja) * | 1991-05-30 | 1994-06-24 | Sony Corp | 配線形成方法 |
| US5470787A (en) * | 1994-05-02 | 1995-11-28 | Motorola, Inc. | Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same |
| AU6376796A (en) * | 1995-03-20 | 1996-10-16 | Mcnc | Solder bump fabrication methods and structure including a ti tanium barrier layer |
| US6436300B2 (en) * | 1998-07-30 | 2002-08-20 | Motorola, Inc. | Method of manufacturing electronic components |
| JP4564113B2 (ja) * | 1998-11-30 | 2010-10-20 | 株式会社東芝 | 微粒子膜形成方法 |
| US6749760B2 (en) * | 2001-10-26 | 2004-06-15 | Intel Corporation | Etchant formulation for selectively removing thin films in the presence of copper, tin, and lead |
| US6803323B2 (en) * | 2002-05-30 | 2004-10-12 | Freescale Semiconductor, Inc. | Method of forming a component overlying a semiconductor substrate |
| US20050092611A1 (en) * | 2003-11-03 | 2005-05-05 | Semitool, Inc. | Bath and method for high rate copper deposition |
| US7410833B2 (en) * | 2004-03-31 | 2008-08-12 | International Business Machines Corporation | Interconnections for flip-chip using lead-free solders and having reaction barrier layers |
| TW200603698A (en) * | 2004-04-13 | 2006-01-16 | Unitive International Ltd | Methods of forming solder bumps on exposed metal pads and related structures |
| JP2006222232A (ja) * | 2005-02-09 | 2006-08-24 | Fujitsu Ltd | 半導体装置およびその製造方法 |
| JP2006270031A (ja) * | 2005-02-25 | 2006-10-05 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
| JP2006303379A (ja) * | 2005-04-25 | 2006-11-02 | Seiko Epson Corp | 半導体装置の製造方法 |
| JP4232044B2 (ja) * | 2005-07-05 | 2009-03-04 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
| DE102005035772A1 (de) * | 2005-07-29 | 2007-02-01 | Advanced Micro Devices, Inc., Sunnyvale | Technik zum effizienten Strukturieren einer Höckerunterseitenmetallisierungsschicht unter Anwendung eines Trockenätzprozesses |
| US7449785B2 (en) * | 2006-02-06 | 2008-11-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Solder bump on a semiconductor substrate |
| JP4937623B2 (ja) * | 2006-03-29 | 2012-05-23 | シチズンホールディングス株式会社 | 半導体装置の製造方法 |
| US7485564B2 (en) * | 2007-02-12 | 2009-02-03 | International Business Machines Corporation | Undercut-free BLM process for Pb-free and Pb-reduced C4 |
| JP2008218884A (ja) * | 2007-03-07 | 2008-09-18 | Citizen Holdings Co Ltd | 半導体装置およびその製造方法 |
| JP5262045B2 (ja) * | 2007-09-27 | 2013-08-14 | 富士通セミコンダクター株式会社 | 電極の形成方法及び半導体装置の製造方法 |
| JP2010062175A (ja) * | 2008-09-01 | 2010-03-18 | Casio Comput Co Ltd | 半導体装置の製造方法 |
| US8003512B2 (en) * | 2009-02-03 | 2011-08-23 | International Business Machines Corporation | Structure of UBM and solder bumps and methods of fabrication |
-
2010
- 2010-11-22 JP JP2010260117A patent/JP2012114148A/ja active Pending
-
2011
- 2011-07-28 US US13/193,569 patent/US20120129335A1/en not_active Abandoned