JP2012114148A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP2012114148A
JP2012114148A JP2010260117A JP2010260117A JP2012114148A JP 2012114148 A JP2012114148 A JP 2012114148A JP 2010260117 A JP2010260117 A JP 2010260117A JP 2010260117 A JP2010260117 A JP 2010260117A JP 2012114148 A JP2012114148 A JP 2012114148A
Authority
JP
Japan
Prior art keywords
insulating layer
layer
barrier layer
forming
conductive portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010260117A
Other languages
English (en)
Japanese (ja)
Other versions
JP2012114148A5 (enExample
Inventor
Masamitsu Ikumo
雅光 生雲
Hiroyuki Yoda
博行 依田
Yasuhito Akutagawa
泰人 芥川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to JP2010260117A priority Critical patent/JP2012114148A/ja
Priority to US13/193,569 priority patent/US20120129335A1/en
Publication of JP2012114148A publication Critical patent/JP2012114148A/ja
Publication of JP2012114148A5 publication Critical patent/JP2012114148A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01257—Changing the shapes of bumps by reflowing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01933—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01935—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H10W72/01953—Changing the shapes of bond pads by etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2010260117A 2010-11-22 2010-11-22 半導体装置の製造方法 Pending JP2012114148A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010260117A JP2012114148A (ja) 2010-11-22 2010-11-22 半導体装置の製造方法
US13/193,569 US20120129335A1 (en) 2010-11-22 2011-07-28 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010260117A JP2012114148A (ja) 2010-11-22 2010-11-22 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2012114148A true JP2012114148A (ja) 2012-06-14
JP2012114148A5 JP2012114148A5 (enExample) 2013-09-19

Family

ID=46064737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010260117A Pending JP2012114148A (ja) 2010-11-22 2010-11-22 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US20120129335A1 (enExample)
JP (1) JP2012114148A (enExample)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015050365A (ja) * 2013-09-03 2015-03-16 信越化学工業株式会社 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法
JP2015173256A (ja) * 2014-03-11 2015-10-01 インテル コーポレイション 集積回路パッケージ
JP2018061018A (ja) * 2016-09-28 2018-04-12 ローム株式会社 半導体装置
JP2019102804A (ja) * 2017-12-06 2019-06-24 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 再配線の形成方法及びこれを利用する半導体素子の製造方法
CN111354700A (zh) * 2018-12-24 2020-06-30 Nepes 株式会社 半导体封装件
KR20200079164A (ko) * 2018-12-24 2020-07-02 주식회사 네패스 반도체 패키지 및 그의 제조 방법
US11276632B2 (en) 2018-12-24 2022-03-15 Nepes Co., Ltd. Semiconductor package
US11545454B2 (en) 2016-09-28 2023-01-03 Rohm Co., Ltd. Semiconductor device
WO2025105367A1 (ja) * 2023-11-13 2025-05-22 富士フイルム株式会社 樹脂組成物、硬化物、積層体、硬化物の製造方法、積層体の製造方法、半導体デバイスの製造方法、半導体デバイス、及び、樹脂の製造方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8431478B2 (en) * 2011-09-16 2013-04-30 Chipmos Technologies, Inc. Solder cap bump in semiconductor package and method of manufacturing the same
CN104241148B (zh) * 2013-06-19 2017-08-25 中芯国际集成电路制造(上海)有限公司 一种在cpi测试中防止衬垫剥离的方法以及产生的器件
US20150179602A1 (en) * 2013-12-20 2015-06-25 Zigmund Ramirez Camacho Integrated circuit packaging system with conductive ink and method of manufacture thereof
US9691723B2 (en) * 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
US9624094B1 (en) * 2015-11-13 2017-04-18 Cypress Semiconductor Corporation Hydrogen barriers in a copper interconnect process
ITUB20160027A1 (it) * 2016-02-01 2017-08-01 St Microelectronics Srl Procedimento per produrre dispositivi a semiconduttore e corrispondente dispositivo
US10103114B2 (en) * 2016-09-21 2018-10-16 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
KR102077455B1 (ko) * 2017-07-04 2020-02-14 삼성전자주식회사 반도체 장치
IT201700087201A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore
IT201700087318A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici e suo metodo di preparazione
IT201700087174A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore
KR102029535B1 (ko) * 2017-08-28 2019-10-07 삼성전기주식회사 팬-아웃 반도체 패키지
US11469194B2 (en) 2018-08-08 2022-10-11 Stmicroelectronics S.R.L. Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer
KR102877704B1 (ko) * 2020-09-09 2025-10-28 삼성전자주식회사 반도체 패키지 및 이의 제조 방법

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410431A (ja) * 1990-04-25 1992-01-14 Fuji Electric Co Ltd 半導体装置の製造方法
JPH04208531A (ja) * 1990-08-10 1992-07-30 Seiko Instr Inc バンプ電極の製造法
JP2000164531A (ja) * 1998-11-30 2000-06-16 Toshiba Corp 微粒子膜形成装置・形成方法、ならびに半導体装置およびその製造方法
JP2006270031A (ja) * 2005-02-25 2006-10-05 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2007266381A (ja) * 2006-03-29 2007-10-11 Citizen Holdings Co Ltd 半導体装置の製造方法
JP2008218884A (ja) * 2007-03-07 2008-09-18 Citizen Holdings Co Ltd 半導体装置およびその製造方法
JP2009503852A (ja) * 2005-07-29 2009-01-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ドライエッチプロセスを使用してアンダーバンプメタル層を効率的にパターニングする技術
JP2010062175A (ja) * 2008-09-01 2010-03-18 Casio Comput Co Ltd 半導体装置の製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940010510B1 (ko) * 1988-11-21 1994-10-24 세이꼬 엡슨 가부시끼가이샤 반도체 장치 제조 방법
JPH06177127A (ja) * 1991-05-30 1994-06-24 Sony Corp 配線形成方法
US5470787A (en) * 1994-05-02 1995-11-28 Motorola, Inc. Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same
EP1134805B1 (en) * 1995-03-20 2004-07-21 Unitive International Limited Solder bump fabrication methods and structure including a titanium barrier layer
US6436300B2 (en) * 1998-07-30 2002-08-20 Motorola, Inc. Method of manufacturing electronic components
US6749760B2 (en) * 2001-10-26 2004-06-15 Intel Corporation Etchant formulation for selectively removing thin films in the presence of copper, tin, and lead
US6803323B2 (en) * 2002-05-30 2004-10-12 Freescale Semiconductor, Inc. Method of forming a component overlying a semiconductor substrate
US20050092611A1 (en) * 2003-11-03 2005-05-05 Semitool, Inc. Bath and method for high rate copper deposition
US7410833B2 (en) * 2004-03-31 2008-08-12 International Business Machines Corporation Interconnections for flip-chip using lead-free solders and having reaction barrier layers
WO2005101499A2 (en) * 2004-04-13 2005-10-27 Unitive International Limited Methods of forming solder bumps on exposed metal pads and related structures
JP2006222232A (ja) * 2005-02-09 2006-08-24 Fujitsu Ltd 半導体装置およびその製造方法
JP2006303379A (ja) * 2005-04-25 2006-11-02 Seiko Epson Corp 半導体装置の製造方法
JP4232044B2 (ja) * 2005-07-05 2009-03-04 セイコーエプソン株式会社 半導体装置の製造方法
US7449785B2 (en) * 2006-02-06 2008-11-11 Taiwan Semiconductor Manufacturing Co., Ltd. Solder bump on a semiconductor substrate
US7485564B2 (en) * 2007-02-12 2009-02-03 International Business Machines Corporation Undercut-free BLM process for Pb-free and Pb-reduced C4
JP5262045B2 (ja) * 2007-09-27 2013-08-14 富士通セミコンダクター株式会社 電極の形成方法及び半導体装置の製造方法
US8003512B2 (en) * 2009-02-03 2011-08-23 International Business Machines Corporation Structure of UBM and solder bumps and methods of fabrication

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410431A (ja) * 1990-04-25 1992-01-14 Fuji Electric Co Ltd 半導体装置の製造方法
JPH04208531A (ja) * 1990-08-10 1992-07-30 Seiko Instr Inc バンプ電極の製造法
JP2000164531A (ja) * 1998-11-30 2000-06-16 Toshiba Corp 微粒子膜形成装置・形成方法、ならびに半導体装置およびその製造方法
JP2006270031A (ja) * 2005-02-25 2006-10-05 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2009503852A (ja) * 2005-07-29 2009-01-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ドライエッチプロセスを使用してアンダーバンプメタル層を効率的にパターニングする技術
JP2007266381A (ja) * 2006-03-29 2007-10-11 Citizen Holdings Co Ltd 半導体装置の製造方法
JP2008218884A (ja) * 2007-03-07 2008-09-18 Citizen Holdings Co Ltd 半導体装置およびその製造方法
JP2010062175A (ja) * 2008-09-01 2010-03-18 Casio Comput Co Ltd 半導体装置の製造方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015050365A (ja) * 2013-09-03 2015-03-16 信越化学工業株式会社 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法
JP2015173256A (ja) * 2014-03-11 2015-10-01 インテル コーポレイション 集積回路パッケージ
JP2018061018A (ja) * 2016-09-28 2018-04-12 ローム株式会社 半導体装置
US11545454B2 (en) 2016-09-28 2023-01-03 Rohm Co., Ltd. Semiconductor device
US11810881B2 (en) 2016-09-28 2023-11-07 Rohm Co., Ltd. Semiconductor device
US12183701B2 (en) 2016-09-28 2024-12-31 Rohm Co., Ltd. Semiconductor device
JP2019102804A (ja) * 2017-12-06 2019-06-24 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 再配線の形成方法及びこれを利用する半導体素子の製造方法
CN111354700A (zh) * 2018-12-24 2020-06-30 Nepes 株式会社 半导体封装件
KR20200079164A (ko) * 2018-12-24 2020-07-02 주식회사 네패스 반도체 패키지 및 그의 제조 방법
KR102317208B1 (ko) * 2018-12-24 2021-10-25 주식회사 네패스 반도체 패키지 및 그의 제조 방법
US11276632B2 (en) 2018-12-24 2022-03-15 Nepes Co., Ltd. Semiconductor package
WO2025105367A1 (ja) * 2023-11-13 2025-05-22 富士フイルム株式会社 樹脂組成物、硬化物、積層体、硬化物の製造方法、積層体の製造方法、半導体デバイスの製造方法、半導体デバイス、及び、樹脂の製造方法

Also Published As

Publication number Publication date
US20120129335A1 (en) 2012-05-24

Similar Documents

Publication Publication Date Title
JP2012114148A (ja) 半導体装置の製造方法
TWI449140B (zh) 積體電路裝置及封裝組件
JP4327656B2 (ja) 半導体装置
JP5582811B2 (ja) 半導体装置及びその製造方法
TWI582930B (zh) 積體電路裝置及封裝組件
US9391036B2 (en) Semiconductor device and manufacturing method thereof
CN102024769B (zh) 集成电路元件
JP4922891B2 (ja) 半導体装置およびその製造方法
US7221054B2 (en) Bump structure
US20140327133A1 (en) Metal bump structure for use in driver ic and method for forming the same
CN1988143B (zh) 半导体器件及其制造方法
US20110291263A1 (en) Ic having dielectric polymeric coated protruding features having wet etched exposed tips
US8309373B2 (en) Method of manufacturing semiconductor device
US8093148B2 (en) Method for manufacturing semiconductor device having electrode for external connection
JP6152434B2 (ja) 半導体装置
JP2011071175A (ja) 半導体装置および半導体装置の製造方法
JP5873146B2 (ja) 半導体装置
JP2006351767A (ja) 半導体装置及びその製造方法
JP2009302340A (ja) 半導体装置の製造方法
JP2006120803A (ja) 半導体装置及び半導体装置の製造方法
JP2009016830A (ja) チップ積層構造物及びその製造方法
TWI904718B (zh) 用於在兩個基底之間形成導電結構的方法
JP2002237500A (ja) 半導体装置の製造方法
JP4868379B2 (ja) 半導体素子およびその製造方法
JP2011113992A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130801

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130801

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140227

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140401

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140528

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140902

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141030

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20150106