JP2012009586A - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents

配線基板、半導体装置及び配線基板の製造方法 Download PDF

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Publication number
JP2012009586A
JP2012009586A JP2010143514A JP2010143514A JP2012009586A JP 2012009586 A JP2012009586 A JP 2012009586A JP 2010143514 A JP2010143514 A JP 2010143514A JP 2010143514 A JP2010143514 A JP 2010143514A JP 2012009586 A JP2012009586 A JP 2012009586A
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JP
Japan
Prior art keywords
insulating layer
wiring board
pad
wiring
solder resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010143514A
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English (en)
Japanese (ja)
Other versions
JP2012009586A5 (enExample
Inventor
Shigeji Muramatsu
茂次 村松
Satoshi Haruhara
聡 春原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010143514A priority Critical patent/JP2012009586A/ja
Priority to US13/166,083 priority patent/US8508050B2/en
Publication of JP2012009586A publication Critical patent/JP2012009586A/ja
Publication of JP2012009586A5 publication Critical patent/JP2012009586A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/281—Auxiliary members
    • H10W72/287—Flow barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H10W72/387—Flow barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2010143514A 2010-06-24 2010-06-24 配線基板、半導体装置及び配線基板の製造方法 Pending JP2012009586A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010143514A JP2012009586A (ja) 2010-06-24 2010-06-24 配線基板、半導体装置及び配線基板の製造方法
US13/166,083 US8508050B2 (en) 2010-06-24 2011-06-22 Wiring substrate, semiconductor device, and method for manufacturing wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010143514A JP2012009586A (ja) 2010-06-24 2010-06-24 配線基板、半導体装置及び配線基板の製造方法

Publications (2)

Publication Number Publication Date
JP2012009586A true JP2012009586A (ja) 2012-01-12
JP2012009586A5 JP2012009586A5 (enExample) 2013-04-18

Family

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Family Applications (1)

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JP2010143514A Pending JP2012009586A (ja) 2010-06-24 2010-06-24 配線基板、半導体装置及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US8508050B2 (enExample)
JP (1) JP2012009586A (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013239604A (ja) * 2012-05-16 2013-11-28 Ngk Spark Plug Co Ltd 配線基板
JP2014029972A (ja) * 2012-06-29 2014-02-13 Kyocer Slc Technologies Corp 配線基板
JP2015012162A (ja) * 2013-06-28 2015-01-19 株式会社デンソー モールドパッケージおよびその製造方法
CN104602459A (zh) * 2013-10-30 2015-05-06 京瓷电路科技株式会社 布线基板及其制造方法
KR101523479B1 (ko) * 2012-08-09 2015-05-27 니혼도꾸슈도교 가부시키가이샤 배선기판
US9185806B2 (en) 2012-09-28 2015-11-10 Ibiden Co., Ltd. Method for manufacturing printed wiring board and printed wiring board
JP2022021766A (ja) * 2020-07-22 2022-02-03 キオクシア株式会社 半導体装置
JP2023067260A (ja) * 2021-10-29 2023-05-16 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9406579B2 (en) * 2012-05-14 2016-08-02 STATS ChipPAC Pte. Ltd. Semiconductor device and method of controlling warpage in semiconductor package
KR20140019173A (ko) * 2012-08-06 2014-02-14 삼성전기주식회사 솔더 코팅볼을 이용한 패키징 방법 및 이에 따라 제조된 패키지
JP5475077B2 (ja) * 2012-09-07 2014-04-16 日本特殊陶業株式会社 配線基板およびその製造方法
US20140124254A1 (en) * 2012-11-05 2014-05-08 Nvidia Corporation Non-solder mask defined copper pad and embedded copper pad to reduce packaging system height
US20140183744A1 (en) * 2012-12-28 2014-07-03 Texas Instruments Incorporated Package substrate with bondable traces having different lead finishes
JP6352644B2 (ja) * 2014-02-12 2018-07-04 新光電気工業株式会社 配線基板及び半導体パッケージの製造方法
JP2015195272A (ja) * 2014-03-31 2015-11-05 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
JP2015231003A (ja) * 2014-06-06 2015-12-21 イビデン株式会社 回路基板および回路基板の製造方法
JP2016058673A (ja) * 2014-09-12 2016-04-21 イビデン株式会社 プリント配線板およびその製造方法
JP2017050315A (ja) * 2015-08-31 2017-03-09 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
JP2017050313A (ja) * 2015-08-31 2017-03-09 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
US11201066B2 (en) 2017-01-31 2021-12-14 Skyworks Solutions, Inc. Control of under-fill using a dam on a packaging substrate for a dual-sided ball grid array package
US20180350630A1 (en) * 2017-06-01 2018-12-06 Qualcomm Incorporated Symmetric embedded trace substrate
US11545425B2 (en) 2020-10-08 2023-01-03 Qualcomm Incorporated Substrate comprising interconnects embedded in a solder resist layer
US11823983B2 (en) * 2021-03-23 2023-11-21 Qualcomm Incorporated Package with a substrate comprising pad-on-pad interconnects
US11621220B2 (en) * 2021-03-25 2023-04-04 Advanced Semiconductor Engineering, Inc. Assembly structure and method for manufacturing the same
US20240332192A1 (en) * 2023-03-30 2024-10-03 Advanced Semiconductor Engineering, Inc. Package structure

Citations (4)

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JP2007035692A (ja) * 2005-07-22 2007-02-08 Matsushita Electric Ind Co Ltd 電子部品実装構造および電子部品実装方法
JP2009289914A (ja) * 2008-05-28 2009-12-10 Shinko Electric Ind Co Ltd 配線基板
JP2010010494A (ja) * 2008-06-27 2010-01-14 Kyocer Slc Technologies Corp 配線基板およびその製造方法
JP2010040936A (ja) * 2008-08-07 2010-02-18 Kyocer Slc Technologies Corp 配線基板およびその製造方法

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US5218234A (en) 1991-12-23 1993-06-08 Motorola, Inc. Semiconductor device with controlled spread polymeric underfill
JP3792445B2 (ja) * 1999-03-30 2006-07-05 日本特殊陶業株式会社 コンデンサ付属配線基板
JP3997903B2 (ja) 2002-11-29 2007-10-24 富士通株式会社 回路基板および半導体装置
JP2005283478A (ja) 2004-03-30 2005-10-13 Ricoh Elemex Corp 超音波流量計
JP4769022B2 (ja) 2005-06-07 2011-09-07 京セラＳｌｃテクノロジー株式会社 配線基板およびその製造方法
JP5091469B2 (ja) 2006-12-05 2012-12-05 京セラＳｌｃテクノロジー株式会社 配線基板およびその製造方法
JP4800253B2 (ja) * 2007-04-04 2011-10-26 新光電気工業株式会社 配線基板の製造方法
JP5138277B2 (ja) * 2007-05-31 2013-02-06 京セラＳｌｃテクノロジー株式会社 配線基板およびその製造方法
JP5203045B2 (ja) * 2008-05-28 2013-06-05 日本特殊陶業株式会社 多層配線基板の中間製品、多層配線基板の製造方法
JP5079646B2 (ja) * 2008-08-26 2012-11-21 新光電気工業株式会社 半導体パッケージ及びその製造方法と半導体装置
JP5313626B2 (ja) * 2008-10-27 2013-10-09 新光電気工業株式会社 電子部品内蔵基板及びその製造方法

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JP2007035692A (ja) * 2005-07-22 2007-02-08 Matsushita Electric Ind Co Ltd 電子部品実装構造および電子部品実装方法
JP2009289914A (ja) * 2008-05-28 2009-12-10 Shinko Electric Ind Co Ltd 配線基板
JP2010010494A (ja) * 2008-06-27 2010-01-14 Kyocer Slc Technologies Corp 配線基板およびその製造方法
JP2010040936A (ja) * 2008-08-07 2010-02-18 Kyocer Slc Technologies Corp 配線基板およびその製造方法

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101523478B1 (ko) * 2012-05-16 2015-05-27 니혼도꾸슈도교 가부시키가이샤 배선기판
JP2013239604A (ja) * 2012-05-16 2013-11-28 Ngk Spark Plug Co Ltd 配線基板
US9179552B2 (en) 2012-05-16 2015-11-03 Nrk Spark Plug Co., Ltd. Wiring board
JP2014029972A (ja) * 2012-06-29 2014-02-13 Kyocer Slc Technologies Corp 配線基板
US9699905B2 (en) 2012-08-09 2017-07-04 Ngk Spark Plug Co., Ltd. Wiring board
KR101523479B1 (ko) * 2012-08-09 2015-05-27 니혼도꾸슈도교 가부시키가이샤 배선기판
US9185806B2 (en) 2012-09-28 2015-11-10 Ibiden Co., Ltd. Method for manufacturing printed wiring board and printed wiring board
JP2015012162A (ja) * 2013-06-28 2015-01-19 株式会社デンソー モールドパッケージおよびその製造方法
JP2015088583A (ja) * 2013-10-30 2015-05-07 京セラサーキットソリューションズ株式会社 配線基板およびその製造方法
CN104602459A (zh) * 2013-10-30 2015-05-06 京瓷电路科技株式会社 布线基板及其制造方法
JP2022021766A (ja) * 2020-07-22 2022-02-03 キオクシア株式会社 半導体装置
JP7490484B2 (ja) 2020-07-22 2024-05-27 キオクシア株式会社 半導体装置
JP2023067260A (ja) * 2021-10-29 2023-05-16 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP7708643B2 (ja) 2021-10-29 2025-07-15 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US12557222B2 (en) 2021-10-29 2026-02-17 Shinko Electric Industries Co., Ltd. Circuit board, semiconductor device, and method of manufacturing circuit board

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Publication number Publication date
US8508050B2 (en) 2013-08-13
US20110316170A1 (en) 2011-12-29

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