JP2012004556A - 半導体装置及び半導体装置の駆動方法 - Google Patents
半導体装置及び半導体装置の駆動方法 Download PDFInfo
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- JP2012004556A JP2012004556A JP2011112124A JP2011112124A JP2012004556A JP 2012004556 A JP2012004556 A JP 2012004556A JP 2011112124 A JP2011112124 A JP 2011112124A JP 2011112124 A JP2011112124 A JP 2011112124A JP 2012004556 A JP2012004556 A JP 2012004556A
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- oxide semiconductor
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
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- G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
【解決手段】バックゲート電極を有する読み出し用トランジスタと、書き込み用トランジスタと、を有する多値型メモリセルを用いる。情報の書き込みは、書き込み用トランジスタをオン状態とすることにより、書き込み用トランジスタのソース電極またはドレイン電極の一方と、読み出し用トランジスタのゲート電極が電気的に接続されたノードに、情報に応じた電位を供給し、その後、書き込み用トランジスタをオフ状態とすることにより、ノードに所定の電位を保持させる。情報の読み出しは、読み出し用トランジスタのソース電極またはドレイン電極の一方と接続された制御信号線に、読み出し制御電位を供給し、その後、読み出し信号線の電位変化を検出することで行う。
【選択図】図1
Description
本実施の形態では、開示する発明の一態様に係る半導体装置の回路構成およびその動作について、図1乃至図2を参照して説明する。本実施の形態では、電子を多数キャリアとするn型トランジスタ(nチャネル型トランジスタ)をトランジスタとして用いる場合について説明する。
本実施の形態では、図3および図4を用いて、実施の形態1に示した半導体装置をm×n個配置して、記憶容量を増加させた半導体装置の回路図の一例を示す。図3は、メモリセル1200が並列に接続された、いわゆるNOR型の半導体装置の回路図である。
本実施の形態では、本明細書に開示する半導体装置に用いることができるトランジスタとその作製方法について、図5及び図7を用いて説明する。本実施の形態では、トランジスタの一例として、チャネルが形成される半導体層に酸化物半導体を用いたトランジスタについて詳細に説明する。
本実施の形態では、実施の形態3に示したトランジスタとは異なる構成のトランジスタについて説明する。なお、上記実施の形態と同一部分又は同様な機能を有する部分、及び工程は、上記実施の形態と同様に行うことができ、本実施の形態での繰り返しの説明は省略する。なお、同じ箇所の詳細な説明も省略する。
本実施の形態では、上述の実施の形態で説明した半導体装置を電子機器に適用する場合について、図8を用いて説明する。本実施の形態では、コンピュータ、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯情報端末(携帯型ゲーム機、音響再生装置なども含む)、デジタルカメラ、デジタルビデオカメラ、電子ペーパー、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)などの電子機器に、上述の半導体装置を適用する場合について説明する。
201 第1のトランジスタ
202 第2のトランジスタ
203 バックゲート電極
211 第1の配線
212 第2の配線
213 第3の配線
214 第4の配線
215 第5の配線
220 容量素子
250 メモリセル
281 ノード
301 処理
302 処理
303 判断
304 処理
305 判断
306 処理
307 判断
311 処理
312 処理
313 処理
314 処理
400 基板
401 ゲート電極
402 ゲート絶縁層
403 酸化物半導体層
405a ソース電極
405b ドレイン電極
406 チャネル保護層
407 絶縁層
409 保護絶縁層
410 トランジスタ
411 バックゲート電極
420 レジストマスク
430 酸素
436 下地層
441 酸化物半導体層
450 トランジスタ
460 トランジスタ
470 トランジスタ
701 筐体
702 筐体
703 表示部
704 キーボード
711 本体
712 スタイラス
713 表示部
714 操作ボタン
715 外部インターフェイス
720 電子書籍
721 筐体
723 筐体
725 表示部
727 表示部
731 電源
733 操作キー
735 スピーカー
737 軸部
740 筐体
741 筐体
742 表示パネル
743 スピーカー
744 マイクロフォン
745 操作キー
746 ポインティングデバイス
747 カメラ用レンズ
748 外部接続端子
749 太陽電池セル
750 外部メモリスロット
761 本体
763 接眼部
764 操作スイッチ
765 表示部
766 バッテリー
767 表示部
770 テレビジョン装置
771 筐体
773 表示部
775 スタンド
780 リモコン操作機
1200 メモリセル
1201 第1のトランジスタ
1202 第2のトランジスタ
1203 バックゲート電極
1211 第1の駆動回路
1212 第2の駆動回路
1213 第3の駆動回路
1214 第4の駆動回路
1300 メモリセルアレイ
Claims (11)
- 第1のトランジスタと、第2のトランジスタと、を有するメモリセルと、第1の配線と、第2の配線と、第3の配線と、第4の配線と、を有し、
前記第1のトランジスタのソース電極またはドレイン電極の一方は、前記第1の配線に電気的に接続され、
前記第1のトランジスタのソース電極またはドレイン電極の他方は、前記第4の配線に電気的に接続され、
前記第2のトランジスタのソース電極またはドレイン電極の一方と、前記第1のトランジスタのゲート電極は電気的に接続され、
前記第2のトランジスタのソース電極またはドレイン電極の他方は、前記第2の配線に電気的に接続され、
前記第2のトランジスタのゲート電極は、前記第3の配線と電気的に接続され、
前記第1のトランジスタはバックゲート電極を有していることを特徴とする半導体装置。 - 請求項1において、
前記メモリセルは容量素子を有し、
前記容量素子は、前記第1のトランジスタのゲート電極に電気的に接続されていることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記バックゲート電極は、前記第1の配線に電気的に接続されていることを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第2のトランジスタは、酸化物半導体を有することを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一項において、
前記第1のトランジスタは、酸化物半導体を有することを特徴とする半導体装置。 - 第1のトランジスタと、第2のトランジスタを有し、前記第2のトランジスタのソース電極またはドレイン電極の一方と、前記第1のトランジスタのゲート電極が電気的に接続され、前記第2のトランジスタのソース電極またはドレイン電極の他方と電気的に接続されたビット線を有する半導体装置の駆動方法であって、
前記第2のトランジスタをオン状態として、前記ビット線に供給された電位を前記第1のトランジスタのゲート電極に供給し、その後、前記第2のトランジスタをオフ状態とすることにより、前記第1のトランジスタのゲート電極の電位を保持することを特徴とする半導体装置の駆動方法。 - 請求項6において、
前記第1のトランジスタのゲート電極に保持される前記電位は、複数の異なる電位のうちの1つであることを特徴とする半導体装置の駆動方法。 - 請求項6乃至請求項7において、
前記第1のトランジスタのゲート電極に保持される前記電位は、前記第1のトランジスタをオフ状態とする電位であることを特徴とする半導体装置の駆動方法。 - 請求項7において、
前記複数の異なる電位の電位差は、前記第1のトランジスタのしきい値ばらつきの標準偏差の2倍以上であることを特徴とする半導体装置の駆動方法。 - バックゲート電極を有する第1のトランジスタと、前記第1のトランジスタのソース電極またはドレイン電極の一方と電気的に接続する制御信号線を有し、
前記第1のトランジスタのソース電極またはドレイン電極の他方と電気的に接続する読み出し信号線を有する半導体装置の駆動方法であって、
前記制御信号線に読み出し制御電位を供給して、前記読み出し信号線の電位変化を検出することを特徴とする半導体装置の駆動方法。 - 請求項10において、
前記読み出し制御電位は、複数の異なる電位を有し、前記制御信号線への前記複数の異なる電位を有する読み出し制御電位の供給は、前記複数の異なる電位のうち絶対値が小さい電位から順に行うことを特徴とする半導体装置の駆動方法。
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JP2017016730A (ja) | 2017-01-19 |
JP2015130512A (ja) | 2015-07-16 |
JP6025292B2 (ja) | 2016-11-16 |
JP5845366B2 (ja) | 2016-01-20 |
TW201220479A (en) | 2012-05-16 |
WO2011145738A1 (en) | 2011-11-24 |
JP5690210B2 (ja) | 2015-03-25 |
TWI527198B (zh) | 2016-03-21 |
US8588000B2 (en) | 2013-11-19 |
TWI611562B (zh) | 2018-01-11 |
US20140071768A1 (en) | 2014-03-13 |
US9734914B2 (en) | 2017-08-15 |
US20110286256A1 (en) | 2011-11-24 |
JP2016076717A (ja) | 2016-05-12 |
TW201628167A (zh) | 2016-08-01 |
US10037808B2 (en) | 2018-07-31 |
TW201721844A (zh) | 2017-06-16 |
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JP6267766B2 (ja) | 2018-01-24 |
US20170358363A1 (en) | 2017-12-14 |
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