JP2011187742A - 半導体素子搭載用基板及びその製造方法 - Google Patents
半導体素子搭載用基板及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 142
- 239000000758 substrate Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 85
- 239000002184 metal Substances 0.000 claims abstract description 85
- 230000001681 protective effect Effects 0.000 claims abstract description 7
- 238000007747 plating Methods 0.000 claims description 146
- 238000000034 method Methods 0.000 claims description 69
- 238000005530 etching Methods 0.000 claims description 64
- 239000000463 material Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 12
- 238000007789 sealing Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
【解決手段】金属板10の両面に、所定形状のめっき層20、21が形成された半導体素子搭載用基板50であって、
前記めっき層は、前記金属基板の表面に形成された凹部12内に、該凹部の深さよりも薄い厚さで形成された保護めっき層20を含むことを特徴とする。
【選択図】図1
Description
前記めっき層は、前記金属基板の表面に形成された凹部内に、該凹部の深さよりも薄い厚さで形成された保護めっき層を含むことを特徴とする。
前記保護めっき層は、前記金属板の一方の面に形成され、
他方の面は、前記金属板の加工が施されていない部分に前記めっき層が形成されたことを特徴とする。
前記他方の面は、半導体素子が搭載される面であり、
前記一方の面は、裏面であることを特徴とする。
前記金属板の両面に、所定形状のめっき層を形成するためのレジストマスクを形成するレジストマスク形成工程と、
前記金属板の一方の面に、エッチング加工により、該金属板の該レジストマスクから露出している部分に凹部を形成するエッチング工程と、
該凹部内に、該凹部の深さよりも薄い厚さでめっき層を形成する第1めっき工程と、
前記金属板の他方の面に、めっき層を形成する第2めっき工程と、を含むことを特徴とする。
前記レジストマスクは、前記エッチング工程及び前記めっき工程の双方に用いることを特徴とする。
前記エッチング工程は、半導体素子が搭載されない裏面に対して行われることを特徴とする。
前記第1めっき工程及び前記第2めっき工程は、同時に行われることを特徴とする。
前記第1めっき工程及び前記第2めっき工程の後、前記レジストマスクを除去するレジストマスク除去工程と、
半導体素子が搭載される表面側のめっき層を覆うレジストマスクと、前記裏面全体を覆うレジストマスクを形成する第2のレジストマスク形成工程と、
前記表面側をハーフエッチング加工するハーフエッチング工程と、を更に有することを特徴とする。
これにより、表面側には、半導体素子が搭載され易く、ワイヤボンディングの行い易い段差を形成することができ、半導体素子搭載機能は従来通りの水準を維持することができる。
前記表面側のめっき層を覆う前記レジストマスクは、前記めっき層よりも広い領域を覆うように形成することを特徴とする。
11、13 表面
11a 平坦部
12 凹部
13a 端子領域
14 半導体素子搭載領域
15 端子部
16 半導体素子搭載部
20 めっき層(保護めっき層)
21 めっき層
30 半導体素子搭載用基板
40、41、42、43 レジストマスク
50 半導体素子
51 半導体素子の電極
52 半導体素子の下面
53 半導体素子の電極形成面
60 ワイヤ
70 封止樹脂
Claims (9)
- 金属板の両面に、所定形状のめっき層が形成された半導体素子搭載用基板であって、
前記めっき層は、前記金属基板の表面に形成された凹部内に、該凹部の深さよりも薄い厚さで形成された保護めっき層を含むことを特徴とする半導体素子搭載用基板。 - 前記保護めっき層は、前記金属板の一方の面に形成され、
他方の面は、前記金属板の加工が施されていない部分に前記めっき層が形成されたことを特徴とする請求項1に記載の半導体素子搭載用基板。 - 前記他方の面は、半導体素子が搭載される面であり、
前記一方の面は、裏面であることを特徴とする請求項2に記載の半導体素子用基板。 - 金属板の両面に、所定形状のめっき層が形成された半導体素子搭載用基板の製造方法であって、
前記金属板の両面に、所定形状のめっき層を形成するためのレジストマスクを形成するレジストマスク形成工程と、
前記金属板の一方の面に、エッチング加工により、該金属板の該レジストマスクから露出している部分に凹部を形成するエッチング工程と、
該凹部内に、該凹部の深さよりも薄い厚さでめっき層を形成する第1めっき工程と、
前記金属板の他方の面に、めっき層を形成する第2めっき工程と、を含むことを特徴とする半導体素子搭載用基板の製造方法。 - 前記レジストマスクは、前記エッチング工程及び前記めっき工程の双方に用いることを特徴とする請求項4に記載の半導体素子搭載用基板の製造方法。
- 前記エッチング工程は、半導体素子が搭載されない裏面に対して行われることを特徴とする請求項5に記載の半導体素子搭載用基板の製造方法。
- 前記第1めっき工程及び前記第2めっき工程は、同時に行われることを特徴とする請求項6に記載の半導体素子搭載用基板の製造方法。
- 前記第1めっき工程及び前記第2めっき工程の後、前記レジストマスクを除去するレジストマスク除去工程と、
半導体素子が搭載される表面側のめっき層を覆うレジストマスクと、前記裏面全体を覆うレジストマスクを形成する第2のレジストマスク形成工程と、
前記表面側をハーフエッチング加工するハーフエッチング工程と、を更に有することを特徴とする請求項7に記載の半導体素子搭載用基板の製造方法。 - 前記表面側のめっき層を覆う前記レジストマスクは、前記めっき層よりも広い領域を覆うように形成することを特徴とする請求項8に記載の半導体装置搭載用基板の製造方法。
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KR1020110019018A KR101307030B1 (ko) | 2010-03-09 | 2011-03-03 | 반도체 소자 탑재용 기판 및 그 제조 방법 |
CN201110054138.6A CN102194763B (zh) | 2010-03-09 | 2011-03-04 | 半导体元件搭载用基板的制造方法 |
TW100107258A TWI500122B (zh) | 2010-03-09 | 2011-03-04 | 半導體元件搭載用基板及其製造方法 |
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Cited By (4)
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JP2014027266A (ja) * | 2012-06-20 | 2014-02-06 | Asahi Kasei Electronics Co Ltd | 半導体パッケージおよびその製造方法 |
JPWO2013114985A1 (ja) * | 2012-02-01 | 2015-05-11 | 株式会社パイオラックスメディカルデバイス | ガイドワイヤ |
JP2017112141A (ja) * | 2015-12-14 | 2017-06-22 | Shマテリアル株式会社 | 半導体素子搭載用リードフレーム及びその製造方法 |
JP7408886B2 (ja) | 2020-03-31 | 2024-01-09 | 長華科技股▲ふん▼有限公司 | 半導体素子搭載用基板 |
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TWI427839B (zh) * | 2010-12-03 | 2014-02-21 | Ind Tech Res Inst | 薄膜圖案的沉積裝置與方法 |
JP5878054B2 (ja) * | 2012-03-27 | 2016-03-08 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法及び半導体装置 |
JP6044936B2 (ja) * | 2013-04-24 | 2016-12-14 | Shマテリアル株式会社 | 半導体素子搭載用基板の製造方法 |
JP6792106B2 (ja) * | 2017-03-30 | 2020-11-25 | スピードファム株式会社 | ワークキャリア及びワークキャリアの製造方法 |
JP6863846B2 (ja) * | 2017-07-19 | 2021-04-21 | 大口マテリアル株式会社 | 半導体素子搭載用基板及びその製造方法 |
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JPH10242367A (ja) * | 1997-02-25 | 1998-09-11 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2000100843A (ja) * | 1998-09-17 | 2000-04-07 | Mitsubishi Electric Corp | 半導体パッケージおよびその製造方法 |
JP2000260897A (ja) * | 1999-03-10 | 2000-09-22 | Shinko Electric Ind Co Ltd | 半導体装置用キャリア基板及びその製造方法及び半導体装置の製造方法 |
JP2001358254A (ja) * | 2000-06-15 | 2001-12-26 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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JPS62286260A (ja) * | 1986-06-04 | 1987-12-12 | Oki Electric Ind Co Ltd | 半導体装置の基板接続構造 |
KR101095527B1 (ko) * | 2009-11-04 | 2011-12-19 | 엘지이노텍 주식회사 | 리드 프레임 및 그 제조 방법 |
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JPH10242367A (ja) * | 1997-02-25 | 1998-09-11 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2000100843A (ja) * | 1998-09-17 | 2000-04-07 | Mitsubishi Electric Corp | 半導体パッケージおよびその製造方法 |
JP2000260897A (ja) * | 1999-03-10 | 2000-09-22 | Shinko Electric Ind Co Ltd | 半導体装置用キャリア基板及びその製造方法及び半導体装置の製造方法 |
JP2001358254A (ja) * | 2000-06-15 | 2001-12-26 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Cited By (4)
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JPWO2013114985A1 (ja) * | 2012-02-01 | 2015-05-11 | 株式会社パイオラックスメディカルデバイス | ガイドワイヤ |
JP2014027266A (ja) * | 2012-06-20 | 2014-02-06 | Asahi Kasei Electronics Co Ltd | 半導体パッケージおよびその製造方法 |
JP2017112141A (ja) * | 2015-12-14 | 2017-06-22 | Shマテリアル株式会社 | 半導体素子搭載用リードフレーム及びその製造方法 |
JP7408886B2 (ja) | 2020-03-31 | 2024-01-09 | 長華科技股▲ふん▼有限公司 | 半導体素子搭載用基板 |
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JP5578704B2 (ja) | 2014-08-27 |
CN102194763B (zh) | 2015-09-23 |
TW201145476A (en) | 2011-12-16 |
CN102194763A (zh) | 2011-09-21 |
KR20110102181A (ko) | 2011-09-16 |
KR101307030B1 (ko) | 2013-09-11 |
TWI500122B (zh) | 2015-09-11 |
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