JP2010278318A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2010278318A
JP2010278318A JP2009130804A JP2009130804A JP2010278318A JP 2010278318 A JP2010278318 A JP 2010278318A JP 2009130804 A JP2009130804 A JP 2009130804A JP 2009130804 A JP2009130804 A JP 2009130804A JP 2010278318 A JP2010278318 A JP 2010278318A
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JP
Japan
Prior art keywords
pads
row
pad
wiring
main surface
Prior art date
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Pending
Application number
JP2009130804A
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English (en)
Japanese (ja)
Other versions
JP2010278318A5 (OSRAM
Inventor
Naoto Taoka
直人 田岡
Atsushi Nakamura
篤 中村
Naozumi Morino
直純 森野
Tomokazu Ishikawa
智和 石川
Yoshihiro Kinoshita
順弘 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009130804A priority Critical patent/JP2010278318A/ja
Priority to US12/785,488 priority patent/US8698296B2/en
Publication of JP2010278318A publication Critical patent/JP2010278318A/ja
Publication of JP2010278318A5 publication Critical patent/JP2010278318A5/ja
Priority to US14/204,988 priority patent/US8975120B2/en
Pending legal-status Critical Current

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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
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    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
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    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
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    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
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    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
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    • H10W72/07231—Techniques
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    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/261—Functions other than electrical connecting
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    • H10W72/29—Bond pads specially adapted therefor
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    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
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    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
JP2009130804A 2009-05-29 2009-05-29 半導体装置 Pending JP2010278318A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009130804A JP2010278318A (ja) 2009-05-29 2009-05-29 半導体装置
US12/785,488 US8698296B2 (en) 2009-05-29 2010-05-24 Semiconductor device
US14/204,988 US8975120B2 (en) 2009-05-29 2014-03-11 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009130804A JP2010278318A (ja) 2009-05-29 2009-05-29 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013264540A Division JP5770258B2 (ja) 2013-12-20 2013-12-20 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2010278318A true JP2010278318A (ja) 2010-12-09
JP2010278318A5 JP2010278318A5 (OSRAM) 2012-04-05

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JP2009130804A Pending JP2010278318A (ja) 2009-05-29 2009-05-29 半導体装置

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US (2) US8698296B2 (OSRAM)
JP (1) JP2010278318A (OSRAM)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013115205A (ja) * 2011-11-28 2013-06-10 Shinko Electric Ind Co Ltd 半導体装置の製造方法、半導体装置、及び半導体素子
JP2014127706A (ja) * 2012-12-27 2014-07-07 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
KR20150120617A (ko) * 2014-04-18 2015-10-28 에스케이하이닉스 주식회사 반도체 칩 적층 패키지
JP2015228511A (ja) * 2015-08-03 2015-12-17 ルネサスエレクトロニクス株式会社 半導体装置
US9818678B2 (en) 2011-06-30 2017-11-14 Renesas Electronics Corporation Semiconductor device
JP2020115592A (ja) * 2014-04-10 2020-07-30 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 電子部品
US11457531B2 (en) 2013-04-29 2022-09-27 Samsung Display Co., Ltd. Electronic component, electric device including the same, and bonding method thereof
JP2024530373A (ja) * 2022-07-08 2024-08-21 チャンシン メモリー テクノロジーズ インコーポレイテッド 半導体パッケージアセンブリ及び製造方法
JP2024530371A (ja) * 2022-07-08 2024-08-21 チャンシン メモリー テクノロジーズ インコーポレイテッド 半導体パッケージアセンブリ及び製造方法

Families Citing this family (51)

* Cited by examiner, † Cited by third party
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JP5207868B2 (ja) * 2008-02-08 2013-06-12 ルネサスエレクトロニクス株式会社 半導体装置
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