JP2010182368A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Abstract
【解決手段】単一のチップダイにおいて入出力される信号数に対応した数のビアだけでなく、積層されるべきチップダイにおいて入出力される信号数にも対応した数のビアと、前記各ビアに対する入出力を制御するスイッチを、各チップダイに備えた半導体装置が得られる。各スイッチの導通、非導通をROMによって制御することにより、積層される複数のチップダイからの信号を並列に出力することができ、各チップダイにおけるデータ転送速度をシステムの転送速度に合わせて高速化する必要がなくなる。
【選択図】 図1
Description
211〜217 第1〜第8のチップダイ
230 メモリセルアレイ
V1000〜V1317 ビア
1000〜1317 スイッチ
2500〜2531 IO回路
2700〜2731 ROM
30 インタフェース回路
D0〜D31 チップダイ
SW−2 第2のスイッチ
42 ESD保護回路
44 プローピングパッド
46 不揮発性素子
48 第3のスイッチ
50、52 インバータ
Claims (23)
- 半導体基板を貫通する複数の電極と、
前記電極にそれぞれ接続されたスイッチと、
複数の前記スイッチに共通に接続された第1の信号線と、
前記第1の信号線に接続された第1の回路と、を備え、
複数の前記スイッチのいずれか一つのみが選択的に導通する、ことを特徴とする半導体装置。 - 請求項1において、前記スイッチを選択的に導通させるROMを備えることを特徴とする半導体装置。
- 請求項2において、前記ROMは、当該半導体装置の少なくともデータ信号の属するグループに関連して設定されていることを特徴とする半導体装置。
- 請求項1〜3のいずれかにおいて、更に、複数の前記第1の信号線を、一つの前記第1の回路に接続する第2のスイッチを備えていることを特徴とする半導体装置。
- 請求項1〜4のいずれかにおいて、更に、前記第1の信号線は、プローピングの際にのみ使用されるプロービング用端子を備えることを特徴とする半導体装置。
- 請求項5において、前記第1の信号線及び前記複数の電極のいずれか一方に接続されたESD保護回路を備えていることを特徴とする半導体装置。
- 請求項1において、前記複数の電極に、それぞれ接続されたESD保護回路と、前記スイッチと前記ROMとの間に設けられた第3のスイッチとラッチ回路を備え、前記第3のスイッチは試験信号によって導通状態になると共に、前記試験信号の活性化により、複数の前記ESD回路が前記第1の信号線に接続されることを特徴とする半導体装置。
- 請求項1において、前記第1の回路の動作電源の電圧は、積層される前記半導体装置の枚数値によって変更できることを特徴とする半導体装置。
- 請求項2において、前記第1の回路は、記憶情報を入出力する回路であり、複数の前記電極で複数ビット(I/O)の前記記憶情報を入出力することを特徴とする半導体装置。
- 請求項2において、前記第1の回路は、前記半導体基板を制御する制御信号処理回路であり、複数の前記電極で前記半導体基板を制御することを特徴とする半導体装置。
- 複数の半導体基板を積層した構成を備え、
前記各半導体基板は、
当該半導体基板を貫通する複数の電極と、
前記電極にそれぞれ接続されたスイッチと、
複数の前記スイッチに共通に接続された第1の信号線と、
前記第1の信号線に接続された第1の回路が設けられていると共に、
複数の前記スイッチのいずれか一つのみが選択的に導通するように、構成されており、
積層された前記複数の半導体基板の前記電極は互いに接続されており、
積層された前記各半導体基板の選択的に導通するスイッチは、互いに異なった位置にある、ことを特徴とする半導体装置。 - 請求項11において、前記互いに異なった位置で導通するそれぞれのスイッチに接続される電極は、複数ビット(I/O)の記憶情報を並列に入出力することを特徴とする半導体装置。
- 請求項12において、前記互いに異なった位置で導通するそれぞれのスイッチに接続される電極は、前記各半導体基板の制御信号用の電極であることを特徴とする半導体装置。
- 請求項11〜13のいずれかにおいて、複数の前記半導体基板を制御する第2の半導体基板(コントローラチップ)を備え、
前記互いに接続された複数の半導体基板の電極と、前記第2の半導体基板の電極とが接続されることを特徴とする半導体装置。 - 請求項14において、前記第2の半導体基板の電極は、前記半導体装置の外部電極に接続されることを特徴とする半導体装置。
- 請求項14又は15において、積層され互いに接続された前記電極には、それぞれESD回路が接続されることを特徴とする半導体装置。
- 請求項11において、前記第1の回路には、前記第1の信号線を駆動する複数の出力バッファを備え、更に、積層される前記半導体基板の枚数値によって前記複数の出力バッファを選択的に動作させ、前記第1の回路の駆動能力を変更することを特徴とする半導体装置。
- 請求項11において、前記第1の回路の動作電源の電圧は、積層される前記半導体基板の枚数値によって変更できることを特徴とする半導体装置。
- 予め定められたビット数のデータ信号を並列に入出力するチップダイであって、前記チップダイは、前記予め定められたビット数と、前記チップダイを複数積層した場合における積層数によって定まる数のデータ信号転送用貫通電極と、前記データ信号転送用貫通電極をそれぞれ選択するスイッチとを有することを特徴とするチップダイ。
- 請求項19において、更に、前記チップダイを個別に選択する制御信号用貫通電極を有していることを特徴とするチップダイ。
- 積層された複数のチップダイと、当該複数のチップダイを制御するコントローラとを含み、前記各チップダイは、前記予め定められたビット数と、前記チップダイを複数積層した場合における積層数によって定まる数のデータ信号転送用貫通電極と、前記データ信号転送用貫通電極をそれぞれ選択するスイッチを備え、
前記コントローラは、前記複数のチップダイから前記スイッチによってそれぞれ選択された前記データ信号転送用貫通電極を通して入出力されるデータ信号を変換するパラレルシリアル変換回路を有することを特徴とするシステム。 - 請求項21において、前記コントローラは、前記複数のチップダイと共に積層されたチップに形成されていることを特徴とするシステム。
- 請求項21において、前記コントローラは、前記積層されたチップダイの外部に設けられていることを特徴とするシステム。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009024486A JP5632584B2 (ja) | 2009-02-05 | 2009-02-05 | 半導体装置 |
US12/656,485 US8243486B2 (en) | 2009-02-05 | 2010-02-01 | Semiconductor device |
US13/531,346 US8503261B2 (en) | 2009-02-05 | 2012-06-22 | Semiconductor device |
US14/820,325 USRE47840E1 (en) | 2009-02-05 | 2015-08-06 | Testing circuits in stacked wafers using a connected electrode in the first wafer |
US16/780,767 USRE49390E1 (en) | 2009-02-05 | 2020-02-03 | Testing a circuit in a semiconductor device |
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JP2009024486A JP5632584B2 (ja) | 2009-02-05 | 2009-02-05 | 半導体装置 |
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JP2014207335A Division JP2015029138A (ja) | 2014-10-08 | 2014-10-08 | 半導体装置のテスト方法、および半導体装置の製造方法 |
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JP2010182368A true JP2010182368A (ja) | 2010-08-19 |
JP5632584B2 JP5632584B2 (ja) | 2014-11-26 |
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JP2013536985A (ja) * | 2010-08-31 | 2013-09-26 | マイクロン テクノロジー, インク. | メモリダイのスタック内のバッファダイおよび方法 |
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Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006012337A (ja) * | 2004-06-28 | 2006-01-12 | Nec Corp | 積層型半導体メモリ装置 |
JP2006013337A (ja) * | 2004-06-29 | 2006-01-12 | Nec Corp | 3次元半導体装置 |
US20070047284A1 (en) * | 2005-08-30 | 2007-03-01 | Micron Technology, Inc. | Self-identifying stacked die semiconductor components |
US20070153588A1 (en) * | 2005-12-30 | 2007-07-05 | Janzen Jeffery W | Configurable inputs and outputs for memory stacking system and method |
JP2007293982A (ja) * | 2006-04-24 | 2007-11-08 | Toshiba Corp | 半導体装置及びメモリ回路システム |
JP2008140220A (ja) * | 2006-12-04 | 2008-06-19 | Nec Corp | 半導体装置 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399505A (en) * | 1993-07-23 | 1995-03-21 | Motorola, Inc. | Method and apparatus for performing wafer level testing of integrated circuit dice |
JPH10172298A (ja) * | 1996-12-05 | 1998-06-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
GB9922763D0 (en) * | 1999-09-28 | 1999-11-24 | Koninkl Philips Electronics Nv | Semiconductor devices |
TW587252B (en) * | 2000-01-18 | 2004-05-11 | Hitachi Ltd | Semiconductor memory device and data processing device |
TWI221922B (en) * | 2001-02-19 | 2004-10-11 | Nihon Densan Read Kabushiki Ka | A circuit board testing apparatus and method for testing a circuit board |
US6614235B2 (en) * | 2001-06-06 | 2003-09-02 | Credence Technologies, Inc. | Apparatus and method for detection and measurement of environmental parameters |
JP2003022430A (ja) * | 2001-07-06 | 2003-01-24 | Hitachi Ltd | メモリカード |
JP2003031672A (ja) * | 2001-07-19 | 2003-01-31 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
JP3989756B2 (ja) * | 2002-03-18 | 2007-10-10 | シャープ株式会社 | 表示装置およびその走査回路検査方法 |
US6852627B2 (en) * | 2003-03-05 | 2005-02-08 | Micron Technology, Inc. | Conductive through wafer vias |
JP2004296928A (ja) * | 2003-03-27 | 2004-10-21 | Matsushita Electric Ind Co Ltd | 半導体装置、これを用いたシステムデバイスおよびその製造方法 |
JP4419049B2 (ja) | 2003-04-21 | 2010-02-24 | エルピーダメモリ株式会社 | メモリモジュール及びメモリシステム |
JP4309368B2 (ja) * | 2005-03-30 | 2009-08-05 | エルピーダメモリ株式会社 | 半導体記憶装置 |
US7818698B2 (en) * | 2007-06-29 | 2010-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accurate parasitic capacitance extraction for ultra large scale integrated circuits |
EP2302403A1 (en) * | 2009-09-28 | 2011-03-30 | Imec | Method and device for testing TSVs in a 3D chip stack |
KR20120062281A (ko) * | 2010-12-06 | 2012-06-14 | 삼성전자주식회사 | 관통 전극을 가지는 적층 구조의 반도체 장치 및 이에 대한 테스트 방법 |
US8866488B2 (en) * | 2011-03-22 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power compensation in 3DIC testing |
-
2009
- 2009-02-05 JP JP2009024486A patent/JP5632584B2/ja active Active
-
2010
- 2010-02-01 US US12/656,485 patent/US8243486B2/en active Active
-
2012
- 2012-06-22 US US13/531,346 patent/US8503261B2/en not_active Ceased
-
2015
- 2015-08-06 US US14/820,325 patent/USRE47840E1/en active Active
-
2020
- 2020-02-03 US US16/780,767 patent/USRE49390E1/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006012337A (ja) * | 2004-06-28 | 2006-01-12 | Nec Corp | 積層型半導体メモリ装置 |
JP2006013337A (ja) * | 2004-06-29 | 2006-01-12 | Nec Corp | 3次元半導体装置 |
US20070047284A1 (en) * | 2005-08-30 | 2007-03-01 | Micron Technology, Inc. | Self-identifying stacked die semiconductor components |
US20070153588A1 (en) * | 2005-12-30 | 2007-07-05 | Janzen Jeffery W | Configurable inputs and outputs for memory stacking system and method |
JP2007293982A (ja) * | 2006-04-24 | 2007-11-08 | Toshiba Corp | 半導体装置及びメモリ回路システム |
JP2008140220A (ja) * | 2006-12-04 | 2008-06-19 | Nec Corp | 半導体装置 |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013536985A (ja) * | 2010-08-31 | 2013-09-26 | マイクロン テクノロジー, インク. | メモリダイのスタック内のバッファダイおよび方法 |
US9691444B2 (en) | 2010-08-31 | 2017-06-27 | Micron Technology, Inc. | Buffer die in stacks of memory dies and methods |
JP2012099162A (ja) * | 2010-10-29 | 2012-05-24 | Elpida Memory Inc | 半導体装置 |
US9170302B2 (en) | 2010-11-26 | 2015-10-27 | SK Hynix Inc. | Semiconductor apparatus and test method thereof |
KR101208960B1 (ko) | 2010-11-26 | 2012-12-06 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이의 테스트 방법 |
US8924903B2 (en) | 2010-11-30 | 2014-12-30 | Ps4 Luxco S.A.R.L. | Semiconductor device having plural memory chip |
US9252081B2 (en) | 2010-11-30 | 2016-02-02 | Ps4 Luxco S.A.R.L. | Semiconductor device having plural memory chip |
JP2012119022A (ja) * | 2010-11-30 | 2012-06-21 | Elpida Memory Inc | 半導体装置 |
KR101854251B1 (ko) * | 2010-11-30 | 2018-05-03 | 삼성전자주식회사 | 멀티 채널 반도체 메모리 장치 및 그를 구비하는 반도체 장치 |
JP2012134380A (ja) * | 2010-12-22 | 2012-07-12 | Hitachi Ltd | 半導体装置 |
EP2555237A2 (en) | 2011-08-03 | 2013-02-06 | Elpida Memory, Inc. | Semiconductor device |
US8704339B2 (en) | 2011-08-03 | 2014-04-22 | Tomohiro Kitano | Semiconductor device |
US8860187B2 (en) | 2011-08-03 | 2014-10-14 | Ps4 Luxco S.A.R.L. | Semiconductor device |
WO2016042603A1 (ja) * | 2014-09-17 | 2016-03-24 | 株式会社東芝 | 半導体装置 |
JP2017168868A (ja) * | 2015-01-16 | 2017-09-21 | 雫石 誠 | 半導体素子 |
Also Published As
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US20100195364A1 (en) | 2010-08-05 |
US20120262198A1 (en) | 2012-10-18 |
US8243486B2 (en) | 2012-08-14 |
USRE49390E1 (en) | 2023-01-24 |
USRE47840E1 (en) | 2020-02-04 |
US8503261B2 (en) | 2013-08-06 |
JP5632584B2 (ja) | 2014-11-26 |
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