JP5623259B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5623259B2 JP5623259B2 JP2010273230A JP2010273230A JP5623259B2 JP 5623259 B2 JP5623259 B2 JP 5623259B2 JP 2010273230 A JP2010273230 A JP 2010273230A JP 2010273230 A JP2010273230 A JP 2010273230A JP 5623259 B2 JP5623259 B2 JP 5623259B2
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Description
基板と、前記基板に順に積層された第1の層及び第2の層と、を含むチップと、
前記チップの下面の第1の電極と、
前記チップの上面の第2の電極と、
前記基板に形成された入力ノード及び出力ノードを有する回路と、
前記第1の電極と、前記第1の層が含む第1のノードと、を接続し、前記基板を貫通する第1の配線と、
前記第1のノードと、前記入力ノードと、を接続する前記第1の層が含む第2の配線と、
前記出力ノードと、前記第2の層が含む第2のノードと、を接続する前記第1及び第2の層が含む第3の配線と、を備え、
前記第2のノードは、前記第2の電極に接続され、
前記第1の電極、前記第2の電極、前記第1の配線は、前記チップの積層方向に沿って同一のライン上に配置されている、半導体装置。
更に、前記第1のノードと前記第2のノードは、共に前記ライン上に配置され、かつ当該ライン上において前記第1と第2の層の間の絶縁層を介して電気的に分離されている、付記1の半導体装置。
前記第1の層は、少なくとも一つの第1の配線層を含み、
前記第1の配線層は、前記第1のノードを含み、かつ前記第1の配線の一部である第4の配線、前記第2の配線及び前記第3の配線を含む、付記1または2の半導体装置。
前記第1の層は、更に、第1及び第2のビアを含み、
前記第2の配線と前記入力ノードは、前記第1のビアを介して接続され、
前記第3の配線と前記出力ノードは、前記第2のビアを介して接続される、付記3の半導体装置。
前記第1の層は、更に、前記第1の配線層を前記基板と挟む第2の配線層を含み、
前記第2の配線層は、前記第1のノードを含み、かつ前記第1の配線の一部である第5の配線と、前記第3の配線の一部である第6の配線を含み、
前記第1の層は、更に、第3乃至第5のビアを含み、
前記第4の配線及び前記第5の配線は、前記第3のビアを介して接続され、
前記第2の配線及び前記第5の配線は、前記第4のビアを介して接続され、
前記第3の配線及び前記第6の配線は、前記第5のビアを介して接続される、
付記4の半導体装置。
前記第2の層は、第3の配線層を含み、
前記第3の配線層は、前記第2のノードを含み、かつ前記第3の配線の一部である第7の配線を含み、
前記第7の配線は、前記第2の電極に接続される、付記1または2の半導体装置。
前記第2の層は、更に、前記第3の配線層を前記第2の電極と挟む第4の配線層と、第6のビアを含み、
前記第4の配線層は、前記第2のノードを含み、かつ前記第1の配線の一部である第8の配線を含み、
前記第8の配線は、前記第6のビアを介して前記第7の配線と接続される、付記6の半導体装置。
前記第2の層は、更に、第7のビアを含み、
前記第8の配線及び前記出力ノードは、前記第7のビアを介して接続される、付記7の半導体装置。
前記第2の層は、更に、第7のビアを含み、
前記第7の配線及び前記出力ノードは、前記第7のビアを介して接続される、付記6の半導体装置。
前記第2の層は、第3の配線層と、第7のビアを含み、
前記第3の配線層は、前記第2のノードを含み、かつ前記第3の配線の一部である第7の配線を含み、
前記第7の配線及び前記第6の配線は、前記第7のビアを介して接続される、付記5の半導体装置。
前記第2の層は、第3の配線層を含み、
前記第3の配線層は、前記第2のノードを含み、かつ前記第3の配線の一部である第7の配線を含み、
前記第7の配線は、前記第2の電極に接続される、付記5の半導体装置。
前記第2の層は、更に、前記第3の配線層を前記第2の電極と挟む第4の配線層と、第6のビアを含み、
前記第4の配線層は、前記第2のノードを含み、かつ前記第1の配線の一部である第8の配線を含み、
前記第8の配線は、前記第6のビアを介して前記第7の配線と接続される、付記11の半導体装置。
前記第2の層は、更に、第7のビアを含み、
前記第8の配線及び前記第6の配線は、前記第7のビアを介して接続される、付記12の半導体装置。
前記回路は、トランジスタを含み、
前記入力ノード及び前記出力ノードは、前記トランジスタの入力電極及び出力電極である、付記1乃至13のいずれか一項の半導体装置。
前記トランジスタは、制御信号によって制御され、前記入力ノードに供給される入力信号を前記出力ノードへ転送する転送トランジスタである、付記14の半導体装置。
前記第1、第2及び第3の配線は、金属で形成された導電体である、付記1乃至15のいずれか一項の半導体装置。
111 第1のスイッチ部
112 信号経路部
113 第2のスイッチ部
114 記憶部
115 スイッチ制御部
21 論理LSIチップ
211 クロックジェネレーター
212 論理制御回路
213 DLL回路
214 入出力回路
22,22−1 SDRAMチップ
221 入力回路
222 コマンドデコーダ
223 アドレスバッファ
224 DLL回路
225 パラレル−シリアル変換回路及び入出力回路
226 Xデコーダ
227 Yデコーダ
228 DRAMアレイ
31 第1のスイッチ
32 第2のスイッチ
33 RAM
34 レジスタ
35 AND回路
51 Si基板
511 TSV
512 TSVトレンチ
513 STI
514 不純物拡散層
52 第1の配線層
521,522 配線
523,524 ビア
53 第2の配線層
531,532 配線
533 ビア
54 保護層
55 裏面バンプ
56 表面バンプ
57 ビア
1001 8ビットデコーダ
1101 RAM
1102 スイッチ
1103 排他的論理和(EXOR)回路
1104 NOT回路
Claims (13)
- 直列に多段接続された複数の半導体チップと、前記複数の半導体チップの一つにクロック信号及び識別信号を供給するコントローラチップと、を備え、
前記複数の半導体チップの各々は、
前記コントローラチップ又は前段の半導体チップから供給されるクロック信号を後段の半導体チップへ伝送する第1のスイッチ部と、
前記コントローラチップ又は前記前段の半導体チップから供給される識別信号を前記後段の半導体チップへ伝送する信号経路部と、
前記信号経路部に接続される第2のスイッチ部と、
前記第2のスイッチ部を介して前記識別信号を識別情報として記憶する記憶部と、
前記クロック信号に基づいて前記第1のスイッチ部及び前記第2のスイッチ部のそれぞれの電気的な導通論理を、互いに排他的に制御するスイッチ制御部と、
を含む、ことを特徴とする半導体装置。 - 前記スイッチ制御部は、前記記憶部に前記識別情報が記憶されるまで、前記第1のスイッチ部を非導通状態にするとともに前記第2のスイッチ部を導通状態にし、前記記憶部に前記識別情報が記憶された後、前記第1のスイッチ部を導通状態にするとともに前記第2のスイッチ部を非導通状態にする、ことを特徴とする請求項1に記載の半導体装置。
- 前記スイッチ制御部は、
第1の制御信号を出力し、前記クロック信号のN(N:自然数)番目のパルスに基づいて前記第1の制御信号の論理レベルを変化させるレジスタと、
前記第1の制御信号の論理反転信号と前記クロック信号との論理積を第2の制御信号として出力するアンド回路と、を含み、
前記第1の制御信号を用いて前記第1のスイッチ部を制御し、前記第2の制御信号を用いて前記第2のスイッチ部を制御する、ことを特徴とする請求項1または2に記載の半導体装置。 - 前記信号経路部は、複数の信号経路を含み、
前記第2のスイッチ部は、前記複数の信号経路にそれぞれ接続された複数のスイッチを含み、
前記記憶部は、前記複数のスイッチにそれぞれ接続された複数のメモリセルを含む、ことを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。 - 前記複数の信号経路、前記複数のスイッチ、及び前記複数のメモリセルの数は、前記複数の半導体チップの数よりも少ない、ことを特徴とする請求項4に記載の半導体装置。
- 前記複数の半導体チップの数が2M(M:自然数)のとき、前記複数の信号経路、前記複数のスイッチ、及び前記複数のメモリセルの数が、それぞれMである、ことを特徴とする請求項5に記載の半導体装置。
- 前記識別信号が、前記複数の半導体チップにそれぞれ対応した互いに異なる識別番号を表す識別番号信号を含む、ことを特徴とする請求項4に記載の半導体装置。
- 前記識別信号が、更に、前記複数の半導体チップを活性化させるチップ選択制御信号のチップ識別番号を含む、ことを特徴とする請求項7に記載の半導体装置。
- 直列に多段接続された複数の半導体チップを備える半導体装置の制御方法において、
前記複数の半導体チップの各々は、
識別信号が供給されると当該識別信号を後段の半導体チップへ伝送し、
クロック信号のn番目のパルスに基づいて、前記識別信号が表す識別情報を記憶部に書き込み、
当該書き込みが終了するまで前記クロック信号の後段の半導体チップへの伝送を阻止し、
前記記憶部への書き込みが終了した後、前記クロック信号の後段の半導体チップへ伝送を許容する、
ことを特徴とする半導体装置の制御方法。 - 前記識別信号が、前記複数の半導体チップにそれぞれ対応した互いに異なる識別番号を表す識別番号信号を含む、ことを特徴とする請求項9に記載の半導体装置の制御方法。
- 前記識別信号が、更に、前記複数の半導体チップを活性化させるチップ選択制御信号のチップ識別番号を含む、ことを特徴とする請求項10に記載の半導体装置の制御方法。
- 前記半導体装置は、コントローラチップを備え、
前記コントローラチップは、前記クロック信号を生成し、前記複数の半導体チップの一つに供給し、前記識別信号を生成し、前記複数の半導体チップの一つに供給する、ことを特徴とする請求項9乃至11のいずれか一項に記載の半導体装置の制御方法。 - 識別信号及びクロック信号を前段から後段へ伝送するように直列に多段接続された複数の半導体チップを備える半導体装置の制御方法において、
前記複数の半導体チップの各々は、
識別信号が供給されると当該識別信号を後段の半導体チップへ伝送し、
クロック信号が供給されると、前記識別信号が表す識別情報を記憶部に書き込み、
当該書き込みが終了するまで前記クロック信号の後段の半導体チップへの伝送を阻止し、
前記記憶部への書き込みが終了した後、前記クロック信号の後段の半導体チップへの伝送を許容し、
これによって、第n段(n:自然数)の半導体チップが前記クロック信号のn番目のパルスに基づいて前記識別信号を前記記憶部に書き込むようにした
ことを特徴とする半導体装置の制御方法。
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JP2010273230A JP5623259B2 (ja) | 2010-12-08 | 2010-12-08 | 半導体装置 |
US13/311,392 US8788738B2 (en) | 2010-12-08 | 2011-12-05 | Semiconductor device and method of manufacturing the same |
US14/330,223 US8938570B2 (en) | 2010-12-08 | 2014-07-14 | Semiconductor device and method of manufacturing the same |
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US9478502B2 (en) * | 2012-07-26 | 2016-10-25 | Micron Technology, Inc. | Device identification assignment and total device number detection |
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KR102342740B1 (ko) * | 2014-09-15 | 2021-12-23 | 삼성전자주식회사 | 신호 송수신 방법 및 장치 |
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JP6658033B2 (ja) * | 2016-02-05 | 2020-03-04 | 富士通株式会社 | 演算処理回路、および情報処理装置 |
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US7308524B2 (en) * | 2003-01-13 | 2007-12-11 | Silicon Pipe, Inc | Memory chain |
JP4507563B2 (ja) * | 2003-11-10 | 2010-07-21 | 株式会社日立製作所 | マルチプロセッサシステム |
US7456384B2 (en) * | 2004-12-10 | 2008-11-25 | Sony Corporation | Method and apparatus for acquiring physical information, method for manufacturing semiconductor device including array of plurality of unit components for detecting physical quantity distribution, light-receiving device and manufacturing method therefor, and solid-state imaging device and manufacturing method therefor |
JP4799157B2 (ja) | 2005-12-06 | 2011-10-26 | エルピーダメモリ株式会社 | 積層型半導体装置 |
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US8266476B2 (en) * | 2006-11-09 | 2012-09-11 | Sony Computer Entertainment Inc. | Multiprocessor system, its control method, and information recording medium |
US8984249B2 (en) * | 2006-12-20 | 2015-03-17 | Novachips Canada Inc. | ID generation apparatus and method for serially interconnected devices |
JP5426311B2 (ja) * | 2009-10-14 | 2014-02-26 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
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US8938570B2 (en) | 2015-01-20 |
US20140321223A1 (en) | 2014-10-30 |
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US20120146707A1 (en) | 2012-06-14 |
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