JP2010093235A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP2010093235A JP2010093235A JP2009191749A JP2009191749A JP2010093235A JP 2010093235 A JP2010093235 A JP 2010093235A JP 2009191749 A JP2009191749 A JP 2009191749A JP 2009191749 A JP2009191749 A JP 2009191749A JP 2010093235 A JP2010093235 A JP 2010093235A
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Abstract
【解決手段】半導体装置100は、SiOCH膜10の表層が改質されることにより形成された、SiOCH膜10よりも炭素濃度が低くかつSiOCH膜10よりも酸素濃度が高い表面改質層20が設けられるとともに、Cu配線50の表面及び表面改質層20の表面に接するキャップ絶縁膜60を有している。このため、SiOCH膜10全体の誘電率の上昇を低減しつつ、CMPプロセスにおいて親水性の表面改質層20が露出することによって水滴が残りにくくなり、CMPプロセス後のパーティクルの残留やウォーターマークの発生を低減できる。
【選択図】図1
Description
以下に、一般的なCu配線の製造方法について、図10、11を用いて説明する。
半導体基板と、
前記半導体基板上に設けられたSiOCH膜からなる第一絶縁膜と、
前記第一絶縁膜の表層を改質することにより形成された、前記第一絶縁膜よりも炭素濃度が低くかつ前記第一絶縁膜よりも酸素濃度が高い表面改質層と、
前記表面改質層及び前記第一絶縁膜に形成された凹部内に埋設された金属配線と、
前記金属配線の表面及び前記表面改質層の表面に接する第二絶縁膜と、
を含むことを特徴とする。
さらに、表面改質層は、第一絶縁膜よりも、炭素濃度が低くかつ酸素濃度が高くなっているため、親水性である。このため、CMPプロセスにおいて表面改質層が露出することによって水滴が残りにくくなり、CMPプロセス後のパーティクルの残留やウォーターマークの発生を低減できる。
半導体基板上にSiOCH膜からなる第一絶縁膜を形成する工程と、
不活性ガスを用いたプラズマ処理を施し、前記第一絶縁膜の表層に表面改質層を形成する工程と、
前記表面改質層上にハードマスクを形成する工程と、
前記ハードマスクおよび前記第一絶縁膜に、前記ハードマスクおよび前記表面改質層を貫通する凹部を形成する工程と、
前記凹部内を埋め込むように金属配線を形成する工程と、
前記凹部の外部に露出した前記金属配線を除去し、かつ前記ハードマスクを除去して前記表面改質層を露出する工程と、
露出された前記表面改質層、および前記金属配線の表面に第二絶縁膜を形成する工程と、
を含むことを特徴とする。
さらに、表面改質層は、第一絶縁膜よりも、炭素濃度が低くかつ酸素濃度が高くなっているため、親水性である。このため、CMPプロセスにおいて表面改質層が露出することによって水滴が残りにくくなり、CMPプロセス後のパーティクルの残留やウォーターマークの発生を低減できる。
また、本実施形態における用語の意味については、以下に説明するとおりである。
図1は、本発明による半導体装置の第1実施形態を示す断面図である。
半導体装置100は、
半導体基板と、
半導体基板上に設けられたSiOCH膜10(第一絶縁膜)と、
SiOCH膜10の表層を改質することにより形成された、SiOCH膜10よりも炭素濃度が低くかつSiOCH膜10よりも酸素濃度が高い表面改質層20と、
表面改質層20及びSiOCH膜10に形成された凹部内に埋設されたCu配線50と、
Cu配線50の表面及び表面改質層20の表面に接するキャップ絶縁膜(第二絶縁膜)60と、
を含む。
SiOCH膜10は、シリコン酸化膜(比誘電率3.9〜4.5)よりも比誘電率が低い低誘電率絶縁膜であって、多孔質絶縁膜である。SiOCH膜10としては、例えば、シリコン酸化膜を多孔質化して比誘電率を小さくした膜、HSQ(ハイドロゲンシルセスキオキサン(Hydrogen SilsesQuioxane))膜、およびSiOCH或いはSiOC(例えば、Black DiamondTM、CORALTM、AuroraTM)などを多孔質化して比誘電率を小さくした膜などが挙げられる。
具体的には、SiOCH膜10上にハードマスク30を形成する前に、ハードマスク形成チャンバーにてHeプラズマ処理を行う。適度なHeプラズマ処理を行うことで、CMP時にハードマスク30を除去した場合でも、親水化した表面改質層20が存在するため、CMP後のパーティクルやウォーターマークの生成を抑制できる。
一方、過度のHeプラズマ処理を施した場合には、表面改質層20が厚くなり、硬化した表面改質層20がCMP時に剥離し、大規模スクラッチを誘起するという問題が生じる。そのため、表面改質層20がSiOCH膜10の表層に形成されるよう、Heプラズマ処理の条件が適宜調整される。
ハードマスク30の材料としては、C量が少ないものであって、例えばSiO2などが挙げられる。
半導体装置100の製造方法は、
半導体基板上にSiOCH膜10(第一絶縁膜)を形成する工程と、
不活性ガスを用いたプラズマ処理を施し、SiOCH膜10の表層に表面改質層20を形成する工程と、
表面改質層20上にハードマスク30を形成する工程と、
ハードマスク30およびSiOCH膜10に、ハードマスク30および表面改質層20を貫通する凹部を形成する工程と、
凹部内を埋め込むようにCu配線50を形成する工程と、
凹部の外部に露出したCu配線50を除去し、かつハードマスク30を除去して表面改質層20を露出する工程と、
露出された表面改質層20、およびCu配線50の表面にキャップ絶縁膜60(第二絶縁膜)を形成する工程と、を含む。
以下、各工程について詳述する。
Heプラズマ処理条件としては、たとえば、処理温度200〜400℃、Heガス流量10〜5000sccm、圧力1〜20Torr、プラズマ発生用高周波電源パワー200〜500W、時間は5〜60秒に設定する。なお、不活性ガスとは、たとえば、ヘリウム、ネオン、アルゴンなどの希ガスをいう。
第一絶縁膜(SiOCH膜10)となる原料モノマーとして、下記式(3)に示す環状有機シリカ構造を有する原料を用いる。原料圧送部102からのHeガスによりリザーバー101からは原料モノマーが送り出され、液体マスフロー104によりその流量が制御される。一方、キャリアガス供給部103からはHeガスが供給され、その流量はガスマスフロー105によって制御される。
半導体装置100は、SiOCH膜10の表層が改質されることにより形成された、SiOCH膜10よりも炭素濃度が低くかつSiOCH膜10よりも酸素濃度が高い表面改質層20が設けられるとともに、Cu配線50の表面及び表面改質層20の表面に接するキャップ絶縁膜60を有している。
さらに、表面改質層20は、SiOCH膜10よりも、炭素濃度が低くかつ酸素濃度が高くなっているため、親水性である。このため、CMPプロセスにおいて表面改質層20が露出することによって水滴が残りにくくなり、CMPプロセス後のパーティクルの残留やウォーターマークの発生を低減できる。
なお、本発明は以下の実施例に限定されるものではなく、本発明の目的を達成できる範囲での変更、改良等は本発明に含まれるものである。デュアルダマシン法またはシングルダマシン法によって形成される第2以降の配線層についても第1の配線層と同様な方法で形成することが可能である。
まず、シリコン基板上に300nmのSiO2膜を成膜し、この上に第1配線層をシングルダマシン法によって形成した。
次に、このSiO2膜上に、下記式(3)に示す環状有機シリカ構造を有する原料を用いて、上記第一実施形態で説明したのと同様にしてプラズマCVD法により、ポーラスSiOCH膜を形成した。ポーラスSiOCH膜は、配線間絶縁膜であって、厚さ120nm、比誘電率2.5であった。
図6は、実施例1で作成したポーラスSiOCH膜にHeプラズマ処理を施した場合(Heプラズマ処理)と、実施例1で作成したポーラスSiOCH膜にHeプラズマ処理を行わなかった場合(未処理)の、ポーラスSiOCH膜の深さと炭素濃度及び酸素濃度との関係を示すグラフ図である。ポーラスSiOCH膜の炭素濃度(図6(a))及び酸素濃度(図6(b))は、X線光電子分光(XPS)分析により求められた。グラフより、Heプラズマ処理によって、ポーラスSiOCH膜表面のC濃度が、60atomic%から43atomic%に低減し、O濃度が20atomic%から35atomic%に変化していることがわかった。
図7は、CMP完了後のウェハ面内の欠陥分布を示す図である。図7(a)〜(c)はそれぞれ、上記実施例1で示したポーラスSiOCH上にHeプラズマ処理を、全く行わない場合、15秒行った場合、50秒行った場合をそれぞれ示す。
図8は、SiOCH膜のC/Si組成比と、研磨レートとの関係を示すグラフ図である。図8より、SiOCH膜のC/Si比が増すに従って、CMP研磨レートが低減していることがわかった。
図9は、SiOCH膜と、研磨量との関係を示すグラフである。また、横軸のSiOCH膜は、比誘電率及びC/Si組成が異なる3種類のSiOCH膜であって、縦軸にはそれぞれのSiOCH膜の配線パターン(L/S;配線幅(L)、配線スペース(S))、および配線幅(L)ごとの研磨量が示されている。
SiOCH膜の研磨量は、SiOCH膜にHeプラズマ処理を15秒施した後、十分にSiO2ハードマスクが取りきれている状態から、さらに30秒オーバー研磨を追加した場合の膜減り量を電子顕微鏡(SEM)で観察して求めた。
10a SiOCH膜
10b SiOCH膜
20 表面改質層
20a 表面改質層
20b 表面改質層
30b ハードマスク
40 バリア膜
40a バリア膜
40b バリア膜
50 Cu配線
50a Cu配線
50b Cu配線
60 キャップ絶縁膜
60a キャップ絶縁膜
60b キャップ絶縁膜
100 半導体装置
101 リザーバー
102 原料圧送部
103 キャリアガス供給部
104 液体マスフロー
105 ガスマスフロー
106 気化器
107 リアクター
108 基板
109 電源
110 排気ポンプ
Claims (17)
- 半導体基板と、
前記半導体基板上に設けられたSiOCH膜からなる第一絶縁膜と、
前記第一絶縁膜の表層を改質することにより形成された、前記第一絶縁膜よりも炭素濃度が低くかつ前記第一絶縁膜よりも酸素濃度が高い表面改質層と、
前記表面改質層及び前記第一絶縁膜に形成された凹部内に埋設された金属配線と、
前記金属配線の表面及び前記表面改質層の表面に接する第二絶縁膜と、
を含むことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記表面改質層の厚さが3nm以上30nm未満であることを特徴とする半導体装置。 - 請求項1または2に記載の半導体装置において、
前記第一絶縁膜は、SiOCH膜であって、C/Siで表される組成比が1以上10以下であることを特徴とする半導体装置。 - 請求項1乃至3いずれかに記載の半導体装置において、
前記表面改質層の炭素濃度は、前記第一絶縁膜の炭素濃度の50%以上90%未満であり、かつ前記表面改質層の酸素濃度は、前記第一絶縁膜の酸素濃度の110%以上200%未満であることを特徴とする半導体装置。 - 請求項1乃至4いずれかに記載の半導体装置において、
前記第一絶縁膜は複数の空孔を有し、前記空孔の平均径は0.8nm未満で、かつ前記空孔が互いに独立した孔であることを特徴とする半導体装置。 - 請求項1乃至5いずれかに記載の半導体装置において、
前記第二絶縁膜は、SiN膜、SiCN膜、およびSiC膜のいずれかを用いた単層または少なくとも2以上を用いた積層の膜であることを特徴とする半導体装置。 - 請求項1乃至5いずれかに記載の半導体装置において、
前記第二絶縁膜は、不飽和炭化水素とアモルファスカーボンを有する第一膜、またはSiN膜、SiCN膜、およびSiC膜のうち少なくとも一つを用いた第二膜と前記第一膜との積層膜であることを特徴とする半導体装置。 - 請求項1乃至10いずれかに記載の半導体装置において、
前記金属配線は、銅含有配線であることを特徴とする半導体装置。 - 半導体基板上にSiOCH膜からなる第一絶縁膜を形成する工程と、
不活性ガスを用いたプラズマ処理を施し、前記第一絶縁膜の表層に表面改質層を形成する工程と、
前記表面改質層上にハードマスクを形成する工程と、
前記ハードマスクおよび前記第一絶縁膜に、前記ハードマスクおよび前記表面改質層を貫通する凹部を形成する工程と、
前記凹部内を埋め込むように金属配線を形成する工程と、
前記凹部の外部に露出した前記金属配線を除去し、かつ前記ハードマスクを除去して前記表面改質層を露出する工程と、
露出された前記表面改質層、および前記金属配線の表面に第二絶縁膜を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項12乃至15いずれかに記載の半導体装置の製造方法において、
前記表面改質層を露出する前記工程は、
研磨液としてアルカリ性のスラリーを用いた化学機械研磨により、前記凹部の外部に露出した前記金属配線を除去し、かつ前記ハードマスクを除去して前記表面改質層を露出することを特徴とする半導体装置の製造方法。 - 請求項12乃至16いずれかに記載の半導体装置の製造方法において、
前記ハードマスクは、SiO2であることを特徴とする半導体装置の製造方法。
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Also Published As
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US8492266B2 (en) | 2013-07-23 |
US20120070986A1 (en) | 2012-03-22 |
JP5554951B2 (ja) | 2014-07-23 |
US8080878B2 (en) | 2011-12-20 |
US20100059887A1 (en) | 2010-03-11 |
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