WO2007132879A1 - 半導体装置、半導体装置の製造方法及び半導体製造装置 - Google Patents
半導体装置、半導体装置の製造方法及び半導体製造装置 Download PDFInfo
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- WO2007132879A1 WO2007132879A1 PCT/JP2007/060012 JP2007060012W WO2007132879A1 WO 2007132879 A1 WO2007132879 A1 WO 2007132879A1 JP 2007060012 W JP2007060012 W JP 2007060012W WO 2007132879 A1 WO2007132879 A1 WO 2007132879A1
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- insulating film
- film
- wiring
- semiconductor device
- modified layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 136
- 238000004519 manufacturing process Methods 0.000 title claims description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 118
- 239000002184 metal Substances 0.000 claims abstract description 113
- -1 siloxane structure Chemical group 0.000 claims abstract description 72
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 64
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 61
- 239000001301 oxygen Substances 0.000 claims abstract description 61
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 125000004432 carbon atom Chemical group C* 0.000 claims abstract description 53
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 52
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 36
- 125000004430 oxygen atom Chemical group O* 0.000 claims abstract description 30
- 239000010410 layer Substances 0.000 claims description 215
- 239000011229 interlayer Substances 0.000 claims description 180
- 238000000034 method Methods 0.000 claims description 86
- 239000000758 substrate Substances 0.000 claims description 41
- 238000012986 modification Methods 0.000 claims description 31
- 230000004048 modification Effects 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 31
- 230000008569 process Effects 0.000 claims description 28
- 230000003647 oxidation Effects 0.000 claims description 26
- 238000007254 oxidation reaction Methods 0.000 claims description 26
- 239000007789 gas Substances 0.000 claims description 24
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 22
- 238000001312 dry etching Methods 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 19
- 238000004380 ashing Methods 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 17
- 238000012545 processing Methods 0.000 claims description 17
- 125000001183 hydrocarbyl group Chemical group 0.000 claims description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 11
- 238000002407 reforming Methods 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 229910018557 Si O Inorganic materials 0.000 claims description 5
- 229930195735 unsaturated hydrocarbon Chemical group 0.000 claims description 5
- 125000004429 atom Chemical group 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 26
- 150000001721 carbon Chemical group 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 609
- 239000010949 copper Substances 0.000 description 50
- 239000002994 raw material Substances 0.000 description 37
- 230000004888 barrier function Effects 0.000 description 36
- 230000009977 dual effect Effects 0.000 description 22
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 18
- 125000004122 cyclic group Chemical group 0.000 description 17
- 239000000463 material Substances 0.000 description 17
- 239000000203 mixture Substances 0.000 description 17
- 238000004458 analytical method Methods 0.000 description 14
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 13
- 229910010271 silicon carbide Inorganic materials 0.000 description 13
- 230000036961 partial effect Effects 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 239000000126 substance Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 239000001257 hydrogen Substances 0.000 description 10
- 229910052739 hydrogen Inorganic materials 0.000 description 10
- 238000005240 physical vapour deposition Methods 0.000 description 9
- 238000009832 plasma treatment Methods 0.000 description 9
- 238000004544 sputter deposition Methods 0.000 description 9
- 238000012360 testing method Methods 0.000 description 9
- 229910018565 CuAl Inorganic materials 0.000 description 7
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 7
- 229910001882 dioxygen Inorganic materials 0.000 description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 7
- DZPJVKXUWVWEAD-UHFFFAOYSA-N [C].[N].[Si] Chemical compound [C].[N].[Si] DZPJVKXUWVWEAD-UHFFFAOYSA-N 0.000 description 6
- 239000010432 diamond Substances 0.000 description 6
- 238000011065 in-situ storage Methods 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 6
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 230000005284 excitation Effects 0.000 description 5
- 150000002431 hydrogen Chemical class 0.000 description 5
- 230000002829 reductive effect Effects 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 4
- 238000010306 acid treatment Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910000510 noble metal Inorganic materials 0.000 description 4
- 125000005375 organosiloxane group Chemical group 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 239000004215 Carbon black (E152) Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000001237 Raman spectrum Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- 229930195733 hydrocarbon Natural products 0.000 description 3
- 150000002430 hydrocarbons Chemical class 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910052754 neon Inorganic materials 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 235000014653 Carica parviflora Nutrition 0.000 description 2
- 244000132059 Carica parviflora Species 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 238000001069 Raman spectroscopy Methods 0.000 description 2
- 238000003848 UV Light-Curing Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 150000001412 amines Chemical class 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 2
- 238000009835 boiling Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000001227 electron beam curing Methods 0.000 description 2
- 238000005430 electron energy loss spectroscopy Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 235000011470 Adenanthera pavonina Nutrition 0.000 description 1
- 240000001606 Adenanthera pavonina Species 0.000 description 1
- 229910016570 AlCu Inorganic materials 0.000 description 1
- 241000252073 Anguilliformes Species 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910002656 O–Si–O Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000560 X-ray reflectometry Methods 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000005441 aurora Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 244000309464 bull Species 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000701 chemical imaging Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000005262 decarbonization Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000000619 electron energy-loss spectrum Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- QHGSGZLLHBKSAH-UHFFFAOYSA-N hydridosilicon Chemical compound [SiH] QHGSGZLLHBKSAH-UHFFFAOYSA-N 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 125000001449 isopropyl group Chemical group [H]C([H])([H])C([H])(*)C([H])([H])[H] 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 231100000572 poisoning Toxicity 0.000 description 1
- 230000000607 poisoning effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 125000001436 propyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052704 radon Inorganic materials 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 238000001350 scanning transmission electron microscopy Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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Definitions
- the present invention relates to a semiconductor device having a multilayer wiring, a method for manufacturing a semiconductor device, and a semiconductor manufacturing apparatus, and more particularly to a semiconductor device configured with a damascene wiring structure mainly composed of Cu.
- LSIs silicon semiconductor integrated circuits
- A1 aluminum
- A1 alloy has been widely used as a conductive material.
- copper (Cu) has come to be used as a conductive material in order to reduce wiring resistance in wiring and achieve high reliability. Since this Cu easily diffuses into the silicon oxide film, a conductive barrier metal film that prevents Cu diffusion is used on the side and bottom of the Cu wiring, and an insulating barrier is formed on the upper surface of the Cu wiring. A membrane is used.
- the low dielectric constant insulating film include an HSQ (hydrogen silsesquioxane) film, a CDO (carbon doped oxide) film, and an organic film. These low dielectric constant insulating films are formed by a spin coating method or a gas phase method.
- Japanese Unexamined Patent Application Publication No. 2003-309173 discloses an NF plasma treatment for an organic siloxane film.
- Japanese Patent Application Laid-Open No. 2006-24641 discloses a modified organic siloxane film by reducing treatment. Techniques for forming a porous layer and protecting an organosiloxane film are described.
- JP-T-2002-526916 describes a technique for forming a porous insulating film using a cyclic organosiloxane raw material.
- Japanese Patent Application No. 2003-400683 discloses a technique for forming a porous insulating film using a three-membered cyclic organosiloxane raw material.
- the modified layer is formed by plasma treatment of the organosiloxane film.
- an organosiloxane film having a relative dielectric constant of 2.5 or less is formed by the technique described in Japanese Patent Application Laid-Open No. 2006-24641
- the modified layer is formed thick, resulting in an increase in the relative dielectric constant and wiring. There was a problem that the capacity increased during this period.
- low dielectric constant insulating films that can achieve a relative dielectric constant of 2.5 or less are disclosed in Japanese Patent Application Publication No. 2002-526916 and Japanese Patent Application No. 2003-400683. It can be formed by using a cyclic organosiloxane raw material.
- this low dielectric constant insulating film is applied to a wiring interlayer insulating film in order to achieve a low wiring capacitance, There is a problem that leakage current between wirings increases. That is, although the capacitance between wires can be reduced, the power consumption of the entire chip due to the leakage current between wires increases, and the insulation reliability between wires deteriorates. It was.
- the present invention has been made to solve the above problems, and provides a multilayer wiring technique having high adhesion and high insulation reliability between wirings while maintaining effective low wiring capacitance. It is something.
- the modified layer is formed on at least one of the interface between the first insulating film and the metal and the interface between the first insulating film and the second insulating film.
- the modified layer is characterized in that the number of carbon atoms per unit volume is smaller than that in the first insulating film and the number of oxygen atoms is increased.
- the number of carbon atoms per unit volume in the first insulating film including the siloxane structure is larger than the number of oxygen atoms.
- this modified layer is a layer having excellent adhesion and insulating properties.
- Figure 1 shows the Raman spectrum of a three-membered cyclic SiOCH film as an example of the Raman spectrum. 580 cm _1 and spectrum of 3-membered cyclic siloxane are detected near reflected the raw material siloxane structure I may insulating film having a cyclic Si- O backbone is possible to form Chikararu. Thus, the analysis of the siloxane structure can be performed by using the Raman analysis.
- Table 1 shows compositions at the time of forming each insulating film, measured by RBSZHFS analysis.
- the ratio of carbon atoms to silicon atoms in the film (CZSi) is expressed by the following formula (3) (random type SiOCH film) formula (2) (four-membered ring type SiOCH film) formula (1) (three-membered ring type SiOCH film) ) In order of increase.
- Random type 1 1 0.7 SiOCH Figure 2 is a plot of the change in the dielectric constant of the insulating film with the acid treatment time for the above three films.
- O plasma irradiation is a parallel plate type in-situ assembly.
- the substrate distance (GAP) 30 mm, pressure 10 mTorr, upper electrode frequency 60 MHz, upper electrode power 600 W, lower electrode frequency 13.56 MHz, lower electrode powerlO 0W, and processing is performed only with oxygen gas.
- the increase in the relative permittivity with the acid-sodium treatment time is shown by the following formula (3) (random type SiOCH film), formula (2) (four-membered ring type SiOCH film), formula (1) (3 It turns out that it becomes small in order of the member ring type SiOCH film).
- the thickness of the modified layer formed on the surface was estimated by XPS (X-ray Photoelectron Spectroscopy) depth direction analysis, and 40 nm (random SiOCH film)> 20 nm (4-membered ring-type SiOCH film)> It was found that the thickness decreased in the order of 10 nm (3-membered ring-type Si OCH film).
- the density of the modified layer formed on the surface of the three-membered ring-type SiOCH film was measured by XRR (X-Ray Reflection: reflectivity measurement) and found to be 2. OgZcm 3 or more.
- a film composition having a larger number of carbon atoms than the number of silicon atoms is preferred because the dielectric constant of the insulating film itself is lowered by the increase of carbon, which is a light element. .
- the densification reaction proceeds with the carbon substitution reaction, and a high-density reformed layer with a nano-level thickness can be formed. It is.
- the siloxane structure preferably includes both a hydrocarbon group having at least 3 carbon atoms and an unsaturated hydrocarbon group.
- the siloxane structure contains both unsaturated hydrocarbon groups and hydrocarbon groups having 3 or more carbon atoms, so that the decarbonization rate is reduced by the strong bond energy of the unsaturated hydrocarbon groups, and the carbon number A large amount of hydrocarbon groups can keep a large amount of hydrocarbon components in the film.
- the cyclic siloxane structure is lower than the random siloxane structure, the high-density modified layer can be formed even though the specific dielectric constant of the film is low. This is because the bonding angle of O—Si—O is smaller as the structure is formed, and thus a high-density SiO structure is easily formed.
- the density of corsite (4-membered ring; 2.92 g / cm 3 ) is higher than that of quartz (6-membered ring; 2.65 g / cm 3 ). Therefore, oxygen substituted for carbon, which is easy to form a high-density O-Si-o structure as an intensified skeleton and preferably contains cyclic siloxane in the insulating film, is a continuous unit of cyclic units. And can easily form a high-density and thin 1% modified layer.
- any of the wiring interlayer insulating film, the hard mask film, and the via interlayer insulating film in contact with the metal wiring and the connection plug is used.
- a first insulating film containing a siloxane structure containing at least silicon, oxygen, and carbon is used.
- each insulating film includes a siloxane structure including both a side chain having 3 or more carbon atoms and a vinyl group.
- the wiring interlayer insulation film, the hard mask film, and the via interlayer insulation film can be formed separately.
- a via interlayer insulating film is formed by setting a low voltage dividing condition
- a wiring interlayer insulating film is formed by setting a high voltage dividing condition
- a relatively low adhesion condition and film strength are set by using a low pressure condition.
- Excellent hardware A mask film and a via interlayer insulating film can be formed.
- the above-mentioned wiring interlayer insulating film, hard A mask film and a via interlayer insulating film can be formed separately.
- the CZSi ratio of the via interlayer insulation film is about 1.4 and the relative dielectric constant 2.7
- the dielectric interlayer dielectric of the wiring interlayer insulation film is about 2.9 and the relative dielectric constant 2.
- a SiOCH film with a CZSi ratio of about 1.2 and a relative dielectric constant of 3.0 can be formed.
- the via interlayer insulating film has a slightly larger number of carbon atoms. Decrease the dielectric constant.
- the wiring interlayer insulating film contains a large number of carbon atoms in order to reduce the relative dielectric constant most. Therefore, when all of the hard mask film, wiring interlayer insulating film, and via interlayer insulating film are insulating films containing a siloxane structure containing at least silicon, oxygen, and carbon, the number of carbon atoms per unit volume in the insulating film.
- the wiring interlayer insulating film> By using the via interlayer insulating film> hard mask film, the adhesion can be further improved.
- the number of carbon atoms per unit volume in the modified layer depends on the modified layer between the wiring interlayer insulating film and the metal, the modified layer between the via interlayer insulating film and the metal, and between the hard mask film and the metal. By decreasing the number of the modified layers in order, the adhesion between these layers can be improved.
- the density inside the first insulating film is typically 1.2 g / cm 3 or less.
- the present invention has the following configuration.
- a wiring groove and a via hole are formed in an insulating film on a semiconductor substrate, and the wiring groove and the via hole are respectively filled with a metal and a connection plug, and at least a part of the insulating film is a first insulating film.
- a multilayer wiring composed of a film and a second insulating film;
- the first insulating film includes at least a siloxane structure containing silicon, oxygen, and carbon. Both are one or more insulating films,
- the siloxane structure inside the first insulating film has more carbon atoms than silicon atoms, the interface between the first insulating film and the metal, and the interface between the first insulating film and the second insulating film.
- a semiconductor device characterized in that a modified layer having a smaller number of carbon atoms per unit volume and a larger number of oxygen atoms is formed in at least one of them than in the first insulating film.
- siloxane structure includes both a hydrocarbon group having 3 or more carbon atoms and an unsaturated hydrocarbon group.
- siloxane structure includes a cyclic siloxane structure including an oxygen atom and a silicon atom.
- the first insulating film is composed of a via interlayer insulating film in a via plug portion, a wiring interlayer insulating film in a wiring portion, and a hard mask film in a wiring portion, which are sequentially stacked from the semiconductor substrate side.
- Each of the hard mask film, the wiring interlayer insulating film, and the via interlayer insulating film is an insulating film including a siloxane structure containing silicon, oxygen, and carbon,
- the modified layer is formed at the interface with the metal in any of the hard mask film, the wiring interlayer insulating film, and the via interlayer insulating film,
- the modified layer has a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than in the corresponding first insulating film.
- the number of carbon atoms per unit volume in the modified layer is determined as follows: the modified layer between the wiring interlayer insulating film and the metal> the modified layer between the via interlayer insulating film and the metal> the modified layer between the hard mask film and the metal. 11. The semiconductor device as described in any one of 1 to 10 above, wherein the number of layers is smaller in order.
- a wiring groove and a via hole are formed in the insulating film on the semiconductor substrate, and the wiring groove and the via hole are respectively filled with a metal and a connection plug, and at least a part of the insulating film is the first. It has a multilayer wiring composed of an insulating film of
- the first insulating film is an insulating film having at least one layer including a siloxane structure containing silicon, oxygen, and carbon,
- the siloxane structure inside the first insulating film has more carbon atoms than the number of silicon atoms, and carbon per unit volume at the interface between the first insulating film and the metal than in the first insulating film.
- a reforming step for forming the modified layer By modifying the wiring trench and via hole side surface in the first insulating film, A reforming step for forming the modified layer;
- a method for manufacturing a semiconductor device comprising:
- a wiring groove and a via hole are formed in the insulating film on the semiconductor substrate, and the wiring groove and the via hole are respectively filled with a metal and a connection plug, and at least a part of the insulating film is the first.
- the first insulating film is an insulating film having at least one layer including a siloxane structure containing silicon, oxygen, and carbon,
- the siloxane structure inside the first insulating film has more carbon atoms than silicon atoms at the interface between the first insulating film and the metal and at the interface between the first insulating film and the second insulating film.
- a modification step of forming the modified layer by performing a modification process on the side surfaces of the wiring grooves and via holes in the first and second insulating films; Forming wirings and connection plugs by filling the wiring trenches and via holes with metal, respectively;
- a method for manufacturing a semiconductor device comprising:
- Etching gas force of the dry etching contains at least Ar, N, O and CF
- a semiconductor manufacturing apparatus comprising: a control unit including a microcomputer storing a program for controlling the groove forming step, the photoresist removing step, and the modifying step.
- the control means further includes a plasma processing sequence in the insulating film forming step.
- the semiconductor manufacturing apparatus By using the semiconductor device manufacturing method, the semiconductor manufacturing apparatus, and the semiconductor device of the present invention, it is possible to simultaneously achieve a low dielectric constant and a high insulation reliability of the interlayer insulating film. In addition, by having high adhesion, it is possible to improve the performance of the wiring and to form a high-speed, low-power-consuming LSI with high reliability.
- the modification treatment in the “step of forming a modified layer on the surface of the second insulating film and forming the modified layer” and the modification step is an oxidation treatment. Further, in the above “13”, it is preferable that the reforming process is performed by nitrogen plasma in the “step of modifying the surface of the second insulating film to form the modified layer” and the modifying step. That's right.
- FIG. 1 is a diagram showing a Raman spectrum of a 3-membered cyclic SiOCH film.
- FIG. 2 is a diagram showing a change in relative dielectric constant of an insulating film depending on an acid treatment time.
- FIG. 3 is a diagram illustrating a manufacturing example of the semiconductor device according to the first embodiment of the present invention.
- FIG. 4 is a diagram showing a comparison result of leakage current between wirings of a semiconductor device with a modified layer and without a modified layer.
- FIG. 5 A plot (RC plot) of wiring resistance and wiring capacity of a semiconductor device with and without a modified layer.
- FIG. 6 is a diagram showing the results of a composition analysis of the semiconductor device without the modified layer and the first embodiment by TEM-EELS.
- FIG. 7 shows each modification of the structure of the dual damascene wiring in the first embodiment.
- FIG. 8 shows each modification of the structure of the dual damascene wiring in the first embodiment.
- FIG. 9 shows each modification of the structure of the dual damascene wiring of the first embodiment.
- FIG. 10 is a diagram illustrating a manufacturing example of the semiconductor device according to the second embodiment of the present invention.
- FIG. 11 is a diagram showing each modification of the structure of the dual damascene wiring of the second embodiment.
- FIG. 12 shows each modification of the structure of the dual damascene wiring of the second embodiment.
- FIG. 13 is a diagram showing a result of composition analysis between wirings of the multilayer wiring of Comparative Example 1 by TEM-EELS.
- FIG. 14 is a diagram illustrating a manufacturing example of the semiconductor device according to the first embodiment of the invention.
- FIG. 15 is a diagram showing an example of a semiconductor device according to Example 2 of the present invention.
- Low dielectric constant insulating film '' is, for example, a film (interlayer insulating film) that insulates and separates wiring materials, and a silicon oxide film (relative dielectric constant) in order to reduce the capacitance between multilayer wirings connecting semiconductor elements 4.
- the porous insulating film for example, a material in which a silicon oxide film is made porous to reduce the relative dielectric constant, an HSQ (Hydrogen Silsesquioxane) film, or a SiOCH, SiOC (for example, , Black Diamond (Trade Mark), CORAL (Trade Mark), Aurora (Trade Mark)), etc. are made porous to reduce the dielectric constant.
- a film forming technique using a cyclic siloxane material is being studied.
- the "siloxane structure” means a structure composed of at least a silicon atom, an oxygen atom, and a carbon atom among compounds containing a Si-O bond, and a film skeleton formed by these atoms. . Further, depending on the siloxane structure, it may have a hydrogen atom. In the present invention, if the number of carbon atoms is too large, a skeleton as a siloxane structure cannot be formed. Therefore, in the present invention, the number of carbon atoms is a silicon atom. The number is preferably 5 times or less.
- Cyclic siloxane refers to a cyclic structure composed of a plurality of units when Si—O is counted as one unit.
- a three-membered ring means a hexagonal molecular structure with (SiO) force.
- the four-membered ring means an octagonal molecular structure that also has (SiO) force.
- Cyclic organosiloxane means a molecular structure having a hydrocarbon group in the side chain of the cyclic siloxane structure.
- hydrocarbon group include a methyl group, an ethyl group, a propyl group, an isopropyl group, and a vinyl group.
- Such a cyclic siloxane raw material is effective for forming a porous insulating film.
- the insulating film is not necessarily limited to a porous film.
- the composition of the insulating film is the ratio of the number of atoms contained per unit volume.
- “Plasma vapor phase epitaxy” refers to, for example, supplying gaseous raw material continuously to a reaction chamber under reduced pressure, causing molecules to be excited by plasma energy, and performing gas phase reaction or substrate surface. This is a technique for forming a continuous film on a substrate by reaction or the like.
- the case where the reactivity of the monomer is improved by introducing a side chain having a high reactivity such as a vinyl group in advance of the raw material molecule is sometimes called a plasma polymerization method.
- Damascene wiring is formed by embedding a metal wiring in a groove of a pre-formed interlayer insulating film and removing excess metal other than in the groove by, for example, CMP. This refers to embedded wiring.
- a wiring structure is generally used in which the side and outer periphery of the Cu wiring are covered with a barrier metal, and the upper surface of the Cu wiring is covered with an insulating barrier film.
- Metal wiring has Cu as a main component.
- metal elements other than Cu may be included in the member made of Cu.
- Metal elements other than Cu may be formed on the upper surface or side surfaces of Cu. .
- the "CMP (Chemical Mechanical Polishing) method” is a method in which unevenness on the wafer surface that occurs during the multilayer wiring formation process is polished by bringing it into contact with a polishing pad that is rotated while flowing a polishing liquid over the wafer surface. It is a method of flattening. In wiring formation by the damascene method, it is used to obtain a flat wiring surface by removing excess metal after embedding metal in wiring grooves or via holes.
- “Barrier metal” refers to a conductive film having a barrier property that covers the side and bottom surfaces of a wiring in order to prevent a metal element constituting the wiring from diffusing into an interlayer insulating film or a lower layer. .
- the wiring is made of a metal element whose main component is Cu, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), Titan (WTi), tungsten carbonitride (WCN), etc.
- Ta tantalum
- TaN tantalum nitride
- TiN titanium nitride
- Ti Titan
- WCN tungsten carbonitride
- a refractory metal, a nitride thereof, or a laminated film thereof is used.
- An "insulating barrier film” is a film formed on the upper surface of a Cu wiring, which has a function of preventing Cu from diffusing into a copper oxide insulating film and a role as an etching stop layer during processing. Show. For example, SiC film, SiCN film, SiN film, etc. are used.
- a “semiconductor substrate” is a substrate on which a semiconductor device is configured.
- a semiconductor device is configured.
- substrates such as manufacturing substrates.
- Hard mask refers to a low dielectric constant that is deposited on the interlayer insulating film when it is difficult to perform CMP directly due to a decrease in strength due to the low dielectric constant of the interlayer insulating film.
- Passivation film refers to a film that is formed in the uppermost layer of a semiconductor element and has a role of protecting the semiconductor element from external moisture and the like.
- a silicon oxynitride film (SiON) formed by a plasma CVD method, a polyimide film, or the like is used.
- Resist poisoning means that the chemical amplification group of the resist is deactivated by the amine component occluded in the low dielectric constant insulating film or at the interface of these insulating films, and the pattern This is a phenomenon that causes malfunction.
- PVD Physical Vapor Deposition
- a normal sputtering method can be used.
- long throw sputtering method collimated sputtering method, ionized sputtering method, etc.
- the metal film formed can be made into an alloy film by preferentially containing a metal other than the main component in the metal target below the solid solubility limit.
- this method can be used mainly when forming a Cu seed layer or a barrier metal layer when forming a damascene Cu wiring.
- TDDB (Time Dependent Dielectric Breakdown) life is a technique for predicting the time until dielectric breakdown by an accelerated test.
- a comb-shaped TEG Thermal Anneadvant
- the measurement condition at a predetermined temperature for example, 125 ° C
- Apply a high electric field By monitoring the leakage current flowing between the wires and measuring the time until the electric field application start time force breakdown, the superiority and inferiority of the TDDB life can be compared.
- m-ELT test is an abbreviation for modified Edge Liftoff Test. An epoxy layer is applied to a sample, and after curing at about 120 ° C, the sample is cooled. At this time, a peeling force is applied to the end face of each layer of the sample due to the residual stress of the epoxy layer generated by cooling, and a peeling portion is generated. This peeling location is detected by image processing, and the temperature at that time is recorded.
- m-ELT test it is assumed that the energy released during peeling is approximately equal to the elastic energy stored in the epoxy layer.
- this is a method for calculating the stress strength (peeling strength) applied to the test thin film. It can be judged that the larger the stress value at peeling obtained by this m-ELT test, the better the adhesion.
- the "siloxane structure" can be analyzed by Raman analysis.
- the “thickness of the modified layer” can be measured by a depth direction analysis of XPS (X-ray Photoelectron Spectroscopy).
- the “modified layer density” can be measured by XRR (X-Ray Reflection).
- the modified layer and the inside of the first insulating film can be discriminated by analysis using TEM-EELS. Furthermore, the composition (atomic ratio) per unit volume in the first insulating film and in the modified layer can be analyzed by this TEM-EELS analysis.
- the interface between the first insulating film and the metal and the interface between the first insulating film and the second insulating film has a modified layer. Should be formed.
- the first insulating film and the second insulating film are formed continuously. However, it may be formed through a clear interface.
- the second insulating film may contain a siloxane structure containing silicon, oxygen and carbon, and a modified layer may be formed at the interface between the second insulating film and the metal.
- the hard mask, the via interlayer insulating film, and the wiring interlayer insulating film may or may not become the first insulating film.
- a cyclic organosiloxane raw material is supplied to the reaction chamber to form a low dielectric constant insulating film suitable as an interlayer insulating film. Then, a suitable modified layer is formed by plasma vapor phase epitaxy on the portion of the insulating film containing the cyclic siloxane structure that becomes the interface with the metal wiring, thereby reducing the capacitance between the wirings and insulating. It is possible to ensure both reliability and reliability.
- the multilayer wiring structure on the semiconductor substrate formed with the semiconductor element formed according to the present embodiment will be described in detail below.
- a noria metal 310a, a metal wiring 311a, an insulating barrier film 31 2b are formed on a semiconductor substrate (not shown) on which a semiconductor element is formed.
- a via interlayer insulating film 313, a wiring interlayer insulating film 314, and a hard mask film 315 are formed thereon.
- the first insulating film is the wiring interlayer insulating film 314, and the second insulating film is the via interlayer insulating film 313.
- Metal wiring is mainly composed of Cu, and metal elements other than Cu may be included to improve the reliability of metal wiring. Metal elements other than Cu are present on the top and side surfaces of Cu. It may be formed. This metal wiring can be formed by a sputtering method using a Cu target, a CVD method, or an electrolytic plating method using a Cu film formed by these methods as an electrode.
- the metal element other than the main component it is also effective to add at least one metal selected from the group force including aluminum, tin, titanium, tungsten, silver, zirconium, indium, and magnesium force. .
- a metal other than Cu for example, tungsten (W) or a compound such as CoWP, is used as an adhesion layer and inserted between the Cu wiring and the insulating barrier film. It is also effective to do.
- the insulating barrier film is made of SiN, SiCN, SiC film, etc., and has a film thickness of 200 to 500 A, and is formed by the plasma CVD method.
- the rare metal can be formed by using a sputtering method, a CVD method, an ALCVD (Atomic Layer Chemical Vapor Deposition) method, or the like.
- barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titan (WTi), titan nitride (WTiN), refractory metals such as tungsten carbonitride (WCN), and nitrides thereof.
- WCN tungsten carbonitride
- WCN tungsten carbonitride
- TaZTaN upper Z lower layer laminated film for Noria metal.
- the via interlayer insulating film 313 is an insulating film containing at least silicon, oxygen, carbon and hydrogen, and has a film thickness of about 1000 to 3000 A and a relative dielectric constant of 3.0 or less. Is preferred.
- the via interlayer insulating film 313 may be an insulating film containing a cyclic siloxane structure containing at least silicon, oxygen, carbon, and hydrogen.
- Examples of the via interlayer insulating film 313 include, for example, an HSQ (Nydrogen Silsesquioxane; Hydrogen Silsesquioxane) film (for example, Typel2 (Trade Mark)), an MSQ (Methyl Silsesquioxane) film.
- HSQ Hydrogen Silsesquioxane
- Hydrogen Silsesquioxane Hydrogen Silsesquioxane
- MSQ Metal Silsesquioxane
- JSR-LKD Trade Mark
- ALCAP Trade Mark
- NCS Trade Mark
- IPS Trade Mark
- HOSP Trade Mark
- organic polymer film SiLK (Trade Mark), Flare (Trade Mark)
- SiOCH SiOC
- Black Diamond Trade Mark
- C ORAL Trade Mark
- Aurora ULK Trade Mark
- Orion Traffic Mark
- insulating films containing organic substances Typical examples thereof include a film in which a plurality of these insulating films are stacked, or a film in which the composition and density of these insulating films are changed in the film thickness direction.
- the wiring interlayer insulating film 314 is a low dielectric constant insulating film using a cyclic organic siloxane raw material containing at least silicon, oxygen, carbon, and hydrogen.
- the thickness of the wiring interlayer insulating film 314 is preferably about 500 to 2000A.
- a layer having excellent adhesion may be inserted into the wiring interlayer insulating film 314 by changing the raw material partial pressure during plasma excitation.
- a SiOCH layer that may be exposed during Cu-CMP with a low carbon content may be inserted on top.
- the wiring interlayer insulating film 3114 is formed using the three-membered cyclic organosiloxane of the formula (1).
- SiO, SiON, SiC, SiCN, etc. can be used for the hard mask film.
- the film thickness is preferably about 500-2000A.
- SiH, TEOS, trimethylsilane, or an acid gas added thereto is added.
- via holes 316 are formed in the via interlayer insulating film 313, the wiring interlayer insulating film 314, and the node mask 315 by patterning and dry etching using a photoresist. To do.
- wiring grooves 317 are transferred and formed in the hard mask 315 by patterning and dry etching using a photoresist.
- the plasma ashing process is efficiently and completely performed by using O plasma ashing.
- the photoresist can be removed. At this time, since the wiring interlayer insulating film 314 is not etched, the side wall of the wiring trench to be formed later is exposed to O plasma.
- a wiring groove 318 is formed in the wiring interlayer insulating film 314 by dry etching using the hard mask film 315 as a mask.
- the dry etching method for the wiring interlayer insulating film at this time will be described in detail below.
- CF 3 tetrafluorocarbon
- Ar argon
- N 2 nitrogen
- O 2 oxygen
- Etching can be performed using a parallel plate type dry etching apparatus using an etching gas mixed at an arbitrary ratio. Specifically, using a parallel plate type 8-inch etching device, the gas flow ratio ArZN / CF / O
- GAP substrate distance
- pressure 50mTorr 50mTorr
- upper electrode frequency 60MHz 60MHz
- upper electrode powerl000W lower electrode frequency 13.56MHz
- lower electrode powerlOOW lower electrode powerlOOW.
- the modified layer 319 is formed by performing an oxidation treatment on the etched side wall.
- the photoresist for groove patterning has already been completely removed. Therefore, the modification treatment can be performed under conditions preferable to modification.
- the treatment time it is preferable to set the treatment time to a force of 5 to 15 seconds, depending on the plasma conditions. Excessive oxidation treatment is preferable because it promotes oxidation of the trench sidewall.
- the distance between substrates (GAP) 30mm, pressure 10mTorr, upper electrode frequency 60MHz, upper electrode power 600W, lower electrode frequency 13.56MHz, lower electrode power 100W, treatment with oxygen gas only for 5 seconds be able to.
- a mixed gas such as O ZAr may be used as a gas system for performing O plasma irradiation.
- the condition is that the pressure is 20 mTorr, the upper electrode frequency is 60 MHz, the upper electrode power is 500 W, the lower electrode frequency is 13.56 MHz, and the lower electrode powerlOOW is 5 seconds only with oxygen gas.
- UV treatment using ozone or annealing treatment using oxygen gas may be used.
- a diagram in which the modified layer is formed only on the side wall of the wiring interlayer insulating film 314 is illustrated as a typical example, but the modified layer is formed in other portions. It's okay.
- a modified layer may also be formed on the via interlayer insulating film at the bottom of the trench, the sidewall of the via hole, or the like.
- the modified layer formed on the trench side wall is thinly formed with a high density of 20 nm or less.
- the wiring interlayer insulating film 314 does not contain any other siloxane structure.
- a modified layer as thick as 30 to 50 nm is formed. This result also shows that it is preferable to apply the first insulating film of the present invention to the wiring layer insulating film 314 in order to make the first insulating film have a low dielectric constant and high insulating properties. .
- the modified layer is formed at the connection interface between the first insulating film and the metal wiring as described above, the adhesion between the metal wiring and the wiring interlayer insulating film can be improved. This is because there is no modified layer and the adhesion of the noria metal to the modified layer is improved compared to the structure. Moreover, in the composition of the modified layer, the number of oxygen atoms per unit volume is larger than the number of carbon atoms, so that the adhesion with the noria metal is improved. Since the modified layer is formed as described above, it does not contain fluorine.
- This oxidation process is performed in a state where Cu under the via interlayer insulating film is exposed.
- perform oxidation treatment without opening the insulating barrier film at the bottom of the via interlayer insulation film, and then etch back. It is also possible to perform an opening with.
- the noble metal 310b and the metal wiring 31 lb are embedded in the dual damascene trench, and the redundant wiring is removed by CMP to form a dual damascene wiring.
- FIG. 5 shows a wiring resistance wiring capacity plot (RC plot).
- the R–C plots for “with modified layer” and “without modified layer” are almost the same, indicating that the wiring performance is the same regardless of the presence or absence of the modified layer. That is, by using a cyclic SiOCH film having more carbon atoms than silicon atoms as a raw material, the leakage current can inevitably be reduced, and by forming the modified layer of the present invention, insulation reliability can be maintained while maintaining wiring performance. It can be seen that the sex can be secured.
- FIG. 6 shows the result of the compositional analysis between the wirings of the multilayer wiring fabricated in this way from TEM-EELS (Transmission Electron Microscop- er Electron Energy Loss Spectroscopy).
- This TEM-EELS can detect many elements from Li and B to 3d elements such as Cu.
- the elemental mapping of the EELS spectrum which also releases the sample force, is performed on the TEM cross section, and the modification formed at the interface between the first insulating film and the wiring metal or the interface between the first insulating film and the second insulating film The composition of the layer can be confirmed.
- a field emission electron microscope (JEM2100F, manufactured by JEOL Ltd.) EELS: GATAN GIF “Tridiem” is used as the TEM-EELS measuring apparatus.
- the measurement conditions were an acceleration voltage of 200kV, a sample absorption current of 10-9A, and a beam spot size of lnm ⁇ , and analysis was performed using spectral imaging in STEM (scanning TEM) mode.
- Fig. 6 (a) (with modified layer), peaks with increased O intensity (au) were observed at 50 nm and -50 nm, whereas in Fig. 6 (b) (without modified layer). , Such peaks are not observed at the 50 nm and 150 nm positions. From this result, it can be seen that when the modified layer is formed, a modified layer of about 15 nm is formed on the side wall.
- a wiring interlayer insulation film is formed on a silicon substrate, and a pseudo oxidation treatment is performed to evaluate the modified layer formed on the surface.
- XRR X-Ray Reflection: X-ray reflectivity measurement
- the inside of the wiring interlayer insulating film at this time is an insulating film including a cyclic siloxane structure containing at least silicon, oxygen, and carbon. From the result of TEM-EELS, the insulating film per unit volume It was found that the carbon atom weight of the carbon was more than twice the oxygen atom weight. On the other hand, from the result of TEM-EELS, it was found that the ratio of the carbon atom weight and the oxygen atom weight was reversed in the modified layer of the first embodiment.
- the semiconductor device manufacturing method and the semiconductor device of the present invention it is possible to achieve a reduction in the dielectric constant of the interlayer insulating film and an excellent insulation reliability at the same time.
- the high adhesion makes it possible to improve the performance of the wiring and to form a high-speed, low-power consumption LSI with high reliability.
- FIGS. Examples of the structure of the dual damascene wiring thus formed are shown in FIGS.
- the lower layer metal wiring is composed of Ding & 7 Ding & Normetal 310 & and CuAl wiring 311a.
- the CuAl wiring 311a contains Cu as a main component and contains A1 of 1.2 atm% or less inside.
- the upper surface of the lower metal wiring is covered with an insulating barrier film 312a.
- a SiCN film having a relative dielectric constant of 4.9 formed by a plasma CVD method is used.
- the via interlayer insulating films 313a and 313b Aurora-ULK (Trade Mark) or Black Diamond (Trade Mark) formed by the plasma CVD method is used.
- the wiring interlayer insulating film 314 an annular SiOCH film having a relative dielectric constant of 2.37 as shown in the formation method in the first embodiment is used.
- the upper layer wiring material has a TaZTaN noria metal 310b and CuAl wiring 31 lb force.
- This TaZTaN noria metal is formed by PVD method.
- Cu A1 wiring 3 l ib is mainly composed of Cu and contains A1 of 1.2 atm% or less inside.
- the upper surface of the upper wiring layer is covered with an insulating barrier film 312b.
- the insulating barrier film 312b was made of a SiCN film having a relative dielectric constant of 4.9 formed by a plasma CVD method.
- the modified layer 319 is formed on the side wall of the groove and is formed so as to surround the periphery with metal wiring.
- FIG. 7B shows a structure in which a hard mask film 315 for protecting the surface of the wiring interlayer insulating film at the time of Cu-CMP is further inserted in the structure of FIG. 7A.
- the hard mask film include a silicon oxide film, a silicon carbide film, a silicon carbon nitrogen film, and the like, and a film having a higher relative dielectric constant than the insulating film 214 between wiring layers and excellent in mechanical strength is preferable. Therefore, as the hard mask film 315, an SiOCH film having a relative dielectric constant of about 3.0 may be used.
- the rest of the structure is the same as in Fig. 7 (a), and is omitted.
- FIG. 7 (c) shows a structure in which etch stop films 320a and 320b are further inserted into the structure of FIG. 7 (b).
- the etch stop film is a film provided to improve the workability of the dual damascene-shaped wiring grooves and via holes. By using such an etch stop film, it is possible to reduce variations in the wiring groove depth. become.
- the material of the etch stop film may be appropriately changed depending on the processed! / And material.
- SiO film, SiN film, SiC film, SiCN film, SiOC At least one of a film, a SiOCH film, a film containing an organic substance in these films, a film containing an organic substance as a main component, and a film containing SiO as a main component containing an organic substance can be used.
- FIG. 8 (a) shows an adhesive layer 321a, 321b formed by utilizing the partial pressure dependence of the cyclic organic siloxane raw material in the interlayer insulating film 314 of the structure of FIG. 7 (a). It is a structure in which is inserted.
- This adhesion layer is an insulating film containing silicon, oxygen, carbon, and hydrogen, which is made of a layer having a low hydrocarbon component formed under a low partial pressure condition, and has a thickness of about 500 to 3000 A.
- the dielectric constant is preferably 3.0 or less.
- the wiring interlayer insulating film 314 is a low dielectric constant insulating film containing a siloxane structure containing at least silicon, oxygen, carbon, and hydrogen.
- FIG. 8B shows a structure in which a hard mask film 315 for protecting the surface of the wiring interlayer insulating film at the time of Cu-CMP is further inserted in the structure of FIG. 8A.
- the hard mask film there are a silicon oxide film, a silicon carbide film, a silicon carbon nitrogen film, etc., and a film having a higher relative dielectric constant and superior mechanical strength than the inter-wiring insulating film 314 is preferable. Therefore, as the hard mask film 315, an SiOCH film having a relative dielectric constant of about 3.0 may be used.
- the rest of the structure is the same as in Fig. 8 (a), and is omitted.
- FIG. 8 (c) shows a structure in which etch stop films 320a and 320b are inserted into the structure of FIG. 8 (b).
- the etch stop film is a film provided to improve the dual damascene wiring trench and via hole additivity.
- the etch stop film can be appropriately changed according to the material to be processed.
- At least one of two films, SiN film, SiC film, and SiCN film can be used.
- FIG. 9 (a) shows that the via interlayer insulating films 313a and 313b are SiOCH films containing at least silicon, oxygen, carbon and hydrogen, and the via interlayer insulating film 313b and the wiring interlayer insulating film 314 are formed.
- the structure formed continuously is shown.
- the via interlayer insulating film 313b is formed by changing the raw material partial pressure during plasma excitation and setting a low partial pressure condition
- the wiring interlayer insulating film 314 is formed by setting the high partial pressure condition.
- the via interlayer insulating film 313b and the wiring interlayer insulating film 314 in FIG. 9A can have a continuous structure.
- the via interlayer insulating film and the wiring interlayer insulating film are formed by using two or more types of siloxane raw materials containing both side chains having 3 or more carbon atoms and bull groups, and changing the ratios of the respective raw materials.
- the via interlayer insulation films 313a and b have a CZSi ratio of about 1.4 and a dielectric constant of 2.7
- the wiring interlayer insulation film has a CZSi ratio of about 2.9 and a dielectric constant of 2.4. can do .
- the modified layer is formed so as to completely surround the periphery of the wiring except the upper surface.
- each of the wiring interlayer insulating film and the via interlayer insulating film is an insulating film including a siloxane structure containing at least silicon, oxygen, and carbon, and the number of carbon atoms in the insulating layer is equal to the wiring interlayer insulating film 314, It is characterized in that the via interlayer insulating film 313 decreases in order.
- FIG. 9B shows a structure in which a hard mask film 315 for protecting the surface of the wiring interlayer insulating film at the time of Cu-CMP is further inserted in the structure of FIG. 9A.
- the hard mask film there are a silicon oxide film, a silicon carbide film, a silicon carbon nitrogen film, etc., and a film having a higher relative dielectric constant and superior mechanical strength than the inter-wiring insulating film 314 is preferable. Therefore, as the hard mask film 315, an SiOCH film having a relative dielectric constant of about 3.0 may be used.
- the via interlayer insulating film, the wiring interlayer insulating film, and the hard mask film use two or more types of siloxane raw materials containing both a side chain having 3 or more carbon atoms and a vinyl group, and changing the ratio of each raw material. Form a film.
- the via interlayer insulating film 313 has a CZSi ratio of about 1.4 and a relative dielectric constant of 2.7
- the wiring interlayer insulating film has a CZSi ratio of about 2.9 and a relative dielectric constant of 2.4. be able to.
- an SiOCH film having a CZSi ratio of 1.2 and a relative dielectric constant of 3.0 can be formed as the hard mask film 315.
- the modified layer is formed so as to surround the entire periphery of the wiring except the upper surface.
- all of the wiring interlayer insulating film, via interlayer insulating film, and hard mask film are insulating films including a siloxane structure including at least silicon, oxygen, and carbon, and the number of carbon atoms in the insulating layer
- insulating films including a siloxane structure including at least silicon, oxygen, and carbon are insulating films including a siloxane structure including at least silicon, oxygen, and carbon, and the number of carbon atoms in the insulating layer.
- FIG. 9 (c) shows a structure in which etch stop films 320a and 320b are inserted into the structure of FIG. 9 (b).
- the etch stop film is a film provided to improve the dual damascene wiring trench and via hole additivity.
- the etch stop film is the material you want to process Depending on the situation, the material should be changed as appropriate. For example, as an etch stop film, SiO
- At least one of 2 films, SiN films, SiC films, and SiCN films can be used.
- At least a cyclic organosiloxane raw material is supplied to a reaction chamber, and an insulating film including a cyclic siloxane structure is formed by plasma vapor deposition. Then, by forming a suitable modified layer for this insulating film, the adhesion between the insulating film and the metal wiring can be improved.
- the multilayer wiring structure formed on the semiconductor substrate formed with the semiconductor element according to the second embodiment will be described in detail.
- a barrier metal 310a, a metal wiring 311a, and an insulating barrier film 312 are laminated on a semiconductor substrate (not shown) on which a semiconductor element is formed, and via interlayer insulation is formed thereon.
- An edge film 313 is formed.
- the via interlayer insulating film 313 is an insulating film including a cyclic organosiloxane structure containing at least silicon, oxygen, carbon, and hydrogen.
- a modified layer 319a is formed by subjecting the via interlayer insulating film 313 to surface oxidation treatment.
- a preferable oxidation treatment condition As a preferable oxidation treatment condition,
- the O plasma irradiation uses a parallel plate type plasma CVD apparatus, and is performed between the substrates.
- GAP 10mm, pressure 2 ⁇ 7Torr, upper electrode frequency 13 ⁇ 56MHz, upper electrode power 200W, oxygen gas alone for 5 seconds. At this time, O plasma ashing is performed.
- the O-based system uses a mixed gas of rare gas such as He, Ar, Ne, Xe, and Rn and O, which can be O alone.
- oxidation treatment conditions other than this may be the same method as described in the first embodiment.
- a wiring interlayer insulating film 314 is formed on the via interlayer insulating film 313.
- a hard mask film 315 is formed.
- the wiring interlayer insulating film 314 an insulating film containing a cyclic organosiloxane structure containing at least silicon, oxygen, carbon, and hydrogen is used, and the film thickness is preferably about 500 to 2000A.
- a layer having excellent adhesion may be inserted into the wiring interlayer insulating film 314 by changing the raw material partial pressure during plasma excitation.
- a SiOCH layer with a low carbon component which may be exposed during Cu CMP, may be inserted on top.
- this cyclic organosiloxane one having a structure having a three-membered ring or a four-membered ring force is used, and an inert carrier gas such as He, Ar, Ne, Xe, Rn or the like is used in the reaction chamber. Film formation can be performed by supplying and applying high frequency power.
- the wiring interlayer insulating film 314 is formed using the three-membered cyclic organosiloxane of the formula (1).
- SiO, SiON, SiC, SiCN, etc. can be used for the hard mask film
- the film thickness is preferably about 500-2000A.
- the first insulating film is the wiring interlayer insulating film 314, and the second insulating film is the via interlayer insulating film 313. Further, by forming the modified layer 319a as described above, the adhesion between the via interlayer insulating film 313 and the wiring interlayer insulating film 314 can be improved.
- a dual damascene trench 318 is formed in the wiring interlayer insulating film 314 and the via interlayer insulating film 313 by patterning and dry etching using a photoresist.
- the etching conditions at this time are the same as those described in the first embodiment, and the force to be omitted is formed. Since the modified layer 319a is formed, the modified layer serves as an etching stop layer. It becomes possible to reduce the variation of the wiring groove depth in the wafer surface.
- the modified layer 319b is formed by performing an oxidation treatment on the etched side wall.
- the oxidation treatment can be performed under conditions favorable for modification.
- the noble metal 310b and the metal wiring 31 lb are embedded in the dual damascene trench, and the surplus wiring is removed by CMP to form a dual damascene wiring. .
- the inside of the wiring interlayer insulating film 314 has a ring containing at least silicon, oxygen, and carbon. It is an insulating film containing a siloxane structure. From the results of the TEM-EELS analysis, the modified layer 319a is formed at the interface between the wiring interlayer insulating film 314 and the via interlayer insulating film 313, and the modified layer 319b is formed at the interface between the wiring interlayer insulating film 314 and the metal wiring 31 lb. I was able to confirm. It was also found that the amount of oxygen atoms per unit volume in the modified layers 319a and 319b was more than twice the amount of carbon atoms. In the second embodiment, the thickness of the modified layers 319a and 319b is 20 nm or less.
- the method for manufacturing a semiconductor device of the present invention and the semiconductor device it was possible to simultaneously achieve a low dielectric constant and a high insulation reliability of the interlayer insulating film.
- the high adhesion has improved the wiring performance, and it has become possible to form high-speed, low-power consumption LSIs with high reliability.
- the lower layer metal wiring is composed of TaZTaN barrier metal 310 & and 0 ⁇ 1 wiring 311a.
- the CuAl wiring 311a contains Cu as a main component and contains A1 of 1.2 atm% or less inside.
- the upper surface of the lower metal wiring is covered with an insulating barrier film 312a.
- a SiCN film having a relative dielectric constant of 4.9 formed by a plasma CVD method is used.
- Via interlayer insulating films 313a and 313b are insulating films including a cyclic organosiloxane structure containing at least silicon, oxygen, carbon, and hydrogen, and include a siloxane structure consisting of a three-membered ring or a four-membered ring. It is a membrane.
- a cyclic SiOCH film having a relative dielectric constant of 2.37 formed using a siloxane structure of the formula (1) as a raw material is used.
- the upper layer wiring material has TaZTaN noria metal 3101) and 0 ⁇ 1 wiring 31 lb force, and the Ta / TaN noria metal is formed by the PVD method.
- This CuAl wiring 31 lb is mainly composed of Cu and contains A1 of 1.2 atm% or less inside.
- the upper surface of the upper wiring is covered with an insulating barrier film 312b, and here, a SiCN film having a relative dielectric constant of 4.9 formed by a plasma CVD method is used.
- the modified layer 319a The modified layer 319b is formed at the interface between the via interlayer insulating film and the wiring interlayer insulating film on the trench sidewall and the trench bottom.
- FIG. 11 (b) shows a structure in which a hard mask film 315 for protecting the surface of the wiring interlayer insulating film is further inserted in the structure of FIG. 11 (a) during Cu-CMP.
- the hard mask film there are a silicon oxide film, a silicon carbide film, a silicon carbon nitrogen film, etc., and a film having a relative dielectric constant higher than that of the wiring interlayer insulating film 214 and excellent in mechanical strength is preferable. Therefore, as the hard mask film 315, a SiOCH film having a relative dielectric constant of about 3.0 may be used.
- the other structures are the same as those in FIG.
- FIG. 12 (a) shows an adhesion layer 321a, 321b formed by utilizing the partial pressure dependence of the cyclic organic siloxane raw material in the interlayer insulating film 314 of the structure of FIG. 11 (a).
- the adhesion layer is an insulating film containing silicon, oxygen, carbon, and hydrogen, which is formed of a low hydrocarbon component layer formed under a low partial pressure condition, and has a film thickness of about 1000 to 3000 A and a relative dielectric constant of 3. It is preferably 0 or less.
- FIG. 12 (b) shows a structure in which a hard mask film 315 for protecting the surface of the wiring interlayer insulating film is further inserted in the structure of FIG. 12 (a) during Cu-CMP.
- the hard mask film there are a silicon oxide film, a silicon carbide film, a silicon carbon nitrogen film, etc., and a film having a relative dielectric constant higher than that of the wiring interlayer insulating film 314 and excellent in mechanical strength is preferable. Therefore, as the hard mask film 315, a SiOCH film having a relative dielectric constant of about 3.0 may be used.
- Other structures are the same as those in FIG.
- a metal 310a, a metal wiring 311a, and an insulating barrier film 312b were stacked on the semiconductor substrate (not shown) on which the semiconductor element is formed. Further, a via interlayer insulating film 313, a wiring interlayer insulating film 314, and hard mask films 315a and 315b were formed on the insulating barrier film 312b.
- the first insulating film is the wiring interlayer insulating film 314, and the second insulating film is the via interlayer insulating film 313.
- the metal wiring 311a was formed by forming a seed layer by sputtering using a CuAl (Al: 1.2 atm%) target and embedding Cu by an electrolytic plating method.
- the insulating barrier film 312b is a SiCN film having a relative dielectric constant of 4.9 formed by a plasma CVD method, and its thickness is 300A. Prior to the formation of the insulating barrier film 312b, plasma NH irradiation or SiH gas irradiation was performed as a reduction treatment of the copper surface.
- the via interlayer insulating film 313 is an insulating film containing at least silicon, oxygen, and carbon, and has a thickness of 1200 A.
- the material used was AuroraULK (Trade Mark) with a high relative dielectric constant of 2.8.
- the via interlayer insulating film 313 includes, for example, NCS (Trade Mark), IP S (Trade Mark), HOSP (Trade Mark), Black Diamond (Trade Mark), C ORAL (Trade Mark ) Etc. may be used.
- the film forming conditions may be changed or a process such as UV curing or EB curing may be used to increase the strength.
- the wiring interlayer insulating film 314 is an insulating film formed by a plasma CVD method using a He carrier gas, using a raw material having a siloxane structure of the formula (1), and its film thickness is 1100 A.
- 4 nm adhesion was inserted into the lower layer by changing the raw material partial pressure during plasma excitation.
- the raw material partial pressure at the time of forming the adhesion layer was set to lOPa, whereas at the time of forming the wiring interlayer insulating film 314, it was set to 50 Pa.
- the hard mask film 315a is an insulating film containing at least silicon, oxygen, and carbon, and has a film thickness of 300A. In this embodiment, specifically, the hard mask film 315a has a relative dielectric constant. A Black Diamond (Trade Mark) with a rate of 3.0 was used.
- the hard mask film 315a is not limited to this. For example, NCS (Trade Mark), IPS (Trade Mark), HOSP (Trade Mark), Black Diamond (Trade Mark), CORAL (Trade Mark) ⁇ AuroraULK (Trade Mark) may be used.
- the film forming conditions may be changed to increase the strength, or a process such as UV curing or EB curing may be used.
- the hard mask film 315b is an SiO film formed by a plasma CVD method, and its film thickness is
- Each of the hard mask films 315a and 315b was irradiated with plasma He in order to improve the adhesion with the lower layer film.
- plasma treatment with an inert gas may be appropriately performed as necessary in order to improve the adhesion between the insulating films.
- via holes were formed in the via interlayer insulating film 313, the wiring interlayer insulating film 314, and the hard mask films 315a and 315b by patterning and dry etching using a photoresist.
- the via hole was cleaned by an organic cleaning process, and then heat-treated at 300 ° C for 1 minute. This is because the organic amine component incorporated into the insulating film is removed by heat treatment to reduce the deterioration of the embedded organic film and resist boiling.
- the organic film 5000A is embedded in the via hole, flattened by etch back once, and then the organic film 321 is again applied 2500A, 300 Curing treatment was performed for 1 minute at ° C.
- a low-temperature oxide film 322 was formed thereon.
- the low-temperature oxide film 322 was formed by the plasma CVD method, and the substrate temperature at that time was set to 200 ° C. or lower.
- an antireflection film (ARC) 323 and a photoresist 324 were formed. By adopting such a structure, resist boiling can be avoided even when an ArF photoresist is used.
- wiring grooves 317 were transferred and formed in the hard mask film 315 by patterning and dry etching using a photoresist.
- photo cash register Stroke 324 and the like were completely removed by an ashing process using O plasma ashing.
- a wiring trench 318 was formed in the wiring interlayer insulating film 314 by dry etching using the hard mask film 315 as a mask.
- P) 35mm, pressure 50mTorr, upper electrode frequency 60MHz, upper electrode powerlOOOW, lower electrode frequency 13.56MHz, lower electrode powerlOOW.
- a modified layer 319 was formed by performing an oxidation treatment on the etched side wall.
- the oxidation treatment conditions at this time were performed by O plasma irradiation.
- the modified layer on the trench side wall has a high density. From TEM-EELS, a modified layer of about lOnm is formed. It was confirmed that In addition, it was confirmed that the modified layer had fewer carbon atoms and more oxygen atoms per unit volume than the wiring interlayer insulating film 314. On the other hand, it was confirmed that a modified layer of about 40 nm was formed on the side wall of the via interlayer insulating film 313 at the bottom of the wiring trench.
- a noble metal 310b and a metal wiring 31 lb were embedded in the dual damascene trench, and excess wiring was removed by CMP to form a dual damascene wiring.
- a semiconductor substrate on which a semiconductor element is formed (see FIG. A noria metal 221a, a metal wiring 220a, and an insulating barrier film 218a are formed on (not shown), and a wiring interlayer insulating film 219a is formed thereon.
- the first insulating film and the second insulating film are integrated into the wiring interlayer insulating films 219a to 219e.
- the wiring interlayer insulating film 219a includes a siloxane structure containing silicon, oxygen, and carbon, and the number of carbon atoms in the siloxane structure is larger than the number of silicon atoms. Further, a modified layer 319a having a smaller number of carbon atoms per unit volume and a larger number of oxygen atoms is formed at the interface with the wiring interlayer insulating film 219a in contact with the metal wiring than in the wiring interlayer insulating film. The thickness is controlled to about 10 to 20 nm.
- the metal wiring material is mainly composed of Cu, and metal elements other than Cu may be included in the member made of Cu in order to improve the reliability of the metal wiring material.
- Metal other than Cu The element may be formed on the upper surface or side surface of Cu.
- Cu was formed by the electrolytic plating method using a 400 A thick Cu layer formed by the PVD method as a seed layer.
- the Cu layer formed by this PVD method contains less than 1.2atm% of A1 inside.
- the insulating barrier film is composed of a SiCN film, and the film thickness is 300 A, which is formed by the plasma CVD method.
- the wiring interlayer insulating film 219a is a cyclic SiOCH film formed by plasma vapor deposition using the cyclic organosiloxane raw material of formula (1), and has a relative dielectric constant of 2.4 and a thickness of It was 2500 A including the via interlayer.
- the metal wiring 220a and the barrier metal 221a are embedded in the dual damascene trench that also forms such an interlayer insulating film force.
- Ta (15 nm) / TaN (5 nm) (formed by PVD method) is applied to the noria metal film 221a.
- the metal wiring member was formed by PVD using a Cu target containing 1.2 atm% A1, and Cu was formed by plating.
- each wiring layer is 170 nm for Ml (the sign of each constituent member is a) to M5 (the sign of each constituent member is e), and 300 nm is M6 (the sign of each constituent member is f). did.
- the noria metals 221b to 221e have the same configuration as the barrier metal 221a
- the metal wirings 220b to 220e have the same configuration as the metal wiring 220a.
- the insulating barrier films 218b to e have the same configuration as the insulating barrier film 218a
- the wiring interlayer insulating films 219b to e have the same configuration as the wiring interlayer insulating film 219a
- the modified layers 319b to e Break It is the same composition as the stratified layer 319a.
- a structure in which a hard mask film or the like is inserted may be used.
- the hard mask film a silicon oxide film, a silicon carbide film, a silicon carbon nitrogen film, or the like can be used, and a film having a higher relative dielectric constant than the wiring interlayer insulating film 213 and excellent in mechanical strength is used. It is preferable. Therefore, a SiOCH film having a relative dielectric constant of about 3.0 may be used as the hard mask film.
- A1 was used for the upper layer wiring, and Ti / TiN225a, Al-Cu226, and TiZTiN225b were formed by the PVD method.
- the thickness of each metal film was TiZTiN225 force of about 0.3 ⁇ m, Al—Cu226 force of 5 m, and TiZTiN225b force of 3 ⁇ m. At this time, metal was continuously embedded in the grooved via hole.
- the upper layer was covered with a passivation film.
- the wafer was diced, the chip was cut out, mounted on a ceramic package, and sealed with grease.
- the chip size was 25 mm x 25 mm, and a temperature cycle test from -65 ° C to 150 ° C was conducted up to 1000 cycles.
- adhesion was improved by the modified layer, and no peeling was observed in 50 chips.
- the semiconductor device in which the modified layer was not formed it was confirmed that 2 chips were generated in the sample in which the angular force of the chip slightly peeled off due to poor adhesion.
- Example 3 An embodiment in which multilayer wiring is formed on a semiconductor substrate on which a semiconductor element is formed and a modification process using nitrogen plasma is performed on the insulating film will be described in detail below. Note that the manufacturing method of the semiconductor device is the same as that in Example 1 except for the reforming process conditions, and is omitted.
- the first insulating film is the wiring interlayer insulating film 314, and the second insulating film is the via interlayer insulating film 313.
- distance between substrates (GAP) 30 mm, pressure 10 mTorr, upper electrode frequency 60 MHz, upper electrode power 600 W, lower electrode frequency 13.5 6 MHz, lower electrode powerlOOW, only nitrogen gas And processed for 5 seconds.
- the modified layer on the trench side wall has a high density. From TEM-EELS, a modified layer of about 10 nm is formed. It was confirmed that The reformed layer is composed of a SiOCN film, which has fewer carbon atoms per unit volume and more oxygen atoms than the wiring interlayer insulating film 314. Decreased carbon content and replaced with nitrogen
- Comparative Example 1 the state of the sidewall when a semiconductor device is formed by using a raw material of linear SiOCH of formula (3) by plasma vapor deposition using oxygen-oxidized plasma with oxygen will be described. .
- the number of carbon atoms in the siloxane structure inside the wiring interlayer insulating film and via interlayer insulating film is approximately the same as the number of silicon atoms.
- FIG. 13 shows the result of TEM-E ELS analysis of the composition of the copper multilayer wiring formed on the linear SiOCH film.
- a modified layer having a thickness of about 40 nm is formed on the side wall, which is twice or more thicker than the modified layer of the present invention.
- the reason for this is that the elimination of carbon rapidly progressed because the film did not contain vinyl groups or hydrocarbon groups having 3 or more carbon atoms.
- the film structure is a random Si—O structure, it is dense and nano-order. This is because a thickness of the modified layer cannot be formed.
- a suitable oxidation condition is selected, a high-density modified layer is not formed, and the oxidation proceeds to the inside of the film.
- N ZO ZC F is mixed as the etching gas for the annular SiOCH film
- Wiring grooves were formed with a lower electrode frequency of 60MHz, an upper electrode powerl000W, a lower electrode frequency of 13.56MHz, and a lower electrode powerl50W.
- the modified layer is formed in the thus formed wiring trench by O plasma treatment.
- the reason for this is that the modification of the trench sidewall cannot be sufficiently performed due to deposits during etching. That is, in this case, the modified layer of the present invention was not formed. Therefore, when the etching conditions are changed, suitable reforming conditions change as appropriate, and can be dealt with by changing the reforming conditions.
- Example 1 As Reference Example 2, in Example 1, a wiring groove is opened by using the groove resist as a mask, and the wiring layer is formed by simultaneously performing the ashing treatment of the groove resist and the modification treatment of the groove side wall with O plasma.
- the resist ashing treatment conditions at this time were performed by O plasma irradiation.
- O plasma irradiation was performed by O plasma irradiation.
- the groove side wall is the same as in Example 1.
- the oxygen plasma is excessively irradiated for 8 times the processing time.
- the present invention relates to a wiring structure of multilayer wiring that requires both improved capacitance between wiring and high insulation reliability by forming a modified layer, and a manufacturing method thereof. For example, it can be applied to anything and is not limited in any way.
- CMOS circuit which is a field of use as the background of the invention made by the present inventors, has been described in detail, but the present invention is not limited to this.
- DRAM Dynamic Random Access Memory
- SRAM Static Random Access Memory
- flash memory FRAM (Ferro Electric Random Access Memory)
- MRAM Magnetic Random Access Memory
- resistance change memory etc.
- the present invention can also be applied to a semiconductor device having a logic circuit such as a microprocessor, a microprocessor, or a mixed-type semiconductor device in which they are listed simultaneously.
- the present invention can also be applied to a semiconductor device, an electronic circuit device, an optical circuit device, a quantum circuit device, a micromachine, etc. having an embedded alloy wiring structure at least partially.
- the modified layer according to the present invention can also be confirmed from the finished product. Specifically, the composition of the modified layer of the wiring interlayer film can be confirmed by analyzing the wiring interlayer insulating film around the metal wiring by TEM-EELS measurement. Similarly, it can be confirmed by analyzing the interface between the via interlayer insulating film and the wiring interlayer insulating film by TEM-EELS measurement.
- the semiconductor manufacturing apparatus of the present invention includes, for example, first and second insulating films, hard mask films, and the like.
- Film forming means capable of forming a film
- vacuum chamber capable of modifying an insulating film
- etching means capable of etching treatment
- photolithographic means capable of photolithography processing
- control of each process are possible Control means.
- control means preferably includes a microcomputer in which a program for controlling the groove forming step, the photoresist removing step, and the modifying step is stored.
- control means preferably further stores a program for forming the first insulating film by the plasma processing sequence in the insulating film forming step.
- This plasma treatment sequence is preferably an oxygen plasma treatment sequence or a nitrogen plasma treatment sequence.
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Abstract
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US12/299,375 US8043957B2 (en) | 2006-05-17 | 2007-05-16 | Semiconductor device, method for manufacturing semiconductor device and apparatus for manufacturing semiconductor |
US13/238,796 US8278763B2 (en) | 2006-05-17 | 2011-09-21 | Semiconductor device |
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US8278763B2 (en) | 2012-10-02 |
US20120013023A1 (en) | 2012-01-19 |
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