JP7116619B2 - 半導体装置およびその製造方法 - Google Patents
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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Description
実施の形態1に係る半導体装置の主要部分について説明する。
実施の形態1では、第1配線と第2配線とを備えた半導体装置の基本的構造について説明した。ここでは、その基本構造を、3層以上の多層配線構造に適用した半導体装置の主要部分の一例について説明する。
Claims (9)
- 第1層間絶縁膜の第1溝に形成された第1配線と、
前記第1配線の上方に配置され、シリコン酸炭化膜からなる第2層間絶縁膜の第2溝に形成された第2配線と、
前記第1配線と前記第2層間絶縁膜との間に形成された第1キャップ絶縁膜と、
前記第1キャップ絶縁膜と前記第2層間絶縁膜との間に形成された、シリコン酸炭化膜からなる第1欠陥形成阻止膜と、
前記第2層間絶縁膜と前記第2配線との間に形成された、シリコン酸炭化膜からなる第2欠陥形成阻止膜と、
を備え、
シリコンと酸素との結合に対応する赤外線吸収強度に対するシリコンと水素との結合に対応する赤外線吸収強度の比を存在比とすると、
前記第1欠陥形成阻止膜における前記存在比は、前記第2層間絶縁膜における前記存在比よりも小さく、
前記第2欠陥形成阻止膜における前記存在比は、前記第2層間絶縁膜における前記存在比よりも小さい、半導体装置。 - 前記第1欠陥形成阻止膜は、前記第1配線の上面と対向するように形成され、
前記第2欠陥形成阻止膜は、前記第2配線の両側面および下面と対向するように形成された、請求項1記載の半導体装置。 - 前記第1配線の下方に配置された半導体基板と、
前記半導体基板を覆うように、前記半導体基板と前記第1層間絶縁膜との間に形成されたコンタクト層間絶縁膜とを備え、
前記コンタクト層間絶縁膜は、第1誘電率を有し、
前記第1層間絶縁膜は、前記第1誘電率よりも低い第2誘電率を有し、
前記第2層間絶縁膜は、前記第1誘電率よりも低い第3誘電率を有する、請求項1記載の半導体装置。 - 前記第2配線の上方に配置され、第3層間絶縁膜の第3溝に形成された第3配線と、
前記第3配線の上方に配置され、第4層間絶縁膜の第4溝に形成された第4配線と、
前記第3配線と前記第4層間絶縁膜との間に形成された第3欠陥形成阻止膜と、
前記第4層間絶縁膜と前記第4配線との間に形成された第4欠陥形成阻止膜と
を備え、
前記第3欠陥形成阻止膜における前記存在比は、前記第4層間絶縁膜における前記存在比よりも小さく、
前記第4欠陥形成阻止膜における前記存在比は、前記第4層間絶縁膜における前記存在比よりも小さい、請求項3記載の半導体装置。 - 前記第3層間絶縁膜は、前記第1誘電率よりも低く、前記第2誘電率および前記第3誘電率よりも高い第4誘電率を有し、
前記第4層間絶縁膜は、前記第1誘電率よりも低く、前記第2誘電率および前記第3誘電率よりも高い第5誘電率を有する、請求項4記載の半導体装置。 - 前記第3欠陥形成阻止膜は、前記第3配線の上面と対向するように形成され、
前記第4欠陥形成阻止膜は、前記第4配線の両側面および下面と対向するように形成された、請求項4記載の半導体装置。 - 半導体基板を覆うように、第1溝を有する第1層間絶縁膜を形成する工程と、
前記第1溝内に第1配線を形成する工程と、
前記第1配線を覆うように、第1キャップ絶縁膜を形成する工程と、
前記第1キャップ絶縁膜を覆うように、シリコン酸炭化膜からなる第1絶縁膜を形成する工程と、
前記第1絶縁膜を形成する工程の後、前記第1絶縁膜に第1プラズマ処理を行うことにより、シリコン酸炭化膜からなる第1欠陥形成阻止膜を形成する工程と、
前記第1欠陥形成阻止膜を覆うように、第2溝を有し、且つシリコン酸炭化膜からなる第2層間絶縁膜を形成する工程と、
前記第2層間絶縁膜に第2プラズマ処理を行うことにより、前記第2溝の側壁面上及び底面上に、シリコン酸炭化膜からなる第2欠陥形成阻止膜を形成する工程と、
前記第2溝内に第2配線を形成する工程と、
を備え、
シリコンと酸素との結合に対応する赤外線吸収強度に対するシリコンと水素との結合に対応する赤外線吸収強度の比を存在比とすると、
前記第1欠陥形成阻止膜を形成する工程では、前記第1欠陥形成阻止膜における前記存在比が、前記第2層間絶縁膜における前記存在比よりも小さくなるように、前記第1欠陥形成阻止膜が形成され、
前記第2欠陥形成阻止膜を形成する工程では、前記第2欠陥形成阻止膜における前記存在比が、前記第2層間絶縁膜における前記存在比よりも小さくなるように、前記第2欠陥形成阻止膜が形成される、半導体装置の製造方法。 - 前記第1プラズマ処理および前記第2プラズマ処理のそれぞれは、酸素原子および炭素原子の少なくともいずれかを含むガスをプラズマ化して行われる、請求項7記載の半導体装置の製造方法。
- 前記ガスとして、酸素ガスおよび二酸化炭素ガスの少なくともいずれかが使用される、請求項8記載の半導体装置の製造方法。
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WO2004090974A1 (ja) | 2003-04-08 | 2004-10-21 | Matsushita Electric Industrial Co., Ltd. | 電子デバイス及びその製造方法 |
WO2007132879A1 (ja) | 2006-05-17 | 2007-11-22 | Nec Corporation | 半導体装置、半導体装置の製造方法及び半導体製造装置 |
WO2010125682A1 (ja) | 2009-04-30 | 2010-11-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2012023245A (ja) | 2010-07-15 | 2012-02-02 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
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WO2006001356A1 (ja) | 2004-06-24 | 2006-01-05 | Nec Corporation | 半導体装置及びその製造方法 |
JP2011199059A (ja) | 2010-03-19 | 2011-10-06 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
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WO2004090974A1 (ja) | 2003-04-08 | 2004-10-21 | Matsushita Electric Industrial Co., Ltd. | 電子デバイス及びその製造方法 |
WO2007132879A1 (ja) | 2006-05-17 | 2007-11-22 | Nec Corporation | 半導体装置、半導体装置の製造方法及び半導体製造装置 |
WO2010125682A1 (ja) | 2009-04-30 | 2010-11-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2012023245A (ja) | 2010-07-15 | 2012-02-02 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
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