JP2009158937A - Soi基板の製造方法 - Google Patents
Soi基板の製造方法 Download PDFInfo
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- JP2009158937A JP2009158937A JP2008300996A JP2008300996A JP2009158937A JP 2009158937 A JP2009158937 A JP 2009158937A JP 2008300996 A JP2008300996 A JP 2008300996A JP 2008300996 A JP2008300996 A JP 2008300996A JP 2009158937 A JP2009158937 A JP 2009158937A
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- 239000004215 Carbon black (E152) Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/928—Front and rear surface processing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
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Abstract
【解決手段】ソースガスを励起してプラズマを生成し、プラズマに含まれるイオン種を単結晶半導体基板の一方の面から添加して、単結晶半導体基板に損傷領域を形成し、単結晶半導体基板の一方の面上に絶縁層を形成し、絶縁層を間に挟んで単結晶半導体基板と向かい合うように支持基板を密着させ、単結晶半導体基板を加熱することにより、損傷領域において、支持基板に接着された単結晶半導体層と単結晶半導体基板とに分離し、支持基板に接着された単結晶半導体層を押圧する。
【選択図】図7
Description
本実施の形態では、単結晶半導体基板を分離して、支持基板に接着された単結晶半導体層と単結晶半導体基板とに分離し、支持基板に接着された単結晶半導体層の表面に対して押圧を行うSOI基板の製造方法について、図面を参照して説明する。また、本実施の形態では、ガラス基板等耐熱温度が低い基板に単結晶半導体層を設けることを目的の一とするSOI基板の製造方法についても合わせて説明する。
・加速電圧 10kV以上100kV以下(好ましくは、20kV以上80kV以下)
・ドーズ量 1×1016atoms/cm2以上4×1016atoms/cm2以下
・ビーム電流密度 2μA/cm2(好ましくは、5μA/cm2以上、より好ましくは10μA/cm2以上)
上記のような水素プラズマ中には、H+、H2 +、H3 +といった水素イオン種が存在する。ここで、各水素イオン種の反応過程(生成過程、消滅過程)について、以下に反応式を列挙する。
e+H→e+H++e ・・・・・ (1)
e+H2→e+H2 ++e ・・・・・ (2)
e+H2→e+(H2)*→e+H+H ・・・・・ (3)
e+H2 +→e+(H2 +)*→e+H++H ・・・・・ (4)
H2 ++H2→H3 ++H ・・・・・ (5)
H2 ++H2→H++H+H2 ・・・・・ (6)
e+H3 +→e+H++H+H ・・・・・ (7)
e+H3 +→H2+H ・・・・・ (8)
e+H3 +→H+H+H ・・・・・ (9)
H2+H+→H3 + ・・・・・ (10)
H2 ++H→H3 + ・・・・・ (11)
上記のように、H3 +は、主として反応式(5)により表される反応過程により生成される。一方で、反応式(5)と競合する反応として、反応式(6)により表される反応過程が存在する。H3 +が増加するためには、少なくとも、反応式(5)の反応が、反応式(6)の反応より多く起こる必要がある(なお、H3 +が減少する反応としては他にも(7)、(8)、(9)が存在するため、(5)の反応が(6)の反応より多いからといって、必ずしもH3 +が増加するとは限らない。)。反対に、反応式(5)の反応が、反応式(6)の反応より少ない場合には、プラズマ中におけるH3 +の割合は減少する。
ここで、イオン種の割合(特にH3 +の割合)が異なる例を示す。図2は、100%水素ガス(イオン源の圧力:4.7×10−2Pa)から生成されるイオンの質量分析結果を示すグラフである。なお、上記質量分析は、イオン源から引き出されたイオンを測定することにより行った。横軸はイオンの質量である。スペクトル中、質量1、2、3のピークは、それぞれ、H+、H2 +、H3 +に対応する。縦軸は、スペクトルの強度であり、イオンの数に対応する。図2では、質量が異なるイオンの数量を、質量3のイオンを100とした場合の相対比で表している。図2から、上記イオン源により生成されるイオンの割合は、H+:H2 +:H3 +=1:1:8程度となることが分かる。なお、このような割合のイオンは、プラズマを生成するプラズマソース部(イオン源)と、当該プラズマからイオンビームを引き出すための引出電極などから構成されるイオンドーピング装置によっても得ることが出来る。
図2のような複数のイオン種を含むプラズマを生成し、生成されたイオン種を質量分離しないで単結晶半導体基板に照射する場合、単結晶半導体基板の表面には、H+、H2 +、H3 +の各イオンが照射される。イオンの照射からイオン導入領域形成にかけてのメカニズムを再現するために、以下の5種類のモデルを考える。
1.照射されるイオン種がH+で、照射後もH+(H)である場合。
2.照射されるイオン種がH2 +で、照射後もH2 +(H2)のままである場合。
3.照射されるイオン種がH2 +で、照射後に2個のH(H+)に分裂する場合。
4.照射されるイオン種がH3 +で、照射後もH3 +(H3)のままである場合。
5.照射されるイオン種がH3 +で、照射後に3個のH(H+)に分裂する場合。
上記のモデルを基にして、水素イオン種をSi基板に照射する場合のシミュレーションを行った。シミュレーション用のソフトウェアとしては、SRIM(the Stopping and Range of Ions in Matter:モンテカルロ法によるイオン導入過程のシミュレーションソフトウェア、TRIM(the Transport of Ions in Matter)の改良版)を用いている。なお、計算の関係上、モデル2ではH2 +を質量2倍のH+に置き換えて計算した。また、モデル4ではH3 +を質量3倍のH+に置き換えて計算した。さらに、モデル3ではH2 +を運動エネルギー1/2のH+に置き換え、モデル5ではH3 +を運動エネルギー1/3のH+に置き換えて計算を行った。
[フィッティング関数]
=X/V×[モデル1のデータ]+Y/V×[モデル5のデータ]
・モデル3に示される照射過程により導入される水素は、モデル5の照射過程と比較して僅かであるため、除外して考えても大きな影響はない(SIMSデータにおいても、ピークが現れていない)。
・モデル5とピーク位置の近いモデル3は、モデル5において生じるチャネリング(結晶の格子構造に起因する原子の移動)により隠れてしまう可能性が高い。すなわち、モデル3のフィッティングパラメータを見積もるのは困難である。これは、本シミュレーションが非晶質Siを前提としており、結晶性に起因する影響を考慮していないことによるものである。
図2に示すようなH3 +の割合を高めた水素イオン種を基板に照射することで、H3 +に起因する複数のメリットを享受することができる。例えば、H3 +はH+やHなどに分離して基板内に導入されるため、主にH+やH2 +を照射する場合と比較して、イオンの導入効率を向上させることができる。これにより、SOI基板の生産性向上を図ることができる。また、H3 +が分離した後のH+やHの運動エネルギーは小さくなる傾向にあるから、薄い半導体層の製造に向いている。
本実施の形態では、実施の形態1とは異なるSOI基板の作製方法について図12を用いて説明する。以下、実施の形態1と同様の構成については同一の符号を付し、説明を省略する。
本実施の形態では、上記の実施の形態とは異なるSOI基板の作製方法について図13及び図14を用いて説明する。以下、実施の形態1と同様の構成については同一の符号を付し、説明を省略する。
本実施の形態では、高性能及び高信頼性な半導体素子を有する半導体装置を、歩留まりよく作製することを目的とした半導体装置の作製方法の一例としてCMOS(相補型金属酸化物半導体:Complementary Metal Oxide Semiconductor)に関して図15及び図16を用いて説明する。なお、実施の形態1と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
本実施の形態では、本発明の半導体装置の製造方法の一例について、図17乃至19を参照して説明する。なお、本実施の形態においては、半導体装置の一例として液晶表示装置を挙げて説明するが、本発明の半導体装置は液晶表示装置に限られるものではない。
本実施の形態では、本発明に係る発光素子を有する半導体装置(エレクトロルミネッセンス表示装置)について説明する。なお、周辺回路領域や画素領域等に用いられるトランジスタの作製方法は、実施の形態5を参照することができるため、詳細については省略する。
本実施の形態では、本発明に係る半導体装置の別の例について、図22及び図23を参照して説明する。なお、本実施の形態においては、マイクロプロセッサ及び電子タグを例に挙げて説明するが、本発明の半導体装置はこれらに限られるものではない。
本実施の形態では、本発明の半導体装置、特に表示装置を用いた電子機器について、図24及び図25を参照して説明する。
本実施の形態では、本発明の半導体装置、特に無線タグの用途について、図26を参照して説明する。
102 絶縁層
102a 酸化窒化シリコン層
102b 窒化酸化シリコン層
103 損傷領域
104 絶縁層
105 イオンビーム
106 レーザビーム
107 支持基板
108 単結晶半導体層
109 単結晶半導体層
110 単結晶半導体層
111 単結晶半導体層
113 矢印
114 部分
116 端部
117 接着界面
118 マスク
119 凸部
120 半導体基板
121 SOI基板
122 SOI基板
123 単結晶半導体層
124 微小な異物
125a 単結晶半導体層
125b 単結晶半導体層
125c 単結晶半導体層
205 単結晶半導体層
206 単結晶半導体層
207 ゲート絶縁層
211 マスク
214 マスク
216a 側壁絶縁層
216b 側壁絶縁層
216c 側壁絶縁層
216d 側壁絶縁層
218 マスク
223 マスク
228 絶縁層
231 薄膜トランジスタ
232 薄膜トランジスタ
233a ゲート絶縁層
233b ゲート絶縁層
301 基板ステージ
302 ヒーター
303 移載器
308 加圧器
309 ヒーター
310 押ピン
700 チャンバー
701 ダイヤフラム
702a 給気バルブ
702b 排気バルブ
702c 排気バルブ
702d 給気バルブ
703 ヒーター
704 加圧室
705 試料室
706 クッション
1102 絶縁層
1104 絶縁層
1108 ゲート絶縁層
1111 単結晶半導体層
1112 単結晶半導体層
1113 単結晶半導体層
1114 単結晶半導体層
1116a マスク
1116b マスク
1116c マスク
1116d マスク
1116e マスク
1132a マスク
1132b マスク
1132c マスク
1146a マスク
1146b マスク
1164 薄膜トランジスタ
1166 薄膜トランジスタ
1168 薄膜トランジスタ
1550 薄膜トランジスタ
1552 薄膜トランジスタ
1554 薄膜トランジスタ
1556 薄膜トランジスタ
1402 絶縁層
1406 絶縁層
1568 絶縁層
Claims (6)
- ソースガスを励起してプラズマを生成し、前記プラズマに含まれるイオン種を単結晶半導体基板の一方の面から添加して、前記単結晶半導体基板に損傷領域を形成し、
前記単結晶半導体基板の一方の面上に絶縁層を形成し、
前記絶縁層を間に挟んで前記単結晶半導体基板と向かい合うように支持基板を密着させ、
前記単結晶半導体基板を加熱することにより、前記損傷領域において、単結晶半導体層が接着された前記支持基板と単結晶半導体基板とに分離し、
前記支持基板に接着された前記単結晶半導体層を押圧することを特徴とするSOI基板の作製方法。 - ソースガスを励起してプラズマを生成し、前記プラズマに含まれるイオン種を単結晶半導体基板の一方の面から添加して、前記単結晶半導体基板に損傷領域を形成し、
前記単結晶半導体基板の一方の面上に絶縁層を形成し、
前記絶縁層を間に挟んで前記単結晶半導体基板と向かい合うように支持基板を密着させ、
前記単結晶半導体基板を加熱することにより、前記損傷領域において、単結晶半導体層が接着された前記支持基板と単結晶半導体基板とを分離し、
前記単結晶半導体層に対して選択的にエッチングを行うことにより、島状の単結晶半導体層を複数形成し、
前記複数の島状の単結晶半導体層を押圧することを特徴とするSOI基板の作製方法。 - ソースガスを励起してプラズマを生成し、前記プラズマに含まれるイオン種を単結晶半導体基板の一方の面から添加して、前記単結晶半導体基板に損傷領域を形成し、
前記単結晶半導体基板の一方の面に絶縁層を形成し、
前記絶縁層が形成された前記単結晶半導体基板に対して選択的にエッチングを行い、前記絶縁層及び前記単結晶半導体基板に前記損傷領域よりも深い開口部を設け、
前記絶縁層を間に挟んで前記単結晶半導体基板と向き合うように支持基板を密着させ、
前記単結晶半導体基板を加熱することにより、前記損傷領域において、複数の単結晶半導体層が接着された前記支持基板と単結晶半導体基板とを分離し、
前記支持基板に接着された前記複数の単結晶半導体層を押圧することを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項3のいずれか一において、
前記絶縁層は、シリコンソースガスに有機シランガスを用いて化学気相成長法により形成された酸化シリコン膜であることを特徴とするSOI基板の作製方法。 - 請求項4において、
前記有機シランガスは、珪酸エチル、テトラメチルシクロテトラシロキサン、オクタメチルシクロテトラシロキサン、ヘキサメチルジシラザン、トリエトキシシラン、トリスジメチルアミノシランから選ばれたガスであることを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項5のいずれか一において、
前記絶縁層の膜厚は、500nm乃至1000nmであることを特徴とするSOI基板の製造方法。
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