JP5619474B2 - Soi基板の作製方法 - Google Patents
Soi基板の作製方法 Download PDFInfo
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- JP5619474B2 JP5619474B2 JP2010119101A JP2010119101A JP5619474B2 JP 5619474 B2 JP5619474 B2 JP 5619474B2 JP 2010119101 A JP2010119101 A JP 2010119101A JP 2010119101 A JP2010119101 A JP 2010119101A JP 5619474 B2 JP5619474 B2 JP 5619474B2
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- crystal semiconductor
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Images
Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Manufacturing & Machinery (AREA)
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- Thin Film Transistor (AREA)
- Electroluminescent Light Sources (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本実施の形態では、複数の単結晶半導体層が基板上に設けられたSOI基板およびその作製方法について説明する。
O2+hν(λ1nm)→O(3P)+O(3P) (1)
O(3P)+O2→O3 (2)
O3+hν(λ2nm)→O(1D)+O2 (3)
O2+hν(λ3nm)→O(1D)+O(3P) (4)
O(3P)+O2→O3 (5)
O3+hν(λ3nm)→O(1D)+O2 (6)
本実施の形態では、単結晶半導体基板の分離の熱処理時に、実施の形態1とは異なるトレイを用いる場合の、複数の単結晶半導体層が基板上に設けられたSOI基板の作製方法について説明する。
本実施の形態では、単結晶半導体基板の再生処理について説明する。図8(C)及び図12(B)に示す単結晶半導体層115が分離された単結晶半導体基板117を再生処理する。図14を用いて、単結晶半導体基板の再生処理を説明する。
本実施の形態では、実施の形態1または実施の形態2で示したSOI基板を用いた半導体装置の作製方法の一例として、半導体素子の一つである薄膜トランジスタを作製する方法を説明する。複数の薄膜トランジスタを組み合わせることで、各種の半導体装置が形成される。本実施の形態では、実施の形態1及び実施の形態2に示す作製方法で作製したSOI基板100を用いることにする。
本実施の形態では、実施の形態1または実施の形態2で示したSOI基板を用いた半導体装置が有する各種回路の具体的な構成について、インバータを例に挙げて説明する。インバータの回路図を図18(A)に、また図18(A)に示すインバータの上面図を図18(B)に、一例として示す。
本実施の形態では、実施の形態1または実施の形態2で示したSOI基板を用いた半導体装置が有する各種回路の具体的な構成について、NAND回路を例に挙げて説明する。NAND回路の回路図を図19(A)に、また図19(A)に示すNAND回路の上面図を図19(B)に、一例として示す。
本実施の形態では、実施の形態1または実施の形態2で示したSOI基板を用いた半導体装置の一つであるRFタグの構成について説明する。図20(A)は該RFタグの一形態を示すブロック図である。図20(A)においてRFタグ500は、アンテナ501と、集積回路502とを有している。集積回路502は、電源回路503、復調回路504、変調回路505、レギュレータ506、制御回路507、メモリ509を有している。
本実施の形態では、実施の形態1または実施の形態2で示したSOI基板を用いた半導体装置の一つである、アクティブマトリクス型の半導体表示装置の構成について説明する。
実施の形態1または実施の形態2で示したSOI基板を用いた半導体装置を用いることができる電子機器として、携帯電話、携帯型ゲーム機または電子書籍、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、オーディオコンポ等)、ノート型パーソナルコンピュータ、記録媒体を備えた画像再生装置(代表的にはDVD:Digital Versatile Disc等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置)などが挙げられる。これら電子機器の具体例を図22に示す。
11 凹部
20 第2のトレイ
21 凹部
30 第3のトレイ
31 凹部
32 支持部
100 SOI基板
101 ベース基板
102 絶縁層
111 単結晶半導体基板
115 単結晶半導体層
116 単結晶半導体層
117 単結晶半導体基板
118 単結晶半導体基板
112 絶縁層
113 脆化層
114 接合層
121 イオンビーム
122 レーザビーム
130 凸部
132 残存した絶縁層
133 残存した脆化層
134 残存した接合層
135 残存した単結晶半導体層
Claims (2)
- 基板を有し、
前記基板の上方に第1の絶縁層を有し、
前記基板の上方に第2の絶縁層を有し、
前記第1の絶縁層の上方に第1の半導体基板を有し、
前記第2の絶縁層の上方に第2の半導体基板を有し、
前記第1の半導体基板に第1の脆化層を有し、
前記第2の半導体基板に第2の脆化層を有する構造体が用意される第1の工程と、
トレイの上方に前記構造体が配置され、熱が加わり、前記第1の半導体基板と第1の半導体層とが分離され、前記第2の半導体基板と第2の半導体層とが分離される第2の工程と、を有し、
前記トレイは、第1の凹部を有し、
前記トレイは、第2の凹部を有し、
前記第1の半導体基板は、前記トレイの前記第1の凹部内に位置するように配置され、
前記第2の半導体基板は、前記トレイの前記第2の凹部内に位置するように配置され、
前記第1の凹部の底面の面積は、前記第1の半導体基板の底面の面積の1.1倍以下であり、
前記第2の凹部の底面の面積は、前記第2の半導体基板の底面の面積の1.1倍以下であり、
前記第1の半導体基板が前記トレイと接触しない状態で前記熱が加わり、
前記第2の半導体基板が前記トレイと接触しない状態で前記熱が加わることを特徴とするSOI基板の作製方法。 - 請求項1において、
前記トレイは、支持部を有し、
前記支持部の幅は、前記第1の凹部と前記第2の凹部との間の幅よりも狭く、
前記支持部が前記基板と接触することを特徴とするSOI基板の作製方法。
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WO2021033989A1 (ko) * | 2019-08-22 | 2021-02-25 | (주)더숨 | 디스플레이 제조용 기판 및 이의 제조 방법 |
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