JP2008527727A5 - - Google Patents

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Publication number
JP2008527727A5
JP2008527727A5 JP2007550572A JP2007550572A JP2008527727A5 JP 2008527727 A5 JP2008527727 A5 JP 2008527727A5 JP 2007550572 A JP2007550572 A JP 2007550572A JP 2007550572 A JP2007550572 A JP 2007550572A JP 2008527727 A5 JP2008527727 A5 JP 2008527727A5
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JP
Japan
Prior art keywords
dielectric layer
layer
dielectric
product
bond pad
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JP2007550572A
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English (en)
Japanese (ja)
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JP2008527727A (ja
JP5321873B2 (ja
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Priority claimed from US11/032,975 external-priority patent/US7282433B2/en
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Publication of JP2008527727A publication Critical patent/JP2008527727A/ja
Publication of JP2008527727A5 publication Critical patent/JP2008527727A5/ja
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Publication of JP5321873B2 publication Critical patent/JP5321873B2/ja
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JP2007550572A 2005-01-10 2006-01-10 接合パッドを具えた相互接続構造、および、接合パッド上にバンプ部位を作成する方法 Active JP5321873B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/032,975 US7282433B2 (en) 2005-01-10 2005-01-10 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
US11/032,975 2005-01-10
PCT/US2006/000881 WO2006074470A1 (en) 2005-01-10 2006-01-10 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads

Publications (3)

Publication Number Publication Date
JP2008527727A JP2008527727A (ja) 2008-07-24
JP2008527727A5 true JP2008527727A5 (enExample) 2008-09-11
JP5321873B2 JP5321873B2 (ja) 2013-10-23

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ID=36282804

Family Applications (1)

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JP2007550572A Active JP5321873B2 (ja) 2005-01-10 2006-01-10 接合パッドを具えた相互接続構造、および、接合パッド上にバンプ部位を作成する方法

Country Status (6)

Country Link
US (3) US7282433B2 (enExample)
EP (2) EP3220416B1 (enExample)
JP (1) JP5321873B2 (enExample)
KR (1) KR100918129B1 (enExample)
TW (1) TWI387018B (enExample)
WO (1) WO2006074470A1 (enExample)

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US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
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