JP2008270758A - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP2008270758A JP2008270758A JP2008060846A JP2008060846A JP2008270758A JP 2008270758 A JP2008270758 A JP 2008270758A JP 2008060846 A JP2008060846 A JP 2008060846A JP 2008060846 A JP2008060846 A JP 2008060846A JP 2008270758 A JP2008270758 A JP 2008270758A
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- layer
- semiconductor
- film
- semiconductor device
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Images
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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Abstract
【解決手段】絶縁基板上に形成された半導体層と、半導体層上に形成された第1の絶縁層と、第1の絶縁層上に形成されたゲート電極と、ゲート電極上に形成された第2の絶縁層と、を有し、少なくとも第1の絶縁層、及び第2の絶縁層に形成された半導体層に達する開口部と、前記開口部において前記第2の絶縁層の側面に形成された段差と、を有する。
【選択図】図1
Description
本実施の形態では、ソース電極又はドレイン電極の膜厚のばらつき又は断線を防止する半導体装置の構成及び作製方法について説明する。
本実施の形態では、図1又は図5に示す半導体装置の具体的な作製工程について説明する。なお、本実施の形態において、図1(A)のAとBとを結ぶ破線での断面における作製工程を図6(A)〜(D)、図7(A)〜(C)を用いて、図1(A)のCとDとを結ぶ破線での断面における作製工程を図6(E)〜(H)、図7(D)〜(F)を用いて説明する。
本発明に係る半導体装置は、実施の形態1〜2に示した構成に限らず様々な形状をとることができる。本実施の形態では、半導体層を部分的にシリサイド化させた薄膜トランジスタの構成及び作製方法について説明する。図8に本実施の形態の半導体装置の構成を示す。図8(A)は上面図であり、図8(B)は図8(A)の破線ABでの断面図を示し、図8(C)は図8(A)の破線CDでの断面図を示す。
実施の形態1〜3で説明した半導体装置は、単結晶シリコン基板中に酸化シリコンでなる酸化膜を形成し、酸化膜上の単結晶半導体薄膜を活性層として用いることができる。本実施の形態では、SIMOXと呼ばれるSOI技術を用いた半導体装置について説明する。
本実施の形態では、単結晶シリコン基板上に酸化シリコンでなる酸化膜を形成し、酸化膜上に形成された単結晶半導体薄膜を活性層として用いる半導体装置について説明する。本実施の形態では、Smart−Cut法を用いて形成されるSOI基板を用いた半導体装置について説明する。
本実施の形態では、実施の形態1で説明した半導体装置を用い、エレクトロルミネッセンス素子(以下、「EL素子」ともいう。)を有する表示装置(EL表示装置)を作製する方法について説明する。なお、本実施の形態において用いることが可能な半導体装置は実施の形態1に示すものに限られず、実施の形態2〜5で説明した半導体装置を用いてもよい。
本実施の形態では、実施の形態1で作製した半導体装置を用いて、透過型液晶表示装置を作製する方法について説明する。もちろん、実施の形態2〜5で作製した半導体装置を用いることもできる。
本実施の形態では、実施の形態1〜5のいずれかで説明した薄膜トランジスタ、記憶素子およびアンテナを含む無線通信可能な半導体装置の作製方法について、図面を参照して説明する。
31 絶縁層
32 半導体層
33 ゲート絶縁層
34 導電層
36 絶縁層
203 絶縁層
204 導電層
205 薄膜トランジスタ
32a チャネル形成領域
32b 不純物領域
32c 不純物領域
Claims (7)
- 基板上に形成された半導体層と、
前記半導体層上に形成された第1の絶縁層と、
前記第1の絶縁層上に形成されたゲート電極と、
前記ゲート電極上に形成された第2の絶縁層と、
少なくとも前記第1の絶縁層、及び前記第2の絶縁層に形成された前記半導体層に達する開口部と、
前記開口部において前記第2の絶縁層の側面に形成された段差と、
前記第2の絶縁層上に形成され、かつ前記開口部の側面を被覆し、半導体層に接する導電層と、を有する半導体装置。 - 基板上に形成された第1の絶縁層と、
前記第1の絶縁層上に形成された第2の絶縁層と、
前記第2の絶縁層上に形成された半導体層と、
前記半導体層上に形成された第3の絶縁層と、
前記第3の絶縁層上に形成されたゲート電極と、
前記ゲート電極上に形成された第4の絶縁層と、
少なくとも前記第2の絶縁層、前記半導体層及び前記第4の絶縁層に形成された前記第1の絶縁層に達する開口部と、
前記第4の絶縁層上に形成され、かつ前記開口部の側面を被覆し、第1の絶縁層と接する導電層と、を有し、
前記半導体層に形成された開口部の口径は、前記第4の絶縁層に形成された開口部の口径に比べて小さい半導体装置。 - 請求項1又は請求項2において、
前記半導体層の側面に形成された絶縁性の側壁を有する半導体装置。 - 基板上に半導体層を形成し、
前記半導体層上に第1の絶縁層を形成し、
前記第1の絶縁層上にゲート電極を形成し、
前記ゲート電極上に第2の絶縁層を形成し、
前記第2の絶縁層上に側面に段差が形成されたレジストを形成し、
前記レジストをマスクとしてエッチングすることにより、少なくとも前記第2の絶縁層に前記半導体層に達する開口部を形成し、前記第2の絶縁層の側面に段差を形成し、
前記開口部の側面、及び前記第2の絶縁層上に、前記半導体層に接する導電層を形成する半導体装置の作製方法。 - 基板上に第1の絶縁層を形成し、
前記第1の絶縁層上に第2の絶縁層を形成し、
前記第2の絶縁層上に半導体層を形成し、
前記半導体層上に第3の絶縁層を形成し、
前記第3の絶縁層上にゲート電極を形成し、
前記ゲート電極上に第4の絶縁層を形成し、
前記第4の絶縁層上に側面に段差が形成されたレジストを形成し、
前記レジストをマスクとしてエッチングすることにより、少なくとも前記第2の絶縁層、前記半導体層及び前記第4の絶縁層に、前記第1の絶縁層に達する開口部を形成し、
前記開口部を形成する工程において、前記半導体層に形成された前記開口部の口径は、前記第4の絶縁層に形成された前記開口部の口径に比べて小さな径で形成し、
前記開口部の側面、及び前記第4の絶縁層上に、前記第1の絶縁層に接する導電層を形成する半導体装置の作製方法。 - 請求項4又は請求項5において、
前記開口部はドライエッチングにより形成する半導体装置の作製方法。 - 請求項4乃至請求項6のいずれか一項において、
前記半導体層の側面に絶縁性の側壁を形成する半導体装置の作製方法。
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JP2019004180A (ja) * | 2011-01-12 | 2019-01-10 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP2019016803A (ja) * | 2011-09-23 | 2019-01-31 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2020129665A (ja) * | 2011-09-23 | 2020-08-27 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2018186296A (ja) * | 2011-11-11 | 2018-11-22 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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KR102188065B1 (ko) * | 2014-05-23 | 2020-12-07 | 엘지디스플레이 주식회사 | 박막 트랜지스터 어레이 기판 및 이의 제조 방법 |
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US7709368B2 (en) | 2010-05-04 |
US7969012B2 (en) | 2011-06-28 |
KR101471823B1 (ko) | 2014-12-11 |
KR101425850B1 (ko) | 2014-08-01 |
KR20080087684A (ko) | 2008-10-01 |
US20080237876A1 (en) | 2008-10-02 |
US8581413B2 (en) | 2013-11-12 |
KR101522860B1 (ko) | 2015-05-26 |
JP5779266B2 (ja) | 2015-09-16 |
US20110248345A1 (en) | 2011-10-13 |
KR20140051882A (ko) | 2014-05-02 |
KR20140093921A (ko) | 2014-07-29 |
JP2014160837A (ja) | 2014-09-04 |
US20100176461A1 (en) | 2010-07-15 |
JP5512930B2 (ja) | 2014-06-04 |
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