JP2008219046A - 薄膜トランジスターの製造方法 - Google Patents
薄膜トランジスターの製造方法 Download PDFInfo
- Publication number
- JP2008219046A JP2008219046A JP2008144142A JP2008144142A JP2008219046A JP 2008219046 A JP2008219046 A JP 2008219046A JP 2008144142 A JP2008144142 A JP 2008144142A JP 2008144142 A JP2008144142 A JP 2008144142A JP 2008219046 A JP2008219046 A JP 2008219046A
- Authority
- JP
- Japan
- Prior art keywords
- film transistor
- thin film
- layer
- oxide
- transistor according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title abstract description 10
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 19
- 239000011521 glass Substances 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims 1
- 239000007943 implant Substances 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 12
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 14
- 230000008021 deposition Effects 0.000 description 8
- 239000002245 particle Substances 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000001953 recrystallisation Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000000354 decomposition reaction Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/909—Controlled atmosphere
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
【解決手段】 薄膜トランジスターは、アモルファスシリコンを堆積させ、ゲート構造を形成し、次いで、高圧酸化を用いて、層化構造を有する高性能ゲート酸化物を形成することにより作成される。
【選択図】 図1
Description
絶縁基板(1)、
前記基板(1)上に堆積され、ソース及びドレイン領域有する再結晶化シリコン層(3)、ここで、前記再結晶化シリコン層(3)は、層化構造を有するシリコン層から形成されたものであり、
前記再結晶化シリコン層(3)に接触し、ソース及びドレイン領域(5)の間に位置するゲート構造(9)を含み、前記ゲート構造が、
前記再結晶化シリコン層(3)上に形成された100Å以下の厚さを有する第1の酸化物層(113)、
前記第1の酸化物層(113)に接触する、TEOSの低圧分解により形成されたSiO2よりなる100Å乃至150Åの厚さを有する圧縮された第2の酸化物層(115)、
前記第2の酸化物層(115)に接触する伝導領域(13)、及び
前記第1の酸化物層(113)と前記再結晶化されたシリコン層(3)の間に5乃至10気圧、800乃至825℃の温度の条件下で成長された第3の酸化物層(111)を含むことを特徴とする薄膜トランジスタを提供することにある。
3 シリコン領域
5 ソース/ドレーン領域
7 チャンネル領域
11 酸化物領域
13 伝導領域
Claims (10)
- 薄膜トランジスターであって、前記トランジスターが、
絶縁基板(1)、
前記絶縁基板(1)上に形成されたゲート構造(9)、及び
前記基板上に位置し、ソース/ドレイン領域(5)及びチャネル領域(7)を有する再結晶化シリコン層(3)を含み、
前記ゲート構造は、
100Å以下の厚さを有する第1の酸化物層(113)、
前記第1の酸化物層(113)の側面に接触する100Å乃至150Åの厚さを有する第2の酸化物層(115)、
前記第1の酸化物層(113)の前記側面に対向する側面に接触する第3の成長酸化物層(111)と、及び
前記第2の酸化物層(115)に接触する伝導領域(13)を含み、
前記ゲート構造(9)の少なくとも一部は、前記ソース/ドレイン領域(5)間に位置し、
前記第1、第2及び第3の酸化物層は、前記伝導領域(13)と前記再結晶化シリコン層(3)の間に位置する
ことを特徴とする薄膜トランジスター。 - 前記再結晶化シリコン層(3)が、粒子構造においてわずかな変動性を有することを特徴とする請求項1記載の薄膜トランジスター。
- 前記伝導領域(13)が、チャネルインプラントを含むことを特徴とする請求項1記載の薄膜トランジスター。
- 前記基板(1)が、集積回路構築において形成される誘電層を含むことを特徴とする請求項1記載の薄膜トランジスター。
- 前記基板が、ガラスで構成されることを特徴とする請求項1記載の薄膜トランジスター。
- 前記再結晶化シリコン層(3)が、層化構造を有することを特徴とする請求項1記載の薄膜トランジスター。
- 前記ゲート構造が、前記絶縁基板(1)上に位置することを特徴とする請求項1記載の薄膜トランジスター。
- 前記再結晶化シリコン層(3)が、前記ゲート構造上に位置することを特徴とする請求項1記載の薄膜トランジスター。
- 前記第1、第2及び第3の酸化物層が、前記絶縁基板(1)に沿って位置することを特徴とする請求項1記載の薄膜トランジスター。
- 前記第1、第2及び第3の酸化物層が、第1の領域において前記再結晶化シリコン層(3)から前記絶縁基板(1)を分離し、前記第1、第2及び第3の酸化物層が、第2の領域において前記再結晶化シリコン層(3)から前記絶縁基板(1)を分離することを特徴とする請求項1記載の薄膜トランジスター。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/932,445 US5322807A (en) | 1992-08-19 | 1992-08-19 | Method of making thin film transistors including recrystallization and high pressure oxidation |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005263148A Division JP2006024958A (ja) | 1992-08-19 | 2005-09-12 | 薄膜トランジスターの製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008219046A true JP2008219046A (ja) | 2008-09-18 |
Family
ID=25462335
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20437593A Expired - Lifetime JP3739809B2 (ja) | 1992-08-19 | 1993-08-19 | 薄膜トランジスターの製造方法 |
JP2005263148A Pending JP2006024958A (ja) | 1992-08-19 | 2005-09-12 | 薄膜トランジスターの製造方法 |
JP2008144142A Pending JP2008219046A (ja) | 1992-08-19 | 2008-06-02 | 薄膜トランジスターの製造方法 |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20437593A Expired - Lifetime JP3739809B2 (ja) | 1992-08-19 | 1993-08-19 | 薄膜トランジスターの製造方法 |
JP2005263148A Pending JP2006024958A (ja) | 1992-08-19 | 2005-09-12 | 薄膜トランジスターの製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5322807A (ja) |
EP (1) | EP0588487A3 (ja) |
JP (3) | JP3739809B2 (ja) |
TW (1) | TW242689B (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002372725A (ja) * | 2001-04-04 | 2002-12-26 | Seiko Epson Corp | 非線形素子の製造方法、電気光学装置の製造方法、電気光学装置、および電子機器 |
US5322807A (en) * | 1992-08-19 | 1994-06-21 | At&T Bell Laboratories | Method of making thin film transistors including recrystallization and high pressure oxidation |
TW232751B (en) * | 1992-10-09 | 1994-10-21 | Semiconductor Energy Res Co Ltd | Semiconductor device and method for forming the same |
US6730549B1 (en) | 1993-06-25 | 2004-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for its preparation |
US5663077A (en) * | 1993-07-27 | 1997-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films |
JPH0766424A (ja) | 1993-08-20 | 1995-03-10 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
CN1052566C (zh) * | 1993-11-05 | 2000-05-17 | 株式会社半导体能源研究所 | 制造半导体器件的方法 |
US6897100B2 (en) | 1993-11-05 | 2005-05-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for processing semiconductor device apparatus for processing a semiconductor and apparatus for processing semiconductor device |
KR950024302A (ko) * | 1994-01-06 | 1995-08-21 | 빈센트 비. 인그라시아 | 반도체 구조체 및 반도체 구조체 제조 방법 |
US6706572B1 (en) * | 1994-08-31 | 2004-03-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a thin film transistor using a high pressure oxidation step |
FR2728390A1 (fr) * | 1994-12-19 | 1996-06-21 | Korea Electronics Telecomm | Procede de formation d'un transistor a film mince |
US5637514A (en) * | 1995-10-18 | 1997-06-10 | Micron Technology, Inc. | Method of forming a field effect transistor |
US5739066A (en) | 1996-09-17 | 1998-04-14 | Micron Technology, Inc. | Semiconductor processing methods of forming a conductive gate and line |
US5846888A (en) * | 1996-09-27 | 1998-12-08 | Micron Technology, Inc. | Method for in-situ incorporation of desirable impurities into high pressure oxides |
US20020137890A1 (en) * | 1997-03-31 | 2002-09-26 | Genentech, Inc. | Secreted and transmembrane polypeptides and nucleic acids encoding the same |
US6143611A (en) * | 1998-07-30 | 2000-11-07 | Micron Technology, Inc. | Semiconductor processing methods, methods of forming electronic components, and transistors |
US6140187A (en) * | 1998-12-02 | 2000-10-31 | Lucent Technologies Inc. | Process for forming metal oxide semiconductors including an in situ furnace gate stack with varying silicon nitride deposition rate |
TW565944B (en) * | 2002-10-09 | 2003-12-11 | Toppoly Optoelectronics Corp | Method of forming a low temperature polysilicon thin film transistor |
KR100763913B1 (ko) * | 2006-04-27 | 2007-10-05 | 삼성전자주식회사 | 박막 트랜지스터의 제조방법 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6435959A (en) * | 1987-07-30 | 1989-02-07 | Ricoh Kk | Thin film transistor |
JPH0284772A (ja) * | 1988-09-21 | 1990-03-26 | Seiko Epson Corp | 半導体装置の製造方法 |
JPH0362526A (ja) * | 1989-07-29 | 1991-03-18 | Sony Corp | 薄膜トランジスタの製法 |
JPH03292718A (ja) * | 1990-04-10 | 1991-12-24 | Seiko Epson Corp | 結晶性半導体薄膜の製造方法 |
JPH0443642A (ja) * | 1990-06-11 | 1992-02-13 | G T C:Kk | ゲート絶縁膜の形成方法 |
EP0474289A1 (en) * | 1990-09-04 | 1992-03-11 | Koninklijke Philips Electronics N.V. | A method for the fabrication of low leakage polysilicon thin film transistors |
JPH04206775A (ja) * | 1990-11-30 | 1992-07-28 | Casio Comput Co Ltd | 薄膜トランジスタ |
JPH06163898A (ja) * | 1992-08-19 | 1994-06-10 | American Teleph & Telegr Co <Att> | 薄膜トランジスターの製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3974515A (en) * | 1974-09-12 | 1976-08-10 | Rca Corporation | IGFET on an insulating substrate |
JPS6014473A (ja) * | 1983-07-05 | 1985-01-25 | Asahi Glass Co Ltd | 薄膜トランジスタの電極構造 |
JPS61199665A (ja) * | 1985-03-01 | 1986-09-04 | Hitachi Ltd | 薄膜半導体装置 |
JPS61228671A (ja) * | 1985-04-02 | 1986-10-11 | Hitachi Ltd | 薄膜トランジスタ |
US4675978A (en) * | 1985-09-09 | 1987-06-30 | Rca Corporation | Method for fabricating a radiation hardened oxide having two portions |
US4888632A (en) * | 1988-01-04 | 1989-12-19 | International Business Machines Corporation | Easily manufacturable thin film transistor structures |
JPH0221663A (ja) * | 1988-07-08 | 1990-01-24 | Sharp Corp | 薄膜トランジスタの製造方法 |
JPH02103925A (ja) * | 1988-10-13 | 1990-04-17 | Seiko Epson Corp | 半導体装置の製造方法 |
JPH03190141A (ja) * | 1989-12-12 | 1991-08-20 | Samsung Electron Devices Co Ltd | 平板ディスプレー用薄膜トランジスタ及びその製造方法 |
US5010027A (en) * | 1990-03-21 | 1991-04-23 | General Electric Company | Method for fabricating a self-aligned thin-film transistor utilizing planarization and back-side photoresist exposure |
US5198379A (en) * | 1990-04-27 | 1993-03-30 | Sharp Kabushiki Kaisha | Method of making a MOS thin film transistor with self-aligned asymmetrical structure |
-
1992
- 1992-08-19 US US07/932,445 patent/US5322807A/en not_active Expired - Lifetime
-
1993
- 1993-07-30 TW TW082106105A patent/TW242689B/zh not_active IP Right Cessation
- 1993-08-11 EP EP9393306357A patent/EP0588487A3/en not_active Withdrawn
- 1993-08-19 JP JP20437593A patent/JP3739809B2/ja not_active Expired - Lifetime
-
2005
- 2005-09-12 JP JP2005263148A patent/JP2006024958A/ja active Pending
-
2008
- 2008-06-02 JP JP2008144142A patent/JP2008219046A/ja active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6435959A (en) * | 1987-07-30 | 1989-02-07 | Ricoh Kk | Thin film transistor |
JPH0284772A (ja) * | 1988-09-21 | 1990-03-26 | Seiko Epson Corp | 半導体装置の製造方法 |
JPH0362526A (ja) * | 1989-07-29 | 1991-03-18 | Sony Corp | 薄膜トランジスタの製法 |
JPH03292718A (ja) * | 1990-04-10 | 1991-12-24 | Seiko Epson Corp | 結晶性半導体薄膜の製造方法 |
JPH0443642A (ja) * | 1990-06-11 | 1992-02-13 | G T C:Kk | ゲート絶縁膜の形成方法 |
EP0474289A1 (en) * | 1990-09-04 | 1992-03-11 | Koninklijke Philips Electronics N.V. | A method for the fabrication of low leakage polysilicon thin film transistors |
JPH04206775A (ja) * | 1990-11-30 | 1992-07-28 | Casio Comput Co Ltd | 薄膜トランジスタ |
JPH06163898A (ja) * | 1992-08-19 | 1994-06-10 | American Teleph & Telegr Co <Att> | 薄膜トランジスターの製造方法 |
JP2006024958A (ja) * | 1992-08-19 | 2006-01-26 | At & T Corp | 薄膜トランジスターの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPH06163898A (ja) | 1994-06-10 |
US5322807A (en) | 1994-06-21 |
EP0588487A2 (en) | 1994-03-23 |
JP3739809B2 (ja) | 2006-01-25 |
TW242689B (ja) | 1995-03-11 |
EP0588487A3 (en) | 1994-09-28 |
JP2006024958A (ja) | 2006-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2008219046A (ja) | 薄膜トランジスターの製造方法 | |
US5275851A (en) | Low temperature crystallization and patterning of amorphous silicon films on electrically insulating substrates | |
JP3884203B2 (ja) | 半導体装置の製造方法 | |
JP2536426B2 (ja) | 半導体装置の製造方法 | |
JP4120938B2 (ja) | 高誘電率絶縁膜を有する半導体装置とその製造方法 | |
CN108198855A (zh) | 半导体元件、半导体基底及其形成方法 | |
KR20040076798A (ko) | 반도체 장치 및 그 제조 방법 | |
Chang et al. | Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric | |
JP2001102587A (ja) | 薄膜トランジスタおよびその製造方法ならびに半導体薄膜の製造方法 | |
JP4025542B2 (ja) | 絶縁膜形成方法、半導体装置及びその製造方法 | |
US8115263B2 (en) | Laminated silicon gate electrode | |
JP2003078116A (ja) | 半導体部材の製造方法及び半導体装置の製造方法 | |
US6323114B1 (en) | Stacked/composite gate dielectric which incorporates nitrogen at an interface | |
JPH06260644A (ja) | 半導体装置の製造方法 | |
JPS63119576A (ja) | 薄膜トランジスターの活性領域の形成方法 | |
JPH0613607A (ja) | 多結晶シリコン薄膜トランジスタ | |
JPH04186634A (ja) | 薄膜半導体装置の製造方法 | |
JPH11297988A (ja) | 金属シリサイドのスパイキング効果を防止するゲート電極製造方法 | |
JP3208604B2 (ja) | 薄膜トランジスタ及びその製造方法 | |
JPH11150277A (ja) | 薄膜トランジスタおよびその製造方法 | |
JPH0284716A (ja) | 半導体素子とその製造方法 | |
JP2000200883A (ja) | メモリセル用キャパシタの製作方法及び基板処理装置 | |
JP3064363B2 (ja) | Si薄膜の形成方法 | |
JP2635086B2 (ja) | 半導体装置の製造方法 | |
JP3143610B2 (ja) | 薄膜絶縁ゲイト型半導体装置およびその作製方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080602 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081006 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20090106 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20090122 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090206 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100301 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100601 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100604 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20100901 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20101004 |