CN108198855A - 半导体元件、半导体基底及其形成方法 - Google Patents

半导体元件、半导体基底及其形成方法 Download PDF

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CN108198855A
CN108198855A CN201710201928.XA CN201710201928A CN108198855A CN 108198855 A CN108198855 A CN 108198855A CN 201710201928 A CN201710201928 A CN 201710201928A CN 108198855 A CN108198855 A CN 108198855A
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layer
compound semiconductor
group iii
silicon
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CN108198855B (zh
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薛芳昌
林恒光
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Nuvoton Technology Corp
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Nuvoton Technology Corp
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

本发明提供一种半导体元件、半导体基底及其形成方法。半导体基底包括第一含硅层、单晶态III‑V族化合物半导体层以及非晶态III‑V族化合物半导体层。第一含硅层具有第一区以及第二区。单晶态III‑V族化合物半导体层配置于第一区的第一含硅层上。非晶态III‑V族化合物半导体层配置于第二区的第一含硅层上。

Description

半导体元件、半导体基底及其形成方法
技术领域
本发明是有关于一种半导体元件、半导体基底及其形成方法。
背景技术
近年来，以III-V族化合物半导体为基础的高电子迁移率晶体管(high electronmobility transistor；HEMT)因为其低阻值、高击穿电压以及快速开关切换频率等特性，在高功率电子元件领域获得相当大的关注。具体来说，将III-V族化合物半导体外延成长在硅基底的技术被广泛地研究。然而，III-V族化合物半导体元件至今仍无法与硅元件有效地整合在一起，使其应用层面受限。
发明内容
有鉴于此，本发明提供一种半导体元件、半导体基底及其形成方法，可抑制形成于此半导体基底上的元件之间的干扰。
本发明的半导体基底包括第一含硅层、单晶态III-V族化合物半导体层以及非晶态III-V族化合物半导体层。第一含硅层具有第一区以及第二区。单晶态III-V族化合物半导体层配置于第一区的第一含硅层上。非晶态III-V族化合物半导体层配置于第二区的第一含硅层上。
在本发明的一实施例中，上述的半导体基底中，单晶态III-V族化合物半导体层与非晶态III-V族化合物半导体层接触。
在本发明的一实施例中，上述的半导体基底中，单晶态III-V族化合物半导体层与非晶态III-V族化合物半导体层的组成相同。
在本发明的一实施例中，上述的半导体基底中，单晶态III-V族化合物半导体层与非晶态III-V族化合物半导体层各自包括第一氮化镓层、氮化铝镓层以及第二氮化镓层。第一氮化镓层配置于第一含硅层上。氮化铝镓层配置于第一氮化镓层上。第二氮化镓层配置于氮化铝镓层上。
在本发明的一实施例中，上述的半导体基底中，单晶态III-V族化合物半导体层还延伸至非晶态III-V族化合物半导体层与第一含硅层之间，且单晶态III-V族化合物半导体层于第一区的厚度大于单晶态III-V族化合物半导体层于第二区的厚度。
在本发明的一实施例中，上述的半导体基底还包括绝缘层与第二含硅层。绝缘层配置于非晶态III-V族化合物半导体层上。第二含硅层配置于绝缘层上。
在本发明的一实施例中，上述的半导体基底中，第一含硅层具有<111>晶面，而第二含硅层具有<100>晶面。
本发明的半导体元件包括第一含硅层、单晶态III-V族化合物半导体层、非晶态III-V族化合物半导体层、第一元件以及第二元件。第一含硅层具有第一区以及第二区。单晶态III-V族化合物半导体层配置于第一区的第一含硅层上。非晶态III-V族化合物半导体层配置于第二区的第一含硅层上。第一元件配置于单晶态III-V族化合物半导体层上。第二元件配置于非晶态III-V族化合物半导体层上。
在本发明的一实施例中，上述的半导体元件中，单晶态III-V族化合物半导体层与非晶态III-V族化合物半导体层的组成相同且彼此接触。
在本发明的一实施例中，上述的半导体元件中，第一元件包括栅极、两块状物、源极以及漏极。两块状物位于栅极两侧。源极与漏极分别穿过该些块状物，其中该些块状物的材料包括三元化合物或四元化合物。
在本发明的一实施例中，上述的半导体元件还包括绝缘层以及第二含硅层。绝缘层配置于非晶态III-V族化合物半导体层上。第二含硅层配置于绝缘层上，其中第二元件配置于第二含硅层上。
在本发明的一实施例中，上述的半导体元件中，第一含硅层具有<111>晶面，而第二含硅层具有<100>晶面。
在本发明的一实施例中，上述的半导体元件中，单晶态III-V族化合物半导体层还延伸至非晶态III-V族化合物半导体层与第一含硅层之间，且单晶态III-V族化合物半导体层于第一区的厚度大于单晶态III-V族化合物半导体层于第二区的厚度，使得非晶态III-V族化合物半导体层的底部低于第一元件在运作时于单晶态III-V族化合物半导体层产生的二维电子气的区域。
本发明的半导体的形成方法包括下列步骤。提供第一含硅层，第一含硅层具有第一区以及第二区。于第一区以及第二区的第一含硅层上形成单晶态III-V族化合物半导体层。进行处理步骤，使得第二区的单晶态III-V族化合物半导体层至少部分转化为非晶态III-V族化合物半导体层。
在本发明的一实施例中，上述的半导体基底的形成方法中，处理步骤包括进行注入制造工艺。
在本发明的一实施例中，上述的半导体基底的形成方法中，注入制造工艺所使用的注入源包括氮、氩、碳、氟或其组合。
在本发明的一实施例中，上述的半导体基底的形成方法中，注入制造工艺的能量为1KeV至600KeV，剂量为1012cm-3至1016cm-3。
在本发明的一实施例中，上述的半导体基底的形成方法中，处理步骤使第二区的单晶态III-V族化合物半导体层完全转化为非晶态III-V族化合物半导体层。
在本发明的一实施例中，上述的半导体基底的形成方法还包括下列步骤。于非晶态III-V族化合物半导体层上形成绝缘层。于绝缘层上形成一第二含硅层。
在本发明的一实施例中，上述的半导体基底的形成方法中，第一含硅层的晶面与第二含硅层的晶面不同。
基于上述，藉由本发明的方法，可简单地将III-V族化合物半导体元件与硅元件有效地整合在一起，将形成于不同区上的元件有效地隔离。因此，可抑制位于半导体基底的不同区的元件之间的干扰。
附图说明
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
图1A至图1C是依照本发明一实施例所绘示的一种半导体基底的形成方法的剖面示意图。
图1D至图1F是依照本发明一实施例所绘示的一种半导体元件的形成方法的剖面示意图。
图2至图6是依照本发明多个实施例所绘示的半导体元件的剖面示意图。
符号说明：
10：第一区
20：第二区
100：第一含硅层
102、102b、102b1：单晶态III-V族化合物半导体层
102a、102a1：非晶态III-V族化合物半导体层
104、104b、104b1：单晶态第一氮化镓层
104a、104a1：非晶态第一氮化镓层
106、106b：单晶态氮化铝镓层
106a：非晶态氮化铝镓层
108、108b：单晶态第二氮化镓层
108a：非晶态第二氮化镓层
110、110a：光掩膜层
112：绝缘层
114：第二含硅层
116、124：保护层
118：半导体基底
120、122、320、322、420、422：块状物
144、344、444、670：第一元件
146、546、672：第二元件
156、356、456、556、656：半导体元件
158、358、458：二维电子气
324、326、424、426：III-V族化合物半导体层
548、550：元件
D1、D2、D3：漏极
G1、G2、G3：栅极
I：注入制造工艺
S1、S2、S3：源极
具体实施方式
图1A至图1C是依照本发明一实施例所绘示的一种半导体基底的形成方法的剖面示意图。
请参照图1A，半导体基底的形成方法包括下列步骤。首先，提供第一含硅层100，其具有第一区10以及第二区20。在一实施例中，第一含硅层100可为具有＜111＞晶面的单晶硅层。
接着，于第一区10以及第二区20的第一含硅层100上形成单晶态III-V族化合物半导体层102。形成单晶态III-V族化合物半导体层102的方法包括进行外延成长(epitaxialgrowth)制造工艺，且单晶态III-V族化合物半导体层102可包括多数层。在一实施例中，单晶态III-V族化合物半导体层102可包括单晶态第一氮化镓层104、单晶态氮化铝镓层106以及单晶态第二氮化镓层108。单晶态第一氮化镓层104可配置于第一含硅层100上。单晶态氮化铝镓层106可配置于单晶态第一氮化镓层104上。单晶态第二氮化镓层108可配置于单晶态氮化铝镓层106上。
之后，在第一含硅层100上形成光掩膜层110。在一实施例中，光掩膜层110覆盖第一区10的单晶态III-V族化合物半导体层102，而裸露出第二区20的单晶态III-V族化合物半导体层102的顶面。在一实施例中，光掩膜层110的材料包括(例如但不限于)氧化硅。
接着，请参照图1B，进行处理步骤，使得第二区20的单晶态III-V族化合物半导体层102至少部分地转化为非晶态III-V族化合物半导体层。在一实施例中，于上述处理步骤之后，第二区20的单晶态III-V族化合物半导体层102完全地转化为非晶态III-V族化合物半导体层102a，留下第一区10的单晶态III-V族化合物半导体层102b。非晶态III-V族化合物半导体层102a包括非晶态第一氮化镓层104a、非晶态氮化铝镓层106a以及非晶态第二氮化镓层108a。单晶态III-V族化合物半导体层102b包括单晶态第一氮化镓层104b、单晶态氮化铝镓层106b以及单晶态第二氮化镓层108b。
本发明的处理步骤用于非晶化第二区20的至少部分膜层，故可视为非晶化步骤。在一实施例中，上述处理步骤包括进行注入制造工艺I，其所使用的注入源可包括氮、氩、碳、氟或其组合。举例来说，注入制造工艺I的能量可为1KeV至600KeV，且其剂量可为1012cm-3至1016cm-3，但本发明并不以此为限。在一实施例中，第一区10的单晶态III-V族化合物半导体层102b与第二区20的非晶态III-V族化合物半导体层102a的组成实质上相同。
本发明的处理步骤将第二区20的单晶态III-V族化合物半导体层转化为非晶态III-V族化合物半导体层102a，进而显著地提高其电阻值。在一实施例中，第二区20的非晶态III-V族化合物半导体层102a可视为绝缘体。
之后，请参照图1C，可于非晶态III-V族化合物半导体层102a上形成绝缘层112。在一实施例中，绝缘层112的材料包括(例如但不限于)氧化硅。接着，可于绝缘层112上形成第二含硅层114，其中第一含硅层100的晶面可与第二含硅层114的晶面不同。在一实施例中，第一含硅层100可为具有＜111＞晶面的单晶硅层，而第二含硅层114可为具有＜100＞晶面的单晶硅层。以此方式，在第二区20上可形成绝缘体上硅(silicon on insulator)的结构。接着，可在第二含硅层上114形成保护层116，以覆盖第二含硅层114。保护层116的材料可包括(例如但不限于)氧化硅。至此，完成本发明的半导体基底118的制作。
以下，将参照图1C说明本发明的半导体基底118的结构。请参照图1C，半导体基底118包括第一含硅层100、单晶态III-V族化合物半导体层102b以及非晶态III-V族化合物半导体层102a。第一含硅层100具有第一区10以及第二区20。单晶态III-V族化合物半导体层102b配置于第一区10的第一含硅层100上。另外，非晶态III-V族化合物半导体层102a配置于第二区20的第一含硅层100上。
在一实施例中，单晶态III-V族化合物半导体层102b可与非晶态III-V族化合物半导体层102a接触。单晶态III-V族化合物半导体层102b与非晶态III-V族化合物半导体层102a的组成可实质上相同，仅晶态不同。单晶态III-V族化合物半导体层102b可包括依序配置于第一区10的第一含硅层100上的单晶态第一氮化镓层104b、单晶态氮化铝镓层106b以及单晶态第二氮化镓层108b。相似地，非晶态III-V族化合物半导体层102a可包括依序配置于第二区20的第一含硅层100上的非晶态第一氮化镓层104a、非晶态氮化铝镓层106a以及非晶态第二氮化镓层108a。
半导体基底118可还包括绝缘层112与第二含硅层114，其中绝缘层112配置于非晶态III-V族化合物半导体层102a上，且第二含硅层114配置于绝缘层112上。第一含硅层100例如具有＜111＞晶面，且第二含硅层114例如具有＜100＞晶面。另外，半导体基底118可还包括保护层116，其覆盖第二含硅层114。
特别要说明的是，由于半导体基底118的第二区20的非晶态III-V族化合物半导体层102a的电阻值相当高，所以在后续制造工艺中形成于第二区20上的元件可与形成于第一区10上的元件有效地隔离。因此，可抑制第一区10上的元件与第二区20上的元件之间的干扰。
此外，本发明的半导体基底118中，第一区10的单晶态III-V族化合物半导体层102b与第二区20的非晶态III-V族化合物半导体层102a形成为直接接触，因此，在后续制造工艺中形成于第一区10上的元件可紧邻于形成于第二区20上的元件，两者之间的间距可大幅降至微米等级。如此一来，可将不同的元件形成于半导体基底118上，以形成系统芯片(system on chip)，且可抑制不同的元件之间的干扰。
图1D至图1F是依照本发明一实施例所绘示的一种半导体元件的形成方法的剖面示意图。
首先，提供如图1C所示的半导体基底118。接着，请参照图1D至图1F，于单晶态III-V族化合物半导体层102b上形成第一元件144。在一实施例中，第一元件144可为HEMT元件。如图1D所示，于单晶态III-V族化合物半导体层102b上形成两个块状物120与122。形成两个块状物120与122的方法包括先将光掩膜层110图案化，以形成光掩膜层110a。接着，分别于光掩膜层110a的两侧形成块状物120及122。具体来说，块状物120可形成于绝缘层112与光掩膜层110a之间，且光掩膜层110a可形成于块状物102与块状物122之间。
在一实施例中，块状物120与122中的每一者可包括三元化合物或四元化合物。三元化合物可包括(但不限于)铟、铝、及氮。四元化合物可包括(但不限于)铟、铝、镓以及氮。上述三元化合物或四元化合物可为单层或多层结构。在一实施例中，三元化合物可包括InAlN，或由InAlN与AlN所组成。在一实施例中，四元化合物可由InAlGaN所组成。
此外，块状物120与122的形成方法包括进行选择性外延再成长(selectivelyepitaxial regrowth)，其仅会在裸露出的单晶态III-V族化合物半导体层102b上外延成长，且其制造工艺温度大约在800℃至1200℃之间。由于第二含硅层114可被保护层116所覆盖，所以在形成块状物120与122时可避免第二含硅层114受到高温破坏。
接着，可在第一区10与第二区20上形成保护层124。具体来说，保护层124可覆盖块状物120与122、光掩膜层110a、非晶态III-V族化合物半导体层102a以及保护层116。保护层124的材料可包括(但不限于)氧化硅(SiO2)、氮化硅(Si3N4)、氧化铝(Al2O3)或其组合。
之后，请参照图1F，形成栅极G1、漏极D1以及源极S1。在一实施例中，先形成漏极D1以及源极S1，再形成栅极G1。具体地说，漏极D1/源极S1形成为穿过保护层124、块状物120/122，并延伸至单晶态III-V族化合物半导体层102b的单晶态第二氮化镓层108b以及单晶态氮化铝镓层106b中。形成源极S1/漏极D1的方法包括先于块状物122/120中分别形成金属插塞，再进行高温扩散制造工艺，使金属插塞的金属向下扩散至第二氮化镓层108b以及单晶态氮化铝镓层106b中。源极S1/漏极D1的材料包括(例如但不限于)铝钛合金，或其他可与单晶态III-V族化合物半导体层102b形成欧姆接触(ohmic contact)的材料。
接着，栅极G1形成为穿过保护层124、光掩膜层110a。形成栅极G1的方法包括先于保护层124、光掩膜层110a中形成开口，再填入栅极金属于开口中。栅极金属的材料包括(例如但不限于)氮化钛、镍或其他可与单晶态III-V族化合物半导体层102b形成肖特基接触(schottky contact)的材料。在一实施例中，栅极G1除了可为如图1F所示的结构之外，也可为金属在绝缘体上(metal-on-insulator,MIS)结构。
之后，于非晶态III-V族化合物半导体层102a上形成第二元件146。在一实施例中，第二元件146包括金属氧化物半导体元件。第二元件146包括栅极G2以及位于栅极G2两侧的漏极D2与源极S2。栅极G2、漏极D2与源极S2形成为穿过保护层124与116，并与第二含硅层114中的掺杂区(未绘示)电连接。至此，完成本发明的半导体元件156的制作。
以下，将参照图1F说明本发明的半导体元件156的结构。请参照图1F，半导体元件156包括半导体基底118、第一元件144以及第二元件146。第一元件144配置于单晶态III-V族化合物半导体层102b上，且第二元件146配置于非晶态III-V族化合物半导体层102a上。
第一元件144可包括栅极G1、块状物120与块状物122、漏极D1与源极S1。块状物120与块状物122位于栅极G1的两侧，且漏极D1与源极S1分别穿过块状物120与块状物122。在一实施例中，块状物120与块状物122的材料包括氮化铝铟(InAlN)。第二元件146可包括栅极G2、漏极D2与源极S2。
特别要说明的是，第一元件144在运作时，可形成二维电子气158，其位于第一氮化镓层104b中邻近于氮化铝镓层106b的区域。二维电子气158可提高第一元件144的操作速度。另外，由于第二元件146下方的非晶态III-V族化合物半导体层102a的电阻值相当高，故上述的二维电子气158并不会延伸至第二元件146的下方。因此，第二元件146在运作时，可避免受到第一元件144的干扰。
基于上述，由于半导体基底118的第二区20的非晶态III-V族化合物半导体层102a的电阻值相当高，所以形成于第二区20上的第二元件146可与形成于第一区10上的第一元件144有效地隔离。因此，可抑制第一元件144与第二元件146之间的干扰。
在上述实施例中，图1B的处理步骤将第二区20的单晶态III-V族化合物半导体层102完全地转化为非晶态III-V族化合物半导体层102a，其用于说明，并不用于限定本发明。在另一实施例中(请参照图2)，图1B的处理步骤仅将第二区20的单晶态III-V族化合物半导体层102部分地转化为非晶态III-V族化合物半导体层102a1，留下第一区10的单晶态III-V族化合物半导体层102b1。更具体地说，第二区20的单晶态第二氮化镓层108与单晶态氮化铝镓层106均完全转化为非晶态第二氮化镓层108a以及非晶态氮化铝镓层106a，而第二区20的单晶态第一氮化镓层104仅部分转化为非晶态第一氮化镓层104a1。
第一区10的单晶态III-V族化合物半导体层102b1包括单晶态第一氮化镓层104b1、单晶态氮化铝镓层106b以及单晶态第二氮化镓层108b，且单晶态III-V族化合物半导体层102b1可还延伸至第二区20的非晶态III-V族化合物半导体层102a1与第一含硅层100之间。
另外，单晶态III-V族化合物半导体层102b1于第一区10的厚度大于单晶态III-V族化合物半导体层102b1于第二区20的厚度，使得第二区20的非晶态III-V族化合物半导体层102a1的底部低于第一元件144在运作时于单晶态III-V族化合物半导体层102b1产生的二维电子气158的区域。
据此，第一元件144所形成的二维电子气158亦并不会延伸至第二元件146的下方。因此，第二元件146在运作时，不会受到第一元件144的干扰。
图3至图6是依照本发明所绘示多个实施例的半导体元件的剖面示意图。图3至图6的半导体元件与图1F的半导体元件类似，差异处将详细说明如下，相同处则不再赘述。
图3的半导体元件356与图1F所示的半导体元件156相似，其差异处在于：图3的块状物320与322为多层结构，而图1F的块状物120与122为单层结构。
更具体地说，图3的第一元件344的块状物320与322中的每一者均包括两个III-V族化合物半导体层324与位于III-V族化合物半导体层324之间的III-V族化合物半导体层326。在一实施例中，III-V族化合物半导体层324的材料包括氮化铝铟，且III-V族化合物半导体层326的材料包括氮化铝(AlN)。
图4的半导体元件456与图1F所示的半导体元件156相似，其差异处在于：图4的块状物420与422为超晶格(superlattice)结构，而图1F的块状物120与122为单层结构。
更具体地说，图4的第一元件444的块状物420与422中的每一者均包括交互堆迭的多层III-V族化合物半导体层424与多层III-V族化合物半导体层426，以形成超晶格结构。
在一实施例中，块状物420与422的最底层为III-V族化合物半导体层424。在另一实施例中，块状物420与422的最底层为III-V族化合物半导体层426。此外，本发明并不对III-V族化合物半导体层424的数量与III-V族化合物半导体层426的数量作限制。在一实施例中，III-V族化合物半导体层424的材料包括氮化铝铟，且III-V族化合物半导体层426的材料包括氮化铝。
与图1F所示的第一元件144相比，图3的第一元件344与图4的第一元件444在运作时可产生浓度更高的二维电子气358、458。因此，可进一步第提高第一元件344、444的操作速度。
在图4所示的实施例中，III-V族化合物半导体层424的能隙(bandgap)可与III-V族化合物半导体层426的能隙相异。另外，每一III-V族化合物半导体层424与每一III-V族化合物半导体层426的厚度仅为数纳米。据此，可在第一元件444中形成多重量子井(multiple quantum wells)，而进一步提高二维电子气458的浓度。换言之，可进一步地提高第一元件444的操作速度。
图5的半导体元件556与图1F所示的半导体元件156相似，其差异处在于：图5的半导体元件556中的第二元件546可包括彼此相邻的元件548与元件550。元件548可包括栅极G2、漏极D2与源极S2。元件550可包括栅极G3、漏极D3与源极S3。在一实施例中，元件548与元件550构成互补式金属氧化物半导体(CMOS)元件。
图6的半导体元件656与图1F所示的半导体元件156相似，其差异处在于：图6的半导体元件656中的第一元件670与第二元件672不限于上述的元件，本领域技术人员可依据其需求选用适当的元件作为第一元件670与第二元件672。
在一实施例中，第一元件670为III-V族化合物半导体元件，例如HEMT元件；而第二元件672为硅元件，例如金属氧化物半导体元件、二极管元件、微波元件、高功率元件、高压元件或其组合。
综上所述，藉由本发明的方法，可简单地将III-V族化合物半导体元件与硅元件有效地整合在一起，将形成于不同区上的元件有效地隔离。因此，可抑制位于半导体基底的不同区的元件之间的干扰。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附的权利要求所界定者为准。

Claims (10)

1.一种半导体基底，其特征在于，包括：
一第一含硅层，具有一第一区以及一第二区；以及
一单晶态III-V族化合物半导体层，配置于所述第一区的所述第一含硅层上；以及
一非晶态III-V族化合物半导体层，配置于所述第二区的所述第一含硅层上。
2.如权利要求1所述的半导体基底，其特征在于，所述单晶态III-V族化合物半导体层与所述非晶态III-V族化合物半导体层各自包括：
一第一氮化镓层，配置于所述第一含硅层上；
一氮化铝镓层，配置于所述第一氮化镓层上；以及
一第二氮化镓层，配置于所述氮化铝镓层上。
3.如权利要求1所述的半导体基底，其特征在于，所述单晶态III-V族化合物半导体层还延伸至所述非晶态III-V族化合物半导体层与所述第一含硅层之间，且所述单晶态III-V族化合物半导体层于所述第一区的厚度大于所述单晶态III-V族化合物半导体层于所述第二区的厚度。
4.一种半导体元件，其特征在于，包括：
一第一含硅层，具有一第一区以及一第二区；以及
一单晶态III-V族化合物半导体层，配置于所述第一区的所述第一含硅层上；
一非晶态III-V族化合物半导体层，配置于所述第二区的所述第一含硅层上；
一第一元件，配置于所述单晶态III-V族化合物半导体层上；以及
一第二元件，配置于所述非晶态III-V族化合物半导体层上。
5.如权利要求4所述的半导体元件，其特征在于，所述单晶态III-V族化合物半导体层与所述非晶态III-V族化合物半导体层的组成相同且彼此接触。
6.如权利要求4所述的半导体元件，其特征在于，所述第一元件包括：
一栅极：
两块状物，位于所述栅极两侧；以及
一源极与一漏极，分别穿过所述块状物，
其中所述块状物的材料包括三元化合物或四元化合物。
7.如权利要求4所述的半导体元件，其特征在于，还包括：
一绝缘层，配置于所述非晶态III-V族化合物半导体层上；以及
一第二含硅层，配置于所述绝缘层上，
其中所述第二元件配置于所述第二含硅层上。
8.如权利要求4所述的半导体元件，其特征在于，所述单晶态III-V族化合物半导体层还延伸至所述非晶态III-V族化合物半导体层与所述第一含硅层之间，且所述单晶态III-V族化合物半导体层于所述第一区的厚度大于所述单晶态III-V族化合物半导体层于所述第二区的厚度，使得所述非晶态III-V族化合物半导体层的底部低于所述第一元件在运作时于所述单晶态III-V族化合物半导体层产生的二维电子气的区域。
9.一种半导体基底的形成方法，其特征在于，包括：
提供一第一含硅层，所述第一含硅层具有一第一区以及一第二区；
于所述第一区以及所述第二区的所述第一含硅层上形成一单晶态III-V族化合物半导体层；以及
进行一处理步骤，使得所述第二区的所述单晶态III-V族化合物半导体层至少部分转化为一非晶态III-V族化合物半导体层。
10.如权利要求9所述的半导体基底的形成方法，其特征在于，所述处理步骤包括进行一注入制造工艺。
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