TW201618193A - 用於製作包括具有不同應變狀態之電晶體通道之半導體結構之方法及相關半導體結構 - Google Patents

用於製作包括具有不同應變狀態之電晶體通道之半導體結構之方法及相關半導體結構 Download PDF

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TW201618193A
TW201618193A TW104129408A TW104129408A TW201618193A TW 201618193 A TW201618193 A TW 201618193A TW 104129408 A TW104129408 A TW 104129408A TW 104129408 A TW104129408 A TW 104129408A TW 201618193 A TW201618193 A TW 201618193A
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semiconductor layer
region
strained semiconductor
strained
transistor channel
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TW104129408A
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馬瑞姆 山達卡
碧言 阮
伊歐納特 朗度
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梭意泰科公司
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Abstract

本發明揭示製作一半導體結構之方法，其包括：將離子植入至一多層基板上之一應變半導體層之一第二區域中以非晶化該應變半導體層之該第二區域中之結晶半導體材料之一部分而不非晶化該應變半導體層之一第一區域。使該非晶區域再結晶，且使元素在該半導體層內擴散以提高該應變半導體層之該第二區域之一部分中之該等經擴散元素之一濃度並相對於該應變半導體層之該第一區域之一應變狀態而變更該應變半導體層之該第二區域之一應變狀態。形成各自包含該半導體層之該第一區域之一部分之第一複數個電晶體通道結構，且形成各自包含該半導體層之該第二區域之一部分之第二複數個電晶體通道結構。

Description

用於製作包括具有不同應變狀態之電晶體通道之半導體結構之方法及相關半導體結構
本發明之實施例係關於可用以製作在一半導體基板上之一共同層中具有不同應力狀態之n型金屬氧化物半導體(NMOS)場效應電晶體及p型金屬氧化物半導體(PMOS)場效應電晶體之方法，且係關於使用此類方法製作之半導體結構及器件。
諸如微處理器及記憶體器件之半導體器件採用固體狀態電晶體作為其積體電路之一基本初級操作結構。常見地在半導體結構及器件中採用之一種類型之電晶體係場效應電晶體(FET)，通常包括一源極觸點、一汲極觸點，以及一或多個閘極觸點。一半導電通道區域在源極觸點與汲極觸點之間延伸。一或多個pn接面界定於源極觸點與閘極觸點之間。閘極觸點定位成毗鄰通道區域之至少一部分，且通道區域之導電性由於一電場之存在而變更。因此，藉由將一電壓施加於閘極觸點而將一電場提供於通道區域內。因此，例如，電流在一電壓經施加至閘極觸點時可自源極觸點流動穿過電晶體以穿過通道區域而到達汲極觸點，但在無施加至閘極觸點之一電壓時不可自源極觸點流動穿 過電晶體以到達汲極觸點。
最近，已經發展採用被稱為「鰭片」之離散、細長通道結構之場效應電晶體(FET)。此一電晶體在此項技術中通常被稱為一「鰭式FET」。在此項技術中已提出鰭式FET之諸多不同組態。
一鰭式FET之細長通道結構或鰭片包含可係經摻雜n型或p型之一半導體材料。亦已論證，在n型半導體材料處於一拉張應力狀態中時，n型經摻雜半導體材料之導電性可經改良，且在p型半導體材料處於一壓縮應力狀態中時，p型半導體材料之導電性可經改良。
提供此概述以用一簡化形式介紹一組概念。此等概念在下文的本發明之實例性實施例之詳細說明中以進一步細節加以闡述。此概述並不意欲鑑別所申請標的物之關鍵特徵或重要特徵，亦並不意欲用於限制所申請標的物之範疇。
在某些實施例中，本發明包括一種製作一半導體結構之方法。提供一多層基板，該多層基板包括：一基底基板；一埋置氧化物層，其在該基底基板之一表面上方；及一應變半導體層，其在該埋置氧化物層上方在該埋置氧化物層之與該基底基板相對之一側部上。該應變半導體層包含結晶半導體材料。該方法進一步包括：將離子植入至該應變半導體層之一第二區域中而不將離子植入至該應變半導體層之一第一區域中，且將該應變半導體層之該第二區域中之該結晶半導體材料之一部分轉變為非晶材料，使得該應變半導體層之該第二區域具有一非晶區域及一下伏結晶區域。使該非晶區域再結晶，並將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之另一部分中，以便提高該應變半導體層之該第二區域之該另一部分中之該等經擴散元素之一濃度並變更該應變半導體層之該第二區域之一應變狀態，使得該應變半導體層之該第二區域處於不同於該應變半導 體層之該第一區域之一應變狀態的一應變狀態中。形成各自包含該半導體層之該第一區域之一部分之第一複數個電晶體通道結構，且形成各自包含該半導體層之該第二區域之一部分之第二複數個電晶體通道結構。
在額外實施例中，本發明包括可藉由本文中揭示之方法製作之半導體結構。舉例而言，在某些實施例中，本發明包括一種半導體結構，其包含：一基底基板；一埋置氧化物層，其在該基底基板之一表面上方；及第一複數個電晶體通道結構及第二複數個電晶體通道結構，其等安置於該埋置氧化物層上方在該埋置氧化物層之與該基底基板相對之一側部上之一共同平面中。該第二複數個電晶體通道結構之每一電晶體通道結構包含包括兩個或兩個以上元素之一經凝縮應變半導體層。該第一複數個電晶體通道結構之每一電晶體通道結構包含一未經凝縮應變半導體層。該第二複數個電晶體通道結構之該等電晶體通道結構具有不同於該第一複數個電晶體通道結構之該等電晶體通道結構之一晶向應變的一晶向應變。
100‧‧‧多層基板
102‧‧‧基底基板
104‧‧‧埋置氧化物層
106‧‧‧應變半導體層
106A‧‧‧半導體層之第一區域/應變半導體層之第一區域
106B‧‧‧半導體層之第二區域/應變半導體層之第二區域
108‧‧‧氧化物層
110‧‧‧經圖案化遮罩層
112‧‧‧非晶區域
114‧‧‧下伏結晶區域
120‧‧‧經再結晶區域
122‧‧‧氧化物層
124‧‧‧額外半導體材料
132A‧‧‧鰭片結構
132B‧‧‧鰭片結構
134‧‧‧淺溝槽隔離結構
140‧‧‧多層基板
142‧‧‧鰭片結構
142A‧‧‧鰭片結構
142B‧‧‧鰭片結構
144‧‧‧鈍化氧化物層/氧化物層
146‧‧‧氮化物層
148‧‧‧遮罩層
150‧‧‧非晶區域
154‧‧‧經再結晶區域
156‧‧‧氧化物層
160‧‧‧鰭式場效應電晶體
162‧‧‧源極區域
164‧‧‧汲極區域
166‧‧‧導電閘極/閘極
168‧‧‧介電材料
儘管說明書以特定地指出且明確地主張被認為係本發明之實施例之內容的申請專利範圍進行總結，但當結合附圖閱讀時可自對本發明之實施例之某些實例之闡述更容易地斷定本發明之實施例之優點，在附圖中：圖1係圖解說明根據本發明之實施例可被採用之包括一應變半導體層之一多層基板之一簡化的示意性地圖解說明之剖面視圖；圖2圖解說明在多層基板之一部分上方施加一遮罩層之後的圖1之基板，且圖解說明離子至多層基板之一未經遮罩部分中的應變半導體層中之植入；圖3係圖1及圖2之基板之一部分之一放大視圖，其展示在將離子 植入於半導體層之一部分中以使得在半導體層內形成一非晶區域之後的該半導體層之該部分；圖4類似於圖3且圖解說明在使該半導體層之該部分中之非晶區域再結晶之後的該半導體層之該部分；圖5類似於圖3及圖4，且圖解說明在自半導體層之表面移除一個氧化物層之後的該半導體層之該部分；圖6類似於圖3至圖5，且圖解說明在於半導體層上磊晶地沈積額外半導體材料以便加厚該半導體層之後的該半導體層之該部分；圖7類似於圖3至圖6且圖解說明在將來自該半導體層之一個區域之元素擴散至該半導體層之另一區域中以便使該半導體層之一區域富集有一或多個元素並變更該半導體層之該區域之一應變狀態之後的該半導體層之該部分；圖8係圖解說明使用參考圖1至圖7闡述之方法製作之一半導體結構的一簡化的示意性地圖解說明之剖面視圖，該半導體結構包含一絕緣體上半導體(SeOI)基板，該絕緣體上半導體(SeOI)基板包括在一基底基板上之一埋置氧化物層上方之具有不同應變狀態之區域之一半導體層；圖9係圖解說明可由圖8之SeOI基板製作且包括形成於半導體層之一區域中之具有一第一應變狀態之第一複數個鰭片結構以及形成於半導體層之一區域中之具有一不同第二應變狀態之第二複數個鰭片結構之一半導體結構的一簡化的示意性地圖解說明之剖面視圖；圖10係圖解說明可由圖8之SeOI基板製作且包括形成於不同應變狀態區域之間的一淺溝槽隔離結構之另一半導體結構之一簡化的示意性地圖解說明之剖面視圖；圖11係圖解說明根據本發明之實施例可採用之與圖1之多層基板相似之另一多層基板之一簡化的示意性地圖解說明之剖面視圖，該另 一多層基板包括一應變半導體層；圖12圖解說明由圖11之基板之應變半導體層形成之複數個鰭片結構；圖13圖解說明離子至某些但非所有鰭片結構中之植入；圖14係圖13之基板之一部分之一放大視圖，其展示在離子植入至某些鰭片結構中並在該等鰭片結構內形成一非晶區域之後的該等鰭片結構；圖15類似於圖14且圖解說明在使鰭片結構中之非晶區域再結晶之後的該等鰭片結構；圖16類似於圖14及圖15，且圖解說明在使來自鰭片結構之一個區域之元素擴散至該等鰭片結構之另一區域中以便使該等鰭片結構之一區域富集有一或多個元素且變更該等鰭片結構之一應變狀態之後的該等鰭片結構；及圖17圖解說明一鰭式FET電晶體之一實例性結構。
本文中所呈現之說明並非意欲作為任一特定半導體結構、器件、系統或方法之實際視圖，而僅係用以闡述本方面之實施例之理想化表示。
本文中所使用之任何標題皆不應視為限制由以下申請專利範圍及其合法等效物界定之本發明之實施例之範圍。在整個說明書通篇中，在任一具體標題中闡述之概念通常適用於其他章節中。
在說明及申請專利範圍中之術語第一及第二係用於在類似元件之間做出區分。
如本文中所使用，術語「鰭片」及「鰭片結構」意指具有一長度、一寬度及一高度之半導體材料之一細長、三維有限且有界體積，其中長度大於寬度。在某些實施例中，鰭片之寬度及高度可沿著鰭片 之長度而變化。
下文參考諸圖闡述可用以製作半導體結構之方法，以及可使用此類方法製作之半導體結構。
參考圖1，可提供一多層基板100，多層基板100包括一基底基板102、在基底基板102之一表面上方之一埋置氧化物(BOX)層104，以及在BOX層104上方在BOX層104之與基底基板102相對之一側部上之一應變半導體層106。應變半導體層106可包含一應變矽層，且多層基板100可包含一絕緣體上應變矽(SSOI)基板。
基底基板102可包含(例如)半導體材料(例如，矽、碳化矽、鍺、一III-V半導體材料等)、一陶瓷材料(例如，氧化矽、氧化鋁、碳化矽等)或一金屬材料(例如，鉬等)之一晶粒或晶圓。在某些實施例中，基底基板102可具有一單晶或多晶微結構。在其他實施例中，基底基板102可係非晶的。基底基板102可具有範圍介於自(例如)約400μm至約900μm(例如，約750μm)之一厚度，不過亦可採用較厚或較薄基底基板102。
上覆於基底基板102上之層(諸如，BOX層104)可使用諸如(例如)化學汽相沈積(CVD)、原子層沈積(ALD)、物理汽相沈積(PLD)、汽相磊晶(VPE)、分子束磊晶(MBE)及熱氧化作用之數個不同過程中之任一者而磊晶經沈積、「生長」或以其他方式形成於基板上方。在額外實施例中，該等層可係使用已知過程而自另一施體基板轉移至基底基板102。
藉由實例而非限制方式，多層基板100可使用在此項技術中已知為SMART-CUT®過程之過程而形成，在該過程中，一半導體材料層自一施體結構轉移至接收基板(亦即，基底基板)，使得一個氧化物層(亦即，BOX層104)安置於接收基板與經轉移層半導體層之間。SMART-CUT®過程係在(例如)以下專利中闡述：讓與Bruel之美國專 利第RE39,484號(2007年2月6日頒佈)、讓與等人之美國專利第6,303,468號(2001年10月16日頒佈)、讓與等人之美國專利第6,335,258號(2002年1月1日頒佈)、讓與Moriceau等人之美國專利第6,756,286號(2004年6月29日頒佈)、讓與Aspar等人之美國專利第6,809,044號(2004年10月26日頒佈)，以及讓與Aspar等人之美國專利第6,946,365號(2005年9月20日)。
BOX層104可包含(例如)氧化物(例如，二氧化矽、氧化鋁、氧化鉿等)、氮化物(例如，氮化矽)、氮氧化物(例如，氮氧化矽)，或此類介電材料之一組合。BOX層104可係結晶或非晶的。BOX層104可具有(例如)介於約10nm與約200nm之間的一平均層厚度，不過在本發明之實施例中亦可採用較厚或較薄BOX層104。
應變半導體層106可包含一應變(壓縮或拉張)結晶半導體材料，諸如一拉伸應變矽(Si)層。在其他實施例中，應變半導體層106可包含應變鍺(Ge)、應變矽鍺(SiGe)，或一應變III-V半導體材料。因此，應變半導體材料106可具有展現高於(拉伸應變)或低於(壓縮地應變)一般地由在均衡狀態下呈獨立式塊體形式之各別半導體材料之晶體結構展現之鬆弛晶格參數之晶格參數的一晶體結構。應變半導體層106可具有約50nm或更小或甚至約10nm或更小之一平均層厚度。應變半導體層106可具有低於應變半導體層106之一臨界厚度之一平均層厚度。在其中應變半導體層106包含自一施體基板轉移至基底基板102之一應變矽層且其中應變半導體層106在層轉移過程之前磊晶生長於施體基板上之一SiGe緩衝層上之實施例中，應變矽層之臨界厚度可隨SiGe緩衝層中之鍺濃度而變化，其中該臨界厚度隨著鍺濃度增加而減小。亦可在本發明之實施例中採用較厚應變半導體材料層106。應變半導體層106可在其轉移至基底基板102之後使用磊晶沈積技術經加厚至大於其臨界厚度之一厚度，而不使應變鬆弛降級，如在(例如)Thean等人， Uniaxial-Biaxial Stress Hybridization for Super-Critical Strained-Si Directly On Insulator(SC-SSOI)PMOS With Different Channel Orientations，IEEE國際性(美國華盛頓哥倫比亞特區2005年電子器件大會)，第509至512頁中所揭示。
作為一非限制性具體實例，施體基板100之基底基板102可包含一單晶矽基板，BOX層104可包含二氧化矽(SiO2)，且應變半導體層106可包含拉伸應變單晶矽(sSi)，該拉伸應變單晶矽(sSi)具有低於其各別臨界厚度之一厚度以便避免起始鬆弛及在其晶體結構中形成局部化缺陷。
在某些實施例中，可係一原生氧化物層或經沈積氧化物之一個氧化物層108可存在於在應變半導體層106之與BOX層104相對之側部上的應變半導體層106之主表面上方。在其他實施例中，可不存在氧化物層108。
參考圖2，一經圖案化遮罩層110可提供於應變半導體層106上方。經圖案化遮罩層110可覆蓋應變半導體層106之一或多個區域，而應變半導體層106之其他區域可不被經圖案化遮罩層110覆蓋。作為一非限制性實例，圖2圖解說明被經圖案化遮罩層110覆蓋之應變半導體層之一第一區域106A，以及不被經圖案化遮罩層110覆蓋之應變半導體層之一第二區域106B。
經圖案化遮罩層110可包含一硬遮罩層材料，諸如一個氧化物層、一個氮化物層或一個氮氧化物層中之一或多者。經圖案化遮罩層110可藉由以下步驟而形成：在多層基板100上方沈積或以其他方式提供一連續硬遮罩材料層，且隨後使用一光微影遮罩及蝕刻過程圖案化硬遮罩材料，以在需要移除硬遮罩材料之部分以不覆蓋應變半導體層106之區域之位置處形成穿過硬遮罩材料之孔隙。在其他實施例中，經圖案化遮罩層110可包含一光阻遮罩材料。
繼續參考圖2，在形成經圖案化遮罩層110之後，可將離子植入至不被經圖案化遮罩層110覆蓋(如由方向性箭頭所指示)的應變半導體層106之一或多個區域(諸如，應變半導體層之第二區域106B)中，而不將離子植入至由經圖案化遮罩層110覆蓋的應變半導體層106之一或多個區域(諸如，應變半導體層之第一區域106A)中。離子可通過遮罩層110中之孔隙且至應變半導體層之第一區域106A中，而遮罩層110遮蔽應變半導體層之第二區域106B且阻止離子植入於其中。
在某些實施例中，可自應變半導體層106上方移除氧化物層108(若存在)，使得曝露應變半導體層106之一表面。然而，在其他實施例中，離子可穿過氧化物層108而植入至應變半導體層106中。
離子之植入可將應變半導體層106之結晶半導體材料之一部分轉變為非晶材料。因此，離子植入至其中的半導體層106之一或多個區域可具有一非晶區域112及一下伏結晶區域114，如在圖3之放大視圖中所圖解說明。
經植入離子可係不同於半導體層106之晶體結構中存在之至少一個元素之元素的離子。舉例而言，在其中應變半導體層包含應變矽(sSi)之實施例中，經植入離子可包含不同於矽之(例如)鍺離子。如此之原因在於具有相對於半導體層106中之其他元素之一不同原子半徑之經植入離子可用以隨後在後續處理中變更半導體層106之一應變狀態，如在下文以進一步細節闡述。
下文之表1對於以40KeV至50KeV之離子植入能量執行之一鍺離子植入過程之五(5)個不同劑量中之每一者，提供在半導體層106之層厚度下之一拉伸應變矽半導體層106中之鍺濃度及鍺含量之實例。
參考圖4，在將離子植入至應變半導體層106之一或多個區域中以使得該一或多個區域包括一非晶區域112及一下伏結晶區域114(如在圖3中所展示)之後，可使半導體層106之非晶區域112再結晶。舉例而言，在一爐中在高溫下執行之一退火過程可用以使非晶區域112再結晶且形成經再結晶區域120，如在圖4中所展示。在再結晶後，經再結晶區域120可由於存在具有相對於存在於最初形成之半導體層106中之至少一個元素(例如，矽)的一不同原子半徑之經植入離子(例如，鍺離子)而處於不同於應變半導體層之第一區域106A之一應變狀態(圖2)之一應變狀態中。
因此，在其中最初形成之應變半導體層106包含拉伸應變矽且經 植入離子包含鍺離子之實施中，經再結晶區域120可包含SiyGe1-y，其中y係自約0.01至約0.50，或在某些實施例中係自約0.10至約0.20。
在再結晶過程期間，半導體層106之非晶區域112之再結晶可由半導體層106之下伏結晶區域114接種。由於半導體層106之下伏結晶區域114可包含矽且經再結晶區域120可包含SiyGe1-y，因此SiyGe1-y之經再結晶區域120形成於下伏Si上面，且SiyGe1-y之晶格可受下伏Si約束，使得SiyGe1-y之經再結晶區域處於一壓縮應變狀態中(SiyGe1-y之晶格參數大於Si之晶格參數，此乃因Ge之原子半徑大於Si之原子半徑)。
參考圖5，在使半導體層106之非晶區域112再結晶以形成經再結晶區域120之後，可使用一化學蝕刻過程、一機械拋光過程或一化學機械(CMP)過程中之一或多者移除選用氧化物層108(若存在)。
如在圖6中所展示，在某些實施例中，可在半導體層之第二區域106B上選擇性地磊晶生長額外半導體材料124，而不在半導體層之第一區域106A上磊晶生長額外半導體材料。舉例而言，額外半導體材料124可包含矽或Si1-yGey。
在某些實施例中，額外半導體材料124之生長可在使非晶區域112再結晶以形成經再結晶區域120之後執行，如在諸圖之序列中所圖解說明。然而，在其他實施例中，額外半導體材料124之生長可在將離子植入至半導體層之第二區域106B中並形成非晶區域112(圖3)之前執行。如關於圖6所論述之額外半導體材料124之選擇性磊晶生長在於參考圖2闡述之離子植入過程之前執行時亦可達成一較高數量之離子之植入，此可允許在半導體層之第二區域106B中獲得較高濃度之經植入離子，以及如下文參考圖7所闡述之一較長熱擴散過程之執行，以及因此，半導體層之第二區域106B之一應變狀態之一較大程度變更。
選擇性地磊晶生長於半導體層之第二區域106B上方之額外半導體材料124之厚度可經選擇，使得繼在下文參考圖7所闡述之一擴散及富集過程之後，半導體層之第二區域106B之一厚度可至少實質上等於不經歷參考圖7闡述之擴散及富集過程之半導體層之第一區域106A之一厚度。
參考圖7，在使半導體層之第二區域106B之非晶區域112再結晶以形成經再結晶區域120之後，元素可自半導體層之第二區域106B之經再結晶區域120之一個部分擴散至半導體層之第二區域106B之另一部分，以便提高半導體層之第二區域106B之該另一部分中之經擴散元素之一濃度且變更半導體層之第二區域106B之一應變狀態。
舉例而言，一凝縮程序(通常被稱為一「熱混合」過程)或另一類型之過程可用以使元素在半導體層之第二區域106B內擴散，使得該等元素在半導體層106B之第二區域之一部分內濃縮並富集以便選擇性地減少拉伸應變，增加壓縮應變，且/或相對於半導體層之第一區域106A中之應變之位準而使半導體層之第二區域106B中之應變鬆弛。在此等實施例中，該等元素可不在半導體層之第一區域106A內以任何實質性方式擴散。換言之，可僅對半導體層之第二區域106B執行而不對半導體層之第一區域106A執行凝縮程序。在下文闡述此一凝縮程序。
圖7類似於圖3至圖6並圖解說明在對半導體層之第二區域106B執行一凝縮程序之後之多層基板100。凝縮程序可涉及使半導體層之第二區域106B在一爐中在高溫下(例如，大約介於約900℃與約1150℃之間)於一個氧化氣氛(例如，具有或不具有HCL之乾O2)中經歷一個氧化過程。氧化過程可導致在半導體層之第二區域106B之表面處形成一個氧化物層122，且可致使元素自半導體層之第二區域106B之一上部區域內擴散至半導體層之第二區域106B之一下部區域中。
在其中應變半導體層106包含應變矽(sSi)之實施例中，如參考圖2所闡述植入至半導體層之第二區域106B中之離子可包含鍺離子，且鍺原子可在凝縮程序期間進一步擴散至半導體層之第二區域106B中。一個氧化物層122可在半導體層之第二區域106B之表面處形成且在厚度上生長至半導體層之第二區域106B中。隨著氧化物層122之厚度在鍺凝縮程序期間生長，SiyGe1-y半導體層106之厚度減小，且半導體層106中之鍺之濃度增加，直至SiyGe1-y半導體層106在其中具有一所要濃度之鍺為止。半導體層之第二區域106B內之鍺之擴散及濃縮可造成應變半導體層106內之任何拉伸應變之減小，且可導致應變鬆弛及/或在應變半導體層106內產生壓縮應變。
因此，半導體層之第一區域106A可處於一第一應變狀態中，且半導體層之第二區域106B可處於不同於第一應變狀態之一第二應變狀態中。
可在後續處理之前自半導體層之第二區域106B上方移除在擴散及富集過程(例如，凝縮程序)中形成之氧化物層122。
如前文所述及，半導體層之第一區域106A可包含一拉伸應變矽層。半導體層之第一區域106A中之拉伸應變可提供半導體層之第一區域106A內之經改良電子移動性，此對於形成具有包含半導體層之第一區域106A之部分之通道區域之n型FET電晶體可係所要的。離子植入及再結晶過程以及在半導體層之第二區域106B中執行之凝縮程序可造成半導體層之第二區域106B內之經改良電洞移動性，此對於形成具有包含半導體層之第二區域106B之部分之通道區域之p型FET電晶體可係所要的。
如在圖8中所展示，可移除上覆於半導體層106上之氧化物層108及遮罩層110以形成一半導體結構130。藉由參考圖1至圖7所闡述之方法形成的圖8中展示之半導體結構130包括一基底基板102、在基底基 板102之一表面上方之一BOX層104，以及安置於BOX層104上方在BOX層104之與基底基板102相對之一側部上之一共同平面中的一半導體層之一第一區域106A及一半導體層之一第二區域106B。半導體結構130可隨後經處理以完成包括n型及p型電晶體之一半導體器件之製作。n型電晶體可形成於半導體層106之第一區域上及/或中，且p型電晶體可形成於半導體層106之第二區域上及/或中。
圖9(例如)圖解說明形成各自包含半導體層之第一區域106A之一部分之第一複數個鰭片結構132A，以及各自包含半導體層之第二區域106B之一部分之第二複數個鰭片結構132B。鰭片結構132A、132B中之每一者經定大小及組態以用作鰭式FET型電晶體中之一電晶體通道結構。作為一非限制性實例，鰭片結構132A、132B中之每一者可經形成為具有約15nm或更小之一平均寬度。
第二複數個鰭片結構132B之鰭片結構132B具有不同於第一複數個鰭片結構132A之鰭片結構132A之一晶向應變的一晶向應變。第一複數個鰭片結構132A之每一鰭片結構132A包括一未經凝縮應變半導體材料。第二複數個鰭片結構132B之每一鰭片結構132B包括包括兩個或兩個以上元素(例如，矽及鍺)之一經凝縮應變半導體材料。
在形成第一複數個鰭片結構132A及第二複數個鰭片結構132B之後，可形成包含第一複數個鰭片結構132A之第一複數個n型鰭式FET電晶體，且可形成包含第二複數個鰭片結構132B之第二複數個p型鰭式FET電晶體。
在額外實施例中，圖8之半導體結構130可隨後經處理以形成在半導體層之第一區域106A上及/或中之複數個習用平面n型金屬氧化物半導體場效應電晶體(NMOS FET)，以及在半導體層之第二區域106B上及/或中之複數個習用平面p型金屬氧化物半導體場效應電晶體(PMOS FET)，如在圖10中所圖解說明。舉例而言，可形成部分地或 完全地穿過半導體層106之一或多個淺溝槽隔離(STI)結構134，以便電隔離將形成於半導體層106中之電晶體通道區域。習用STI處理可用以界定半導體層106中之電晶體通道結構。在此類處理中，一遮罩及蝕刻過程可用以在毗鄰電晶體通道結構之間形成溝槽，且介電材料可提供於溝槽內以在電晶體通道結構之間形成STI結構134。因此，半導體層106中之STI結構134可用以電隔離將界定於半導體層106中之電晶體通道結構。儘管在圖10中圖解說明僅一個STI結構134，但複數個此類STI結構134可用以界定半導體層106中之電晶體通道結構。
在於半導體層106中形成STI結構134之後，可形成各自包含半導體層之第一區域106A之一部分之第一複數個電晶體通道結構，且可形成各自包含之一部分半導體層之第二區域106B之第二複數個電晶體通道結構。電晶體通道結構可經定大小及組態以用作MOS FET型電晶體中之電晶體通道結構。
形成於半導體層之第一區域106A中之NMOS FET電晶體通道結構具有不同於形成於半導體層之第二區域106B中之PMOS FET電晶體通道結構之一晶向應變的一晶向應變。在形成第一及第二複數個電晶體通道結構之後，可形成包含第一複數個電晶體通道結構之第一複數個NMOS FET電晶體，且可形成包含第二複數個電晶體通道結構之第二複數個PMOS FET電晶體。
在額外實施例中，在形成STI結構134之前，可形成包含第一複數個電晶體通道結構之第一複數個NMOS FET電晶體，且可形成包含第二複數個電晶體通道結構之第二複數個PMOS FET電晶體。圖11至圖16圖解說明可用以製作類似於上文參考圖1至圖9闡述之共平面n型及p型鰭式FET電晶體的共平面n型及p型鰭式FET電晶體之一方法之一額外實施例。
圖11圖解說明一多層基板140，多層基板140包括一基底基板 102、一埋置氧化物層104以及一應變半導體層106，如在本文中先前參考圖1所闡述。
如在圖12中所展示，可使用(例如)一遮罩及蝕刻過程圖案化應變半導體層106以形成各自包含應變半導體層106之一區域之鰭片結構142。鰭片結構142可使用此項技術中已知之鰭式FET製作過程而形成，且可包括間隔物定義之雙圖案化(SDDP)過程(在此項技術中亦已知為「側壁影像轉移」過程)。鰭片結構142可包括第二複數個鰭片結構142B及第一複數個鰭片結構142A。
參考圖13，一或多個遮罩層可沈積於鰭片結構142上方。遮罩層可包括(例如)一鈍化氧化物層144、一個氮化物層146，以及一遮罩層148。遮罩層148可包含(例如)一光阻遮罩材料，其可經圖案化以在第二複數個鰭片結構142B上方形成穿過遮罩層148之孔隙。可使用一或多個蝕刻過程移除氧化物層144及氮化物層146中之一者或兩者，在該等蝕刻過程中使氧化物層144及氮化物層146透過遮罩層148中之孔隙曝露於一蝕刻劑，而遮罩層148遮蔽該結構之其餘部分以免遭蝕刻劑。如在圖13中所展示，在某些實施例中，可使用一蝕刻過程移除上覆於第二複數個鰭片結構142B上的氮化物層146之區域，而可使氧化物層144之至少一部分保留於第二複數個鰭片結構142B上方之適當位置中。然而，在其他實施例中，可至少實質上完全地移除上覆於第二複數個鰭片結構142B上的氧化物層144之部分。可視情況在後續處理之前移除遮罩層148，或可如在圖13中所展示將遮罩層148保留於適當位置中。
如在圖13中所展示，可用先前參考圖2闡述之一過程將離子透過遮罩層148及氮化物層146中之一者或兩者中之孔隙而植入至第二複數個鰭片結構142B中，以便在第二複數個鰭片結構142B之部分中形成非晶區域150，如在圖14中所展示。第二複數個鰭片結構142B可包括 保留於非晶區域150下方的應變半導體層106之結晶區域114，實質上如先前參考圖3所闡述。
參考圖15，在形成非晶區域150之後，可使非晶區域150再結晶以形成經再結晶區域154。再結晶過程可如先前參考圖4所闡述地執行。
參考圖16，可在形成經再結晶區域154(圖15)之後以如先前參考圖7所闡述之一方式對第二複數個鰭片結構142B執行一擴散及富集過程(例如，一凝縮程序)。擴散及富集過程可導致在第二複數個鰭片結構142B中之每一者上方形成一個氧化物層156。
視情況地，亦可在執行擴散及富集過程之前對第二複數個鰭片結構142B執行額外半導體材料之磊晶生長，如先前參考圖5及圖6所闡述。
因此，第二複數個鰭片結構142B可包含經定大小及組態以用於形成p型鰭式FET電晶體之電晶體通道結構，且第一複數個鰭片結構142A可包含經定大小及組態以用於形成n型鰭式FET電晶體之電晶體通道結構。
在如先前參考圖11至圖16所闡述地形成第一複數個鰭片結構142A及第二複數個鰭片結構142B之後，可形成包含第一複數個鰭片結構142A之第一複數個NMOS鰭式FET電晶體，且可形成包含第二複數個鰭片結構142B之第二複數個PMOS鰭式FET電晶體。
圖17圖解說明根據本發明之實施例(圖9之鰭片結構)之可使用第二複數個鰭片結構142B及/或第一複數個鰭片結構142A製作之一鰭式FET電晶體組態之一非限制性簡化實例實施例。應注意，鰭式FET之諸多不同組態在此項技術中係已知的且可根據本發明之實施例而採用，且在圖17中展示之鰭式FET結構僅作為此類鰭式FET結構之一實例而被陳述。
如在圖17中所展示，一鰭式FET電晶體160包含一源極區域162、一汲極區域164，以及在源極區域162與汲極區域164之間延伸之一通道。通道由一鰭片(諸如，一第一鰭片結構142A或一第二鰭片結構142B)界定且包含該鰭片。在某些實施例中，源極區域162及汲極區域164可包括一鰭片結構142之縱向端部分，或由該縱向端部分界定。一導電閘極166在源極區域162與汲極區域164之間的鰭片結構142之至少一部分上方且與其毗鄰地延伸。閘極166可藉由一介電材料168而與鰭片結構142分離。閘極166可包括一個多層結構，且可包括半導電及/或導電層。包括一金屬、一金屬化合物或此兩者(諸如，一導電矽化物)之一低電阻層可沈積於源極區域162及/或汲極區域164上方以與其一起形成電觸點。
有利地，通道中之拉張應力/應變可增加NMOS鰭式FET電晶體之效能並減小臨限電壓，同時通道中之經減小拉伸應變/應變(例如，較小拉張應力、無拉張或壓縮應力，或壓縮應力)可增加PMOS鰭式FET電晶體之效能並減小臨限電壓。對於某些功能，應變器件係有益的，此乃因需要高性能，且對於某些其他功能，效能不如此重要，但一高臨限電壓係有益的。藉助於本發明之實施例，製造者可選擇性地將不同位準之應力及應變併入至一共同FET電晶體平面中的同一器件中之不同鰭式FET或MOSFET電晶體之晶格中。
下文陳述本發明之額外非限制實例性實施例。
實施例1：一種製作一半導體結構之方法，其包含：提供一多層基板，該多層基板包括：一基底基板，一埋置氧化物層，其在該基底基板之一表面上方，及一應變半導體層，其在該埋置氧化物層上方在該埋置氧化物層之與該基底基板相對之一側部上，該應變半導體層包含結晶半導體材料；將離子植入至該應變半導體層之一第二區域中而不將離子植入至該應變半導體層之一第一區域中，且將該應變半導體 層之該第二區域中之該結晶半導體材料之一部分轉變為非晶材料，使得該應變半導體層之該第二區域具有一非晶區域及一下伏結晶區域；使該非晶區域再結晶；將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之另一部分中，以便提高該應變半導體層之該第二區域之該另一部分中之該等經擴散元素之一濃度並變更該應變半導體層之該第二區域之一應變狀態，使得該應變半導體層之該第二區域處於不同於該應變半導體層之該第一區域之一應變狀態的一應變狀態中；及形成各自包含該半導體層之該第一區域之一部分之第一複數個電晶體通道結構以及各自包含該半導體層之該第二區域之一部分之第二複數個電晶體通道結構。
實施例2：如實施例1之方法，其進一步包含選擇該應變半導體層以包含應變矽。
實施例3：如實施例2之方法，其進一步包含選擇該應變半導體層以包含拉伸應變矽。
實施例4：如實施例2或實施例3之方法，其中將離子植入至該應變半導體層之該第二區域中包含將鍺離子植入至該應變半導體層之該第二區域中以形成SiyGe1-y，其中y係自約0.10至約0.50，且其中將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之另一部分中包含將鍺擴散至該應變半導體層之該第二區域之該另一部分中。
實施例5：如實施例1至4中任一項之方法，其中形成該第一複數個電晶體通道結構及該第二複數個電晶體通道結構包含形成各自包含該半導體層之該第一區域之一部分之第一複數個鰭片結構以及各自包含該半導體層之該第二區域之一部分之第二複數個鰭片結構。
實施例6：如實施例5之方法，其進一步包含形成包含第一複數個鰭片結構之複數個n型鰭式FET電晶體並形成包含第二複數個鰭片 結構之複數個p型鰭式FET電晶體。
實施例7：如實施例1至6中任一項之方法，其進一步包含形成該第一複數個電晶體通道結構及該第二複數個電晶體通道結構之該等電晶體通道結構以具有約15nm或更小之一平均寬度。
實施例8：如實施例1至7中任一項之方法，其中將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之另一部分中包含使該應變半導體層之該第二區域中之應變鬆弛。
實施例9：如實施例8之方法，其中使該應變半導體層之該第二區域中之應變鬆弛包含增加該應變半導體層之該第二區域內之一電洞移動性。
實施例10：如實施例1至9中任一項之方法，其中將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之另一部分中包含對該應變半導體層之該第二區域執行一凝縮程序。
實施例11：如實施例10之方法，其中對該應變半導體層之該第二區域執行一凝縮程序包含使該應變半導體層之該第二區域之一部分氧化。
實施例12：如實施例1至11中任一項之方法，其中使該非晶區域再結晶包含用該下伏結晶區域接種該非晶區域之再結晶。
實施例13：如實施例1至12中任一項之方法，其進一步包含在將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之該另一部分中之前，在該半導體層之該第二區域上磊晶生長額外半導體材料而不在該半導體層之該第一區域上生長額外半導體材料。
實施例14：一種半導體結構，其包含：一基底基板，一埋置氧化物層，其在該基底基板之一表面上方，第一複數個電晶體通道結構及第二複數個電晶體通道結構，其等安置於該埋置氧化物層上方在該 埋置氧化物層之與該基底基板相對之一側部上之一共同平面中，該第二複數個電晶體通道結構之每一電晶體通道結構包含包括兩個或兩個以上元素之一經凝縮應變半導體層，該第一複數個電晶體通道結構之每一電晶體通道結構包含一未經凝縮應變半導體層；其中該第二複數個電晶體通道結構之該等電晶體通道結構具有不同於該第一複數個電晶體通道結構之該等電晶體通道結構之一晶向應變的一晶向應變。
實施例15：如實施例14之半導體結構，其中該第一複數個電晶體通道結構之每一電晶體通道結構之該未經凝縮應變半導體層包含應變矽。
實施例16：如實施例14或實施例15之半導體結構，其中該第二複數個電晶體通道結構之每一電晶體通道結構之該經凝縮應變半導體層包含SixGe1-x，其中x係自約0.01至約0.50。
實施例17：如實施例14至16中任一項之半導體結構，其中該第一複數個電晶體通道結構之該等電晶體通道結構處於一拉伸應變狀態中，且該第一複數個電晶體通道結構之該等電晶體通道結構係鬆弛的或處於一壓縮應變狀態中。
實施例18：如實施例14至17中任一項之半導體結構，其中該第一複數個電晶體通道結構及該第二複數個電晶體通道結構之該等電晶體通道結構具有約15nm或更小之一平均寬度。
實施例19：如實施例14至18中任一項之半導體結構，其中該第一複數個電晶體通道結構及該第二複數個電晶體通道結構中之每一者之該等電晶體通道結構包含鰭片結構。
實施例20：如實施例19之半導體結構，其進一步包含包括該第一複數個電晶體通道結構之第一複數個n型鰭式FET電晶體，以及包括該第二複數個電晶體通道結構之第二複數個p型鰭式FET電晶體。
本發明之上述實例性實施例並不限制本發明之範疇，此乃因該 等實施例僅係本發明之實施例之實例，本發明之範疇係由隨附申請專利範圍之範疇及其合法等效物界定。任何等效實施例皆意欲屬本發明之範疇內。實際上，除本文中者展示及闡述之彼等(諸如，所述要素之替代性有用組合)外，熟習此項技術者自本說明將明瞭本發明之各種修改。換言之，本文中所闡述之一個實例性實施例之一或多個特徵可與本文中所闡述之另一實例性實施例之一或多個特徵進行組合以提供本發明之額外實施例。此等修改及實施例亦意欲落於隨附申請專利範圍之範疇內。
102‧‧‧基底基板
104‧‧‧埋置氧化物層
106‧‧‧應變半導體層
106A‧‧‧半導體層之第一區域/應變半導體層之第一區域
106B‧‧‧半導體層之第二區域/應變半導體層之第二區域
132A‧‧‧鰭片結構
132B‧‧‧鰭片結構

Claims (15)

  1. 一種製作一半導體結構之方法，其包含：提供一多層基板，該多層基板包括：一基底基板，一埋置氧化物層，其在該基底基板之一表面上方，及一應變半導體層，其在該埋置氧化物層上方在該埋置氧化物層之與該基底基板相對之一側部上，該應變半導體層包含結晶半導體材料；將離子植入至該應變半導體層之一第二區域中而不將離子植入至該應變半導體層之一第一區域中，且將該應變半導體層之該第二區域中之該結晶半導體材料之一部分轉變為非晶材料，使得該應變半導體層之該第二區域具有一非晶區域及一下伏結晶區域；使該非晶區域再結晶；將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之另一部分中，以便提高該應變半導體層之該第二區域之該另一部分中之該等經擴散元素之一濃度並變更該應變半導體層之該第二區域之一應變狀態，使得該應變半導體層之該第二區域處於不同於該應變半導體層之該第一區域之一應變狀態的一應變狀態中；及形成各自包含該半導體層之該第一區域之一部分之第一複數個電晶體通道結構以及各自包含該半導體層之該第二區域之一部分之第二複數個電晶體通道結構。
  2. 如請求項1之方法，其進一步包含選擇該應變半導體層以包含應變矽。
  3. 如請求項2之方法，其進一步包含選擇該應變半導體層以包含拉伸應變矽。
  4. 如請求項2之方法，其中將離子植入至該應變半導體層之該第二區域中包含將鍺離子植入至該應變半導體層之該第二區域中以形成SiyGe1-y，其中y係自約0.10至約0.50，且其中將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之另一部分中包含將鍺擴散至該應變半導體層之該第二區域之該另一部分中。
  5. 如請求項1之方法，其中形成該第一複數個電晶體通道結構及該第二複數個電晶體通道結構包含形成各自包含該半導體層之該第一區域之一部分之第一複數個鰭片結構以及各自包含該半導體層之該第二區域之一部分之第二複數個鰭片結構。
  6. 如請求項1之方法，其中將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之另一部分中包含使該應變半導體層之該第二區域中之應變鬆弛。
  7. 如請求項1之方法，其中將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之另一部分中包含對該應變半導體層之該第二區域執行一凝縮程序。
  8. 如請求項7之方法，其中對該應變半導體層之該第二區域執行一凝縮程序包含使該應變半導體層之該第二區域之一部分氧化。
  9. 如請求項1之方法，其中使該非晶區域再結晶包含用該下伏結晶區域接種該非晶區域之再結晶。
  10. 如請求項1之方法，其進一步包含在將來自該應變半導體層之該第二區域之一個部分之元素擴散至該應變半導體層之該另一部分中之前，在該半導體層之該第二區域上磊晶生長額外半導體材料而不在該半導體層之該第一區域上生長額外半導體材料。
  11. 一種半導體結構，其包括：一基底基板，一埋置氧化物層，其在該基底基板之一表面上方，第一複數個電晶體通道結構及第二複數個電晶體通道結構，其等安置於該埋置氧化物層上方在該埋置氧化物層之與該基底基板相對之一側部上之一共同平面中，該第二複數個電晶體通道結構之每一電晶體通道結構包含包括兩個或兩個以上元素之一經凝縮應變半導體層，該第一複數個電晶體通道結構之每一電晶體通道結構包含一未經凝縮應變半導體層；其中該第二複數個電晶體通道結構之該等電晶體通道結構具有不同於該第一複數個電晶體通道結構之該等電晶體通道結構之一晶向應變的一晶向應變。
  12. 如請求項11之半導體結構，其中該第一複數個電晶體通道結構之每一電晶體通道結構之該未經凝縮應變半導體層包含應變矽。
  13. 如請求項11之半導體結構，其中該第二複數個電晶體通道結構之每一電晶體通道結構之該經凝縮應變半導體層包含SixGe1-x，其中x係自約0.01至約0.50。
  14. 如請求項11之半導體結構，其中該第一複數個電晶體通道結構之該等電晶體通道結構處於一拉伸應變狀態中，且該第一複數個電晶體通道結構之該等電晶體通道結構係鬆弛的或處於一壓縮應變狀態中。
  15. 如請求項11之半導體結構，其中該第一複數個電晶體通道結構及該第二複數個電晶體通道結構中之每一者之該等電晶體通道結構包含鰭片結構。
TW104129408A 2014-09-18 2015-09-04 用於製作包括具有不同應變狀態之電晶體通道之半導體結構之方法及相關半導體結構 TW201618193A (zh)

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