CN102820253B - 一种基于soi衬底的高迁移率双沟道材料的制备方法 - Google Patents

一种基于soi衬底的高迁移率双沟道材料的制备方法 Download PDF

Info

Publication number
CN102820253B
CN102820253B CN201110151806.7A CN201110151806A CN102820253B CN 102820253 B CN102820253 B CN 102820253B CN 201110151806 A CN201110151806 A CN 201110151806A CN 102820253 B CN102820253 B CN 102820253B
Authority
CN
China
Prior art keywords
layer
soi substrate
preparation
high mobility
channel material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201110151806.7A
Other languages
English (en)
Other versions
CN102820253A (zh
Inventor
张苗
张波
薛忠营
王曦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Institute of Microsystem and Information Technology of CAS
Shanghai Simgui Technology Co Ltd
Original Assignee
Shanghai Institute of Microsystem and Information Technology of CAS
Shanghai Simgui Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Institute of Microsystem and Information Technology of CAS, Shanghai Simgui Technology Co Ltd filed Critical Shanghai Institute of Microsystem and Information Technology of CAS
Priority to CN201110151806.7A priority Critical patent/CN102820253B/zh
Priority to PCT/CN2011/077580 priority patent/WO2012167487A1/zh
Priority to US13/262,656 priority patent/US8580659B2/en
Publication of CN102820253A publication Critical patent/CN102820253A/zh
Application granted granted Critical
Publication of CN102820253B publication Critical patent/CN102820253B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种基于SOI衬底的高迁移率双沟道材料的制备方法，基于传统的SOI（silicon-on-insulator）衬底，外延压应变的SiGe材料，用作PMOSFET的沟道材料；在SiGe材料上继续外延Si，采用离子注入、退火等手段，使部分应变的SiGe弛豫，同时将应变传递到上方Si层中，从而形成应变Si材料，用做NMOSFET的沟道材料。本方法其工艺步骤简单，易于实现，能够同时为NMOSFET及PMOSFET提供高迁移率的沟道材料，满足了同时提高NMOSFET和PMOSFET器件性能的要求，为下一代的CMOS工艺提供潜在的沟道材料。

Description

一种基于SOI衬底的高迁移率双沟道材料的制备方法
技术领域
本发明涉及一种用于CMOS器件的双沟道材料的制备方法，尤其涉及一种基于SOI衬底的高迁移率双沟道材料的制备方法，属于微电子与固体电子学技术领域。
背景技术
随着集成电路工艺的发展，器件的特征尺寸不断缩小，体硅材料较低的电子和空穴迁移率已经成为提高器件性能的瓶颈。应变硅(strained silicon)，通过在晶格常数不同于硅的材料上外延硅，或者其他工艺方法引起硅晶格结构的拉伸或者压缩形变而形成。由于其可以有效提高载流子迁移率，已经成为面向新一代半导体工艺节点的候选衬底材料。SiGe衬底具有与Si不相同的晶格常数，在SiGe衬底上外延生长的Si与SiGe衬底之间会存在晶格失配，这种晶格失配使得外延的Si层会有应变。应变硅材料由于其晶格结构的畸变，能够同时提高电子和空穴的迁移率，而绝缘体上应变硅(sSOI，strained silicon on insulator)同时具有绝缘体上硅(SOI，silicon on insulator)和应变硅的优点，在集成电路工艺中具有更广阔的应用前景。
绝缘体上应变硅材料也可以是应变Si与(应变)SiGe的组合，即以应变Si/(应变)SiGe形成双沟道层结构(应变Si为表层、SiGe为埋层)。在双沟道独特的能带结构中，电子被限制在应变Si层中，可以获得高的电子迁移率，空穴被限制在(应变)SiGe层中，可以获得高的空穴迁移率。
鉴于此，本发明将提出一种基于SOI衬底的应变Si/SiGe双沟道材料的制备工艺，采用该工艺可同时为NMOS及PMOS提供高迁移率的沟道材料。
发明内容
本发明要解决的技术问题在于提供一种基于SOI衬底的高迁移率双沟道材料的制备方法。
为了解决上述技术问题，本发明采用如下技术方案：
一种基于SOI衬底的高迁移率双沟道材料的制备方法，包括以下步骤：
步骤一、在SOI衬底上外延生长SiGe层，其中SOI衬底由下至上依次由硅衬底、绝缘埋层和顶层硅组成；
步骤二、在所述SiGe层上继续外延生长Si盖帽层；
步骤三、在所述Si盖帽层上形成光刻胶，利用光刻刻蚀工艺将部分Si盖帽层露出；
步骤四、在露出的Si盖帽层上继续外延生长Si层；
步骤五、进行离子注入，使注入的离子分布在SOI衬底的顶层硅中；
步骤六、进行退火工艺，使部分SiGe层中的应力产生弛豫，从而将应力转移到其上方外延的Si材料中形成应变硅；形成的应变硅用于形成NMOSFET沟道，在光刻胶覆盖区域下方的SiGe层用于形成PMOSFET沟道。
作为本发明的优选方案，步骤一所采用的SOI衬底的顶层硅厚度为5-100nm，绝缘埋层厚度为10-500nm。
作为本发明的优选方案，步骤一在SOI衬底上外延生长SiGe层之前，还需要对该SOI衬底进行RCA清洗。
作为本发明的优选方案，步骤一外延生长的SiGe层中，Ge含量为10％-50％。
作为本发明的优选方案，步骤一外延生长的SiGe层的厚度为5-200nm。
作为本发明的优选方案，步骤二外延生长的Si盖帽层的厚度为2-5nm。
作为本发明的优选方案，步骤四外延生长的Si层的厚度为5-20nm。
作为本发明的优选方案，步骤五注入的离子为H、He、N、Si、C中的一种或多种。
作为本发明的优选方案，步骤五离子注入的剂量为1E13-1E18/cm2。
作为本发明的优选方案，步骤五退火的温度为300-1000℃，时间为1分钟至2小时。
本发明的有益效果在于：
本发明采用了传统的SOI衬底，利用外延、离子注入、退火等手段在SOI衬底上形成了应变Si/SiGe双沟道材料，其工艺步骤简单，易于实现，能够同时为NMOSFET及PMOSFET提供高迁移率的沟道材料，满足了同时提高NMOSFET和PMOSFET器件性能的要求，为下一代的CMOS工艺提供潜在的沟道材料。
附图说明
图1-8为本发明方法的工艺流程示意图。
具体实施方式
下面结合附图进一步说明本发明的具体实施步骤，为了示出的方便附图并未按照比例绘制。
实施例一
请参见图1-8，本实施例提供的制备方法，包括以下步骤：
步骤一、提供一片传统的SOI衬底，如图1所示，SOI衬底由下至上依次由硅衬底10、绝缘埋层20和顶层硅30组成，其中，顶层硅30厚度为5-100nm，绝缘埋层20厚度为10-500nm；然后对该SOI衬底进行标准的RCA(Radio Corporation of America)清洗，去除表面的污染物；再在该SOI衬底上外延生长SiGe层40，如图2所示，SiGe层40的Ge含量可以优选为10％-50％，厚度优选为5-200nm。为了保证生长的SiGe层40具有压应力，SiGe材料的厚度应控制在临界厚度以内，本实施例中，外延生长的SiGe层40的Ge含量为20％，其厚度控制在100nm左右。
步骤二、如图3所示，在所述SiGe层40上继续外延生长Si材料，作为Si盖帽层50。Si盖帽层50的厚度为2-5nm，在后续制作MOS器件时用于和高介电常数(H-K)栅介质接触，从而避免界面缺陷态的形成。
步骤三、根据CMOS工艺的要求，在所述Si盖帽层50上形成光刻胶60，如图4所示；然后利用光刻刻蚀工艺形成相应的图形，露出一部分的Si盖帽层50，如图5所示。由此可将设计为PMOSFET的部分用光刻胶进行保护，而设计为NMOSFET的部分露出以便后续工艺在该区域形成应变硅。
步骤四、如图6所示，在露出的Si盖帽层50上继续外延生长Si层70。外延生长的Si层70，厚度优选为5-20nm，以便于后续SiGe应力释放后，完全将应力转移到Si中，从而形成应变硅。本实施例中，外延生长的Si层70，厚度为10nm。
步骤五、如图7所示，进行离子注入，使注入的离子分布在SOI衬底的顶层硅30中。注入的离子优选为H、He、N、Si、C中的一种或多种，注入的剂量优选为1E13-1E18/cm2，而注入的能量根据不同的离子种类、和SiGe及其上方的Si的厚度进行确定，从而使离子注入的射程分布在SOI衬底的顶层硅30中。本实施例中，采用H离子注入，注入剂量为1E15/cm2。
步骤六、进行退火工艺，退火的温度优选为300-1000℃，时间为1分钟至2小时。由于离子注入引起的损伤，使得部分SiGe层40中的应力产生弛豫，从而将应力转移到其上方外延的Si材料中形成应变硅80。本实施例中，退火温度为600℃，时间为50分钟。如图8所示，形成的应变硅80用于形成NMOSFET沟道，在光刻胶60覆盖区域下方的SiGe层40用于形成PMOSFET沟道。
去除光刻胶后，利用该双沟道材料，可以在应变的SiGe材料上设计PMOSFET，在应变的Si材料上设计NMOSFET，从而可以实现CMOS工艺的集成。
实施例二
采用与实施例一相类似的工艺步骤，不同之处在于：
步骤一中外延生长的SiGe层Ge含量为10％，其厚度控制在200nm；步骤四中外延生长的Si层，厚度为5nm；步骤五中采用He离子注入，注入剂量为1E13/cm2；步骤六中的退火温度为1000℃，时间为1分钟。
实施例三
采用与实施例一相类似的工艺步骤，不同之处在于：
步骤一中外延生长的SiGe层Ge含量为30％，其厚度控制在80nm；步骤四中外延生长的Si层，厚度为10nm；步骤五中采用N离子注入，注入剂量为1E15/cm2；步骤六中的退火温度为800℃，时间为5分钟。
实施例四
采用与实施例一相类似的工艺步骤，不同之处在于：
步骤一中外延生长的SiGe层Ge含量为40％，其厚度控制在50nm；步骤四中外延生长的Si层，厚度为15nm；步骤五中采用Si离子注入，注入剂量为1E16/cm2；步骤六中的退火温度为400℃，时间为90分钟。
实施例五
采用与实施例一相类似的工艺步骤，不同之处在于：
步骤一中外延生长的SiGe层Ge含量为50％，其厚度控制在5nm；步骤四中外延生长的Si层，厚度为20nm；步骤五中采用C离子注入，注入剂量为1E18/cm2；步骤六中的退火温度为300℃，时间为120分钟。
上述实施例仅列示性说明本发明的原理及功效，而非用于限制本发明。任何熟悉此项技术的人员均可在不违背本发明的精神及范围下，对上述实施例进行修改。因此，本发明的权利保护范围，应如权利要求书所列。

Claims (9)

1.一种基于SOI衬底的高迁移率双沟道材料的制备方法，其特征在于，包括以下步骤：
步骤一、在SOI衬底上外延生长SiGe层，其中SOI衬底由下至上依次由硅衬底、绝缘埋层和顶层硅组成；
步骤二、在所述SiGe层上继续外延生长Si盖帽层；
步骤三、在所述Si盖帽层上形成光刻胶，利用光刻刻蚀工艺将部分Si盖帽层露出；
步骤四、在露出的Si盖帽层上继续外延生长Si层；
步骤五、进行离子注入，使注入的离子分布在SOI衬底的顶层硅中；
步骤六、进行退火工艺，使部分SiGe层中的应力产生弛豫，从而将应力转移到其上方外延的Si材料中形成应变硅；形成的应变硅用于形成NMOSFET沟道，在光刻胶覆盖区域下方的SiGe层用于形成PMOSFET沟道。
2.根据权利要求1所述的基于SOI衬底的高迁移率双沟道材料的制备方法，其特征在于：步骤一所采用的SOI衬底的顶层硅厚度为5-100nm，绝缘埋层厚度为10-500nm。
3.根据权利要求1所述的基于SOI衬底的高迁移率双沟道材料的制备方法，其特征在于：步骤一在SOI衬底上外延生长SiGe层之前，还需要对该SOI衬底进行RCA清洗。
4.根据权利要求1所述的基于SOI衬底的高迁移率双沟道材料的制备方法，其特征在于：步骤一外延生长的SiGe层的厚度为5-200nm。
5.根据权利要求1所述的基于SOI衬底的高迁移率双沟道材料的制备方法，其特征在于：步骤二外延生长的Si盖帽层的厚度为2-5nm。
6.根据权利要求1所述的基于SOI衬底的高迁移率双沟道材料的制备方法，其特征在于：步骤四外延生长的Si层的厚度为5-20nm。
7.根据权利要求1所述的基于SOI衬底的高迁移率双沟道材料的制备方法，其特征在于：步骤五注入的离子为H、He、N、Si、C中的一种或多种。
8.根据权利要求1所述的基于SOI衬底的高迁移率双沟道材料的制备方法，其特征在于：步骤五离子注入的剂量为1E13-1E18/cm2。
9.根据权利要求1所述的基于SOI衬底的高迁移率双沟道材料的制备方法，其特征在于：步骤五退火的温度为300-1000℃，时间为1分钟至2小时。
CN201110151806.7A 2011-06-08 2011-06-08 一种基于soi衬底的高迁移率双沟道材料的制备方法 Expired - Fee Related CN102820253B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201110151806.7A CN102820253B (zh) 2011-06-08 2011-06-08 一种基于soi衬底的高迁移率双沟道材料的制备方法
PCT/CN2011/077580 WO2012167487A1 (zh) 2011-06-08 2011-07-25 一种基于soi衬底的高迁移率双沟道材料的制备方法
US13/262,656 US8580659B2 (en) 2011-06-08 2011-07-25 Method of fabricating high-mobility dual channel material based on SOI substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110151806.7A CN102820253B (zh) 2011-06-08 2011-06-08 一种基于soi衬底的高迁移率双沟道材料的制备方法

Publications (2)

Publication Number Publication Date
CN102820253A CN102820253A (zh) 2012-12-12
CN102820253B true CN102820253B (zh) 2014-04-16

Family

ID=47295373

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110151806.7A Expired - Fee Related CN102820253B (zh) 2011-06-08 2011-06-08 一种基于soi衬底的高迁移率双沟道材料的制备方法

Country Status (3)

Country Link
US (1) US8580659B2 (zh)
CN (1) CN102820253B (zh)
WO (1) WO2012167487A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8927363B2 (en) 2013-05-17 2015-01-06 International Business Machines Corporation Integrating channel SiGe into pFET structures
FR3006806A1 (fr) * 2013-06-07 2014-12-12 St Microelectronics Sa Procede de formation de composants sur une couche de silicium-germanium
US9349863B2 (en) 2013-08-07 2016-05-24 Globalfoundries Inc. Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet
US9018057B1 (en) 2013-10-08 2015-04-28 Stmicroelectronics, Inc. Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer
US9887939B2 (en) 2015-03-11 2018-02-06 International Business Machines Corporation Transmitting multi-destination packets in overlay networks
KR102188538B1 (ko) 2014-04-21 2020-12-09 삼성전자주식회사 반도체 메모리 장치 및 이의 제조 방법
US9165945B1 (en) * 2014-09-18 2015-10-20 Soitec Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures
US9293373B1 (en) 2015-05-26 2016-03-22 International Business Machines Corporation Method for fabricating CMOS finFETs with dual channel material
US9972683B2 (en) 2015-10-27 2018-05-15 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
JP6775935B2 (ja) 2015-11-04 2020-10-28 株式会社東芝 文書処理装置、方法、およびプログラム
JP6490607B2 (ja) * 2016-02-09 2019-03-27 株式会社東芝 材料推薦装置
JP6602243B2 (ja) 2016-03-16 2019-11-06 株式会社東芝 学習装置、方法、及びプログラム
US9773893B1 (en) 2016-09-26 2017-09-26 International Business Machines Corporation Forming a sacrificial liner for dual channel devices
JP6622172B2 (ja) 2016-11-17 2019-12-18 株式会社東芝 情報抽出支援装置、情報抽出支援方法およびプログラム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1503327A (zh) * 2002-11-20 2004-06-09 国际商业机器公司 弛豫、低缺陷绝缘体上SiGe及其制造方法
CN101740463A (zh) * 2009-12-08 2010-06-16 中国科学院上海微系统与信息技术研究所 一种通过氧离子注入退火制备绝缘体上应变硅材料的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6515335B1 (en) * 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
TWI263709B (en) * 2004-02-17 2006-10-11 Ind Tech Res Inst Structure of strain relaxed thin Si/Ge epitaxial layer and fabricating method thereof
US20050221591A1 (en) * 2004-04-06 2005-10-06 International Business Machines Corporation Method of forming high-quality relaxed SiGe alloy layers on bulk Si substrates
JP2006108365A (ja) * 2004-10-05 2006-04-20 Renesas Technology Corp 半導体装置およびその製造方法
KR101455564B1 (ko) * 2005-12-09 2014-10-27 세미이큅, 인코포레이티드 탄소 클러스터의 주입에 의한 반도체 디바이스의 제조를 위한 시스템 및 방법
WO2008039534A2 (en) * 2006-09-27 2008-04-03 Amberwave Systems Corporation Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1503327A (zh) * 2002-11-20 2004-06-09 国际商业机器公司 弛豫、低缺陷绝缘体上SiGe及其制造方法
CN101740463A (zh) * 2009-12-08 2010-06-16 中国科学院上海微系统与信息技术研究所 一种通过氧离子注入退火制备绝缘体上应变硅材料的方法

Also Published As

Publication number Publication date
CN102820253A (zh) 2012-12-12
WO2012167487A1 (zh) 2012-12-13
US8580659B2 (en) 2013-11-12
US20130029478A1 (en) 2013-01-31

Similar Documents

Publication Publication Date Title
CN102820253B (zh) 一种基于soi衬底的高迁移率双沟道材料的制备方法
US10056300B2 (en) Methods of forming NMOS and PMOS finFET devices and the resulting product
US8853040B2 (en) Strained thin body CMOS device having vertically raised source/drain stressors with single spacer
US6583000B1 (en) Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation
JP3512701B2 (ja) 半導体装置及びその製造方法
US8124470B1 (en) Strained thin body semiconductor-on-insulator substrate and device
US11699757B2 (en) High dose implantation for ultrathin semiconductor-on-insulator substrates
US9076867B2 (en) Semiconductor device structures including strained transistor channels
US7018882B2 (en) Method to form local “silicon-on-nothing” or “silicon-on-insulator” wafers with tensile-strained silicon
JP2002043576A (ja) 半導体装置
WO2000060671A1 (fr) Dispositif a semi-conducteur et substrat de semi-conducteur
JPH09219524A (ja) 半導体装置及びその製造方法
JP2002368230A (ja) 絶縁体上シリコン基板上に歪Ｓｉ／ＳｉＧｅ層を用いた良好な移動度を有するＮＭＯＳおよびＰＭＯＳトランジスタ
TW200539425A (en) Integrated circuit with strained and non-strained transistors, and method of forming thereof
US20130285117A1 (en) CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION
US8062952B2 (en) Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors
US9263582B2 (en) Strain engineering in semiconductor devices by using a piezoelectric material
JPH1092947A (ja) 半導体装置及びその製造方法
CN103762242B (zh) 压应变GeSn p沟道金属氧化物半导体场效应晶体管
US8659083B2 (en) Enhancement of charge carrier mobility in transistors
CN102820252B (zh) 一种基于键合工艺的高迁移率双沟道材料的制备方法
Maiti Strained-Si heterostructure field effect devices: Strain-engineering in CMOS technology
JP2010141349A (ja) 半導体装置の製造方法
Yeo Towards ultimate CMOS performance with new stressor materials
Patton Discontinuous Innovation: Strained Silicon Technology

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140416

Termination date: 20150608

EXPY Termination of patent right or utility model