JP2008131039A - 電子素子内蔵型印刷回路基板の製造方法 - Google Patents

電子素子内蔵型印刷回路基板の製造方法 Download PDF

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JP2008131039A
JP2008131039A JP2007283566A JP2007283566A JP2008131039A JP 2008131039 A JP2008131039 A JP 2008131039A JP 2007283566 A JP2007283566 A JP 2007283566A JP 2007283566 A JP2007283566 A JP 2007283566A JP 2008131039 A JP2008131039 A JP 2008131039A
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electronic element
circuit board
printed circuit
tape
hole
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Seung-Gu Kim
キム スン−グ
Je-Gwang Yoo
ヨー ジェ−グワン
Doo-Hwan Lee
リー ドゥ−ファン
Moon-Il Kim
キム ムーン−イル
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Samsung Electro Mechanics Co Ltd
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Abstract

【課題】異種材料を最小限に使用して電子素子を内蔵することにより、印刷回路基板の反りを防止できる電子素子内蔵型印刷回路基板の製造方法を提供する。
【解決手段】本発明のよる電子素子内蔵型印刷回路基板の製造方法は、（ａ）表面に回路パターンが形成されたコア基板に貫通ホールを穿孔する段階と、（ｂ）コア基板の一側にテープを付着し、電子素子を、貫通ホールのテープが露出された部分に付着する段階と、（ｃ）貫通ホールと電子素子との間の空隙の一部に接着剤を充填して電子素子を固定する段階と、（ｄ）テープを除去する段階と、及び（ｅ）コア基板の両側に絶縁剤を一括に積層して貫通ホールと電子素子との間の空隙のその他の部分を絶縁剤の一部で充填する段階とを含むことを特徴とする。
【選択図】図２

Description

本発明は、電子素子内蔵型印刷回路基板の製造方法に関する。
携帯用電子機器の小型化により電子部品の実装面積が減少している。従来集積回路（Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ：ＩＣ ）パッケージでは、高密度化のために受動素子と能動素子とを上に積み上げる３Ｄパッケージの形態であった。このような集積回路パッケージは、実装面積の減少にある程度効果的であった。
しかし、表面実装では小型化に限界があり、能動型や受動型の電子素子を基板内に内蔵することにより、さらに効果のある小型高密度化を具現することができる。電子素子内蔵型基板を製造する代表的な方法を説明すると、次の通りである。
先ず、銅箔積層板の電子素子が内蔵される位置に貫通ホールを穿孔する。以後、貫通ホールの一面にテープを付着し、貫通ホールの内部の露出されたテープの接着面に電子素子を付着する。次に、貫通ホールのその他の部分を充填材で充填し、充填材が硬化されたらテープを除去する。テープが除去された面には、電子素子の電気接点が露出されるが、このような露出された電気接点と回路パターンとを連結するために無電解メッキ及び電解メッキの過程を経る。無電解メッキは、充填材が非伝導性であるため追加される工程である。メッキ工程が終わると、回路パターン形成工程が行われる。
しかし、上記工程において、貫通ホールに電子素子を挿入した後に充填材で貫通ホールを充填する方法は、異種の物質が互いに境界面に接しているので、物理的環境の変化に応じて基板が反るなどの副作用が発生する。
本発明は、異種材料を最小限に使用することにより電子素子を内蔵しても、基板の反り現象が最小化される電子素子内蔵型印刷回路基板の製造方法を提供する。
本発明の一実施形態によれば、（ａ）表面に回路パターンの形成されたコア基板に貫通ホールを穿孔する段階と、（ｂ）コア基板の一側にテープを付着して電子素子を、貫通ホールの内部のテープが露出された部分に付着する段階と、（ｃ）貫通ホールと電子素子との間の空隙の一部に接着剤を充填して電子素子を固定する段階と、（ｄ）テープを除去する段階と、及び（ｅ）コア基板の両側に絶縁剤を一括積層して、貫通ホールと電子素子との間の空隙のその他の部分を絶縁剤の一部で充填する段階とを含む電子素子内蔵型印刷回路基板の製造方法が提供される。
上記段階（ｅ）の後に、絶縁剤の表面に回路パターンを形成する段階をさらに含むことができる。
本発明によれば、電子素子を印刷回路基板に内蔵する時、最小限の接着剤を用いて固定するので、異種材料を用いて電子素子を内蔵する場合に発生する基板の反り現象を防止することができる。
以下、本発明による電子素子内蔵型印刷回路基板の製造方法の好ましい実施例を添付図面を参照して詳しく説明する。添付図面を参照して説明することにおいて、図面符号にかかわらず同一である構成要素は同一の参照符号を付与し、これに対する重複される説明は略する。
図１は、本発明の好ましい一実施例による電子素子内蔵型印刷回路基板の製造方法に対するフローチャートであり、図２は、本発明の好ましい一実施例による電子素子内蔵型印刷回路基板の製造方法に対する工程図である。図２を参照すると、コア基板２０、絶縁層２１ａ、回路パターン２１及び２９、貫通ホール２２、テープ２３、電子素子２４、パッド２４ａ、接着剤２５、絶縁剤２６、印刷回路基板２００が示されている。
図１の段階Ｓ１１は、表面に回路パターン２１が形成されたコア基板２０に貫通ホール２２を穿孔する段階であり、図２の（ａ）が、これに対応する工程である。コア基板２０は、絶縁層２１ａの表面に回路パターン２１が形成された形態である。回路パターン２１は、サブトラクティブ（ｓｕｂｔｒａｃｔｉｖｅ）、セミアディティブ（ｓｅｍｉ−ａｄｄｉｔｉｖｅ）などのような一般的な工法で形成される。貫通ホール２２は、コア基板２０に電子素子２４が実装される位置を選別して穿孔する。穿孔方法としては、機械的なドリルを用いることがよい。
図１の段階Ｓ１２は、コア基板２０の一側にテープを付着して電子素子２４を、貫通ホール２２の内のテープ２３が露出された部分に付着する段階であり、図２の（ｂ）と（ｃ）が、これに対応する工程である。テープ２３は、貫通ホール２２の一側を遮断して、電子素子２４が接着剤２５により固定される前に臨時的に固定させるための材料である。電子素子２４は貫通ホール２２に挿入されるが、この時、パッド２４ａがテープ２３と接触されるように挿入することがよい。
図１の段階Ｓ１３は、貫通ホール２２と電子素子２４との間の空隙２７の一部に接着剤２５を充填して上記電子素子２４を固定する段階であり、Ｓ１４は、テープ２３を除去する段階であり、図２の（ｄ）と（ｅ）は、これに対応する工程である。接着剤２５は、絶縁層２１ａの材質とは異なって、異種材料は熱膨脹係数が異なるため、外部の熱に露出される場合基板が反る原因となる。これは、製品の信頼性にかなり悪影響を及ぼす。従って、このような異種材料間の接触を最小化することが重要である。本工程の接着剤２５は、電子素子２４を一定時間だけ貫通ホール２２に固定させる役目をすればよい。よって、電子素子２４と貫通ホール２２との間の空隙をすべて接着剤２５で充填する必要はなく、電子素子２４が臨時的に固定される程度で用いればいい。よって、空隙２７の一部だけに接着剤２５が充填されることになる。本実施例にように電子素子２４を固定する場合、接着剤２５の使用量が少ないので、異種材料の間で発生し得る問題は減少する。図３及び図４は、それぞれ空隙２７の二つの地点と四つの地点に接着剤２５を充填して電子素子２４を固定する形態を示す。
接着剤２５が充分に硬化されたら、テープ２３を除去する。テープ２３は、穿孔ホール２２に電子素子２４を固定するために用いられる一時的な材料であり、以後の工程のために除去することがよい。
図１の段階Ｓ１５は、コア基板２０の両側に絶縁剤２６を一括積層して貫通ホール２２と電子素子２４との間の空隙２７のその他の部分を絶縁剤２６で充填する段階であり、図２の（ｆ）と（ｇ）は、これに対応する工程である。また、絶縁剤２６としては、比較的に流れのよいレジンの含量が高いものがよい。この段階で熱を加えて圧着する場合、絶縁剤２６の一部であるレジンが空隙２７のその他の部分に流れ込んで充填されるようになる。以後、温度を低めると絶縁剤２６は硬化され、空隙２７に流れ込んだレジンも硬化されて電子素子２４は安定的に固定される。
以後、図２の（ｈ）のように、絶縁剤２６の表面に追加的に回路パターン２９を形成することができる。この場合に回路パターン２９の一部は、パッド２４ａと電気的に接続することが好ましい。さらに、回路パターン２９の一部が、回路パターン２１と電気的に接続してもよいし、パッド２４ａと回路パターン２１との間を電気的に接続してもよい。
本発明の技術思想が上述した実施例により具体的に記述されたが、上述した実施例はその説明のためのものであり、その制限のためのものではないし、本発明の技術分野において通常の専門家であれば、本発明の技術思想の範囲内で多様な実施例が可能であることを理解できるだろう。
本発明の好ましい一実施例による電子素子内蔵型印刷回路基板の製造方法のフローチャートである。 本発明の好ましい一実施例による電子素子内蔵型印刷回路基板の製造方法の工程図である。 本発明の好ましい一実施例による電子素子内蔵型印刷回路基板の平面図である。 本発明の好ましい一実施例による電子素子内蔵型印刷回路基板の平面図である。
符号の説明
２０ コア基板
２１ａ 絶縁層
２１ 回路パターン
２２ 貫通ホール
２３ テープ
２４ 電子素子
２４ａ パッド
２５ 接着剤
２６ 絶縁剤

Claims (2)

  1. （ａ）表面に回路パターンが形成されたコア基板に貫通ホールを穿孔する段階と、
    （ｂ）前記コア基板の一側にテープを付着し、電子素子を前記貫通ホールの内の前記テープが露出された部分に付着する段階と、
    （ｃ）前記貫通ホールと前記電子素子との間の空隙の一部に接着剤を充填し、前記電子素子を固定する段階と、
    （ｄ）前記テープを除去する段階と、及び
    （ｅ）前記コア基板の両側に絶縁剤を一括積層し、前記貫通ホールと前記電子素子との間の空隙のその他の部分を前記絶縁剤で充填する段階と
    を含む電子素子内蔵型印刷回路基板の製造方法。
  2. 前記段階（ｅ）の後に、前記絶縁剤の表面に回路パターンを形成する段階をさらに含む請求項１記載の電子素子内蔵型印刷回路基板の製造方法。
JP2007283566A 2006-11-21 2007-10-31 電子素子内蔵型印刷回路基板の製造方法 Pending JP2008131039A (ja)

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