CN101188915B - 制造元件嵌入式印刷电路板的方法 - Google Patents
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Abstract
本发明公开了一种制造元件嵌入式印刷电路板的方法。该方法包括:在核心衬底中打通孔,该核心衬底的表面上形成有电路图案;将胶带贴于该核心衬底的一侧并将元件贴在该胶带的暴露于该通孔中的部分上;在该通孔与该元件之间的间隙的一部分中填充粘合剂,以固定该元件;去除该胶带;以及在该核心衬底的两侧上集中堆叠绝缘层,以用该绝缘层的一些部分填充该通孔与该元件之间的间隙的剩余部分,可采用极少量的不同类材料将该元件嵌入,从而可以防止电路板的翘曲。
Description
相关申请交叉参考
本申请要求于2006年11月21日向韩国知识产权局提交的第10-2006-0115399号韩国专利申请的权益,其公开内容整体结合于此作为参考。
发明领域
本发明涉及一种制造元件嵌入式(component-embedded)印刷电路板的方法。
背景技术
随着便携式电子器件尺寸的减小,用于安装电子元件的面积也在减小。一些传统的IC封装具有3D封装的形式,其中将无源元件和有源元件向上堆积,以实现较大的密度。这种IC封装形式在某种程度上对于减小安装面积而言是有效的。
然而,由于在使用表面安装工艺时其对减小尺寸是有限的,因此可以将有源和无源元件嵌入电路板中,以在较小的尺寸上实现较大的密度。如下所述是一种典型的制造元件嵌入式电路板的方法。
首先,在覆铜箔层压板上的待嵌入电子元件的位置中打通孔。然后,在通孔的一侧处贴上胶带,将电子元件贴在胶带的暴露于通孔内侧的粘结面上。接着,用填料填充通孔的剩余部分,并且当填料固化后,去除胶带。在胶带被去除的表面上露出电子元件的电触点,为使露出的触点与电路图案相接触,执行化学镀和电镀工艺。加入化学镀是因为填料是非导电性的。在镀覆工艺之后,执行形成电路图案的工艺。
然而,在上述工艺中,当将元件嵌入通孔后在通孔内填充填料时,不同类材料彼此相互接触,从而可能产生不理想的效果,诸如由于其环境的物理变化而引起的电路板翘曲。
发明内容
本发明的一个方面是提供一种制造元件嵌入式印刷电路板的方法,该方法需要使用极少量的不同类材料,从而即使在元件被嵌入时电路板的翘曲也最小。
所要求的本发明的一个方面提供一种制造元件嵌入式印刷电路板的方法,该方法包括:在核心衬底(core substrate)中打通孔,该核心衬底的表面上形成有电路图案;将胶带贴于该核心衬底的一侧并将元件贴在该胶带的暴露于该通孔中的部分上;在该通孔与该元件之间的间隙的一部分中填充粘合剂,以固定该元件;去除该胶带;以及在该核心衬底的两侧上集中堆叠绝缘层,以用该绝缘层的一些部分填充该通孔与该元件之间的间隙的剩余部分。
在集中堆叠该绝缘层后,可进一步包括在该绝缘层的表面上形成电路图案的操作。
本发明的其他方面和优点将在以下描述中部分地阐述,并且通过该描述部分地显而易见,或者可以通过实施本发明来理解。
附图说明
图1是示出根据本发明实施例的制造元件嵌入式印刷电路板的方法的流程图。
图2是示出根据本发明实施例的制造元件嵌入式印刷电路板方法的工艺图。
图3和图4是根据本发明某些实施例的元件嵌入式印刷电路板的平面图。
具体实施方式
下面将结合附图更详细地描述本发明的实施例。在结合附图的描述中,不管图号如何,使用相同的参考标号来表示那些相同或相应的部件,并省略重复性描述。
图1是示出根据本发明实施例的制造元件嵌入式印刷电路板的方法的流程图,图2是示出根据本发明实施例的制造元件嵌入式印刷电路板的方法的工艺图。图2中示出了核心衬底20、绝缘层21a、电路图案21和29、通孔22、胶带23、元件24、焊盘24a、粘合剂25以及绝缘层26。
图1的操作S11表示在具有形成于表面上的电路图案21的核心衬底20中打通孔22,图2的(a)示出相应的工艺。核心衬底20可具有绝缘层21a的形式,电路图案21形成在绝缘层21a的表面上。电路图案21可以采用普通工艺形成,诸如减成或者半加成工艺,等。可在选择待安装元件24的位置之后再在核心衬底20中打通孔22。打孔方法可包括使用机械钻孔机。
图1的操作S12表示将胶带贴于核心衬底20的一侧并将元件24贴在胶带23的暴露于通孔22中的部分上,图2(b)和图2(c)示出相应的工艺。胶带23可以是这样一种材料,其封闭通孔22,然后在元件24被粘合剂25固定前暂时性地固定元件24。可将元件24插入通孔22中,其中该元件插入使得焊盘24a与胶带23相接触。
图1的操作S13表示在通孔22与元件24之间的间隙27的一部分中填充粘合剂25以固定元件24,操作S14表示去除胶带23,其中图2的(d)和(e)示出了相应的工艺。粘合剂25可能具有与绝缘层21a不同的材料,由于不同类材料具有不同的热膨胀系数,因而这可能造成电路板在受到外部加热时产生翘曲。这会在产品的可靠性方面造成不利影响。因此,将这种不同材料之间的接触最小化是很重要的。在该工艺中,粘合剂25可只在特定长的时间内将元件24固定在通孔22内。因此,元件24与通孔22之间的间隙无须被粘合剂25完全填充,只需使用能够暂时性地固定元件24的一定量。这样,只在间隙27的一部分中填充粘合剂25。当如在本发明实施例中这样固定元件24之后,减少了粘合剂25的使用,从而可减少在不同类材料之间可能产生的问题。图3和图4分别示出在间隙27中的两个位置处和四个位置处填充粘合剂25,以固定元件24。
当粘合剂25被充分固化时,可以去除胶带23。胶带23可以是用于将元件24固定在通孔22中的一种暂时性的材料,因此可被去除以进行随后的工艺。
图1的操作S15表示在核心衬底20的两侧上集中堆叠绝缘层26,以用绝缘层26的一部分来填充通孔22与元件24之间的间隙27的剩余部分,图2的(f)和(g)示出了相应的工艺。绝缘层26可包含高含量的具有相对良好的流动特性的树脂。因此,当施加热压力时,该树脂(即绝缘层26的一些部分)可以流入并填充间隙27的剩余部分。然后,当温度降低时,绝缘层26可被固化,并且该树脂也流向间隙27,由此元件24可以稳固的方式被固定。
然后,如图2的(h)所示,还可在绝缘层26的表面上形成电路图案29。
根据如上所述本发明的某些实施例,可以用最少量的粘合剂将元件嵌入印刷电路板中,从而可以防止在使用不同类材料嵌入元件时可能发生的电路板翘曲。
尽管已经结合具体实施例详细描述了本发明的精神,但是这些实施例仅用于示例性的目的,而并非限制本发明。应该理解,在不背离本发明的范围和精神的前提下,本领域的技术人员可以对这些实施例进行改变和修改。
Claims (2)
1.一种制造元件嵌入式印刷电路板的方法,所述方法包括:
在其至少一个表面上形成有电路图案的核心衬底上打至少一个通孔;
将胶带贴于所述核心衬底的一侧,并且将元件贴在所述胶带的暴露于所述通孔中的部分上;
在所述通孔与所述元件之间的间隙的两个或四个位置处分别填充粘合剂,以固定所述元件;
去除所述胶带;以及
在所述核心衬底的两侧上集中堆叠绝缘层,以利用所述绝缘层的一部分填充所述通孔与所述元件之间的所述间隙的剩余部分。
2.根据权利要求1所述的方法,在所述集中堆叠后,进一步包括在所述绝缘层的表面上形成电路图案。
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