JPH0236037U - - Google Patents
Info
- Publication number
- JPH0236037U JPH0236037U JP11535888U JP11535888U JPH0236037U JP H0236037 U JPH0236037 U JP H0236037U JP 11535888 U JP11535888 U JP 11535888U JP 11535888 U JP11535888 U JP 11535888U JP H0236037 U JPH0236037 U JP H0236037U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- wiring board
- printed wiring
- insulating substrate
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Die Bonding (AREA)
Description
第１図ａ，ｂは本考案の一実施例の平面図及び
Ａ―Ａ′線断面図、第２図ａ〜ｃは本考案の一実
施例の使用方法を説明するための断面図、第３図
ａ，ｂは従来のチツプ・オン・ボード用プリント
配線基板の一例の平面図及びＢ―Ｂ′線断面図、
第４図は第３図ａ，ｂに示すプリント配線基板の
使用方法を説明するための断面図である。 １……絶縁基板、２……配線、３……チツプ搭
載部、４……窪み、５……孔、６……粘着テープ
、７……半導体チツプ、８……樹脂、９……デイ
スペンサ、１０……金属線、１１……封止枠、１
２……樹脂。
Ａ―Ａ′線断面図、第２図ａ〜ｃは本考案の一実
施例の使用方法を説明するための断面図、第３図
ａ，ｂは従来のチツプ・オン・ボード用プリント
配線基板の一例の平面図及びＢ―Ｂ′線断面図、
第４図は第３図ａ，ｂに示すプリント配線基板の
使用方法を説明するための断面図である。 １……絶縁基板、２……配線、３……チツプ搭
載部、４……窪み、５……孔、６……粘着テープ
、７……半導体チツプ、８……樹脂、９……デイ
スペンサ、１０……金属線、１１……封止枠、１
２……樹脂。
Claims (1)
- 配線が表面に形成された絶縁基板に半導体チツ
プを搭載するための凹部が形成されているプリン
ト配線基板において、前記半導体チツプを固着す
る樹脂の上面と同じレベルの面を底面とする窪み
を前記凹部に接して設け、かつ前記窪みに前記絶
縁基板を貫通する孔を設けたことを特徴とするプ
リント配線基板。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11535888U JPH0236037U (ja) | 1988-08-31 | 1988-08-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11535888U JPH0236037U (ja) | 1988-08-31 | 1988-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0236037U true JPH0236037U (ja) | 1990-03-08 |
Family
ID=31356946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11535888U Pending JPH0236037U (ja) | 1988-08-31 | 1988-08-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0236037U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008131039A (ja) * | 2006-11-21 | 2008-06-05 | Samsung Electro-Mechanics Co Ltd | 電子素子内蔵型印刷回路基板の製造方法 |
-
1988
- 1988-08-31 JP JP11535888U patent/JPH0236037U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008131039A (ja) * | 2006-11-21 | 2008-06-05 | Samsung Electro-Mechanics Co Ltd | 電子素子内蔵型印刷回路基板の製造方法 |