JPS62199948U - - Google Patents

Info

Publication number
JPS62199948U
JPS62199948U JP8814186U JP8814186U JPS62199948U JP S62199948 U JPS62199948 U JP S62199948U JP 8814186 U JP8814186 U JP 8814186U JP 8814186 U JP8814186 U JP 8814186U JP S62199948 U JPS62199948 U JP S62199948U
Authority
JP
Japan
Prior art keywords
board
substrate
wire bonding
auxiliary
semiconductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8814186U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8814186U priority Critical patent/JPS62199948U/ja
Publication of JPS62199948U publication Critical patent/JPS62199948U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Die Bonding (AREA)

Description

【図面の簡単な説明】
第1図は本考案の実施例を示す断面図、第2図
は従来の半導体回路基板を示す断面図である。 1……主基板、2……IC素子、3……透孔、
4……補助基板。

Claims (1)

    【実用新案登録請求の範囲】
  1. IC素子をワイヤボンデイングにより基板パタ
    ーンと接続して回路構成した半導体回路基板にお
    いて、IC素子塔載部位に透孔を穿設した主基板
    と、IC素子を塔載した薄膜状補助基板とからな
    り、このIC素子を前記透孔に遊挿して補助基板
    を主基板に接着し、ワイヤボンデイングした後、
    その上面に封止材を被着した半導体回路基板。
JP8814186U 1986-06-10 1986-06-10 Pending JPS62199948U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8814186U JPS62199948U (ja) 1986-06-10 1986-06-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8814186U JPS62199948U (ja) 1986-06-10 1986-06-10

Publications (1)

Publication Number Publication Date
JPS62199948U true JPS62199948U (ja) 1987-12-19

Family

ID=30945980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8814186U Pending JPS62199948U (ja) 1986-06-10 1986-06-10

Country Status (1)

Country Link
JP (1) JPS62199948U (ja)

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