JPH0470738U - - Google Patents
Info
- Publication number
- JPH0470738U JPH0470738U JP11440890U JP11440890U JPH0470738U JP H0470738 U JPH0470738 U JP H0470738U JP 11440890 U JP11440890 U JP 11440890U JP 11440890 U JP11440890 U JP 11440890U JP H0470738 U JPH0470738 U JP H0470738U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- die bonding
- chamfered
- bonded
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第１図は、本考案に係る半導体素子の一実施例
の実装状態を示す斜視図、第２図は、第１図に示
される半導体素子の斜視図、第３図は、上述の例
の変形例の説明に供される図、第４図は、従来の
半導体素子の一例の実装状態を示す側面図、第５
図は、上述の従来例の説明に供される図である。 １０……半導体素子、１２……ダイボンデイン
グ電極、１４……配線基板、１５……ダイボンド
レジン、１７……副面。
の実装状態を示す斜視図、第２図は、第１図に示
される半導体素子の斜視図、第３図は、上述の例
の変形例の説明に供される図、第４図は、従来の
半導体素子の一例の実装状態を示す側面図、第５
図は、上述の従来例の説明に供される図である。 １０……半導体素子、１２……ダイボンデイン
グ電極、１４……配線基板、１５……ダイボンド
レジン、１７……副面。
Claims (1)
- 基板に接合されるダイボンデイング面側におけ
る外周縁部の少なくとも一部が面取りされている
ことを特徴とする半導体素子。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11440890U JPH0470738U (ja) | 1990-10-31 | 1990-10-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11440890U JPH0470738U (ja) | 1990-10-31 | 1990-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0470738U true JPH0470738U (ja) | 1992-06-23 |
Family
ID=31862083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11440890U Pending JPH0470738U (ja) | 1990-10-31 | 1990-10-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0470738U (ja) |
-
1990
- 1990-10-31 JP JP11440890U patent/JPH0470738U/ja active Pending