JPS6212948U - - Google Patents
Info
- Publication number
- JPS6212948U JPS6212948U JP1985105045U JP10504585U JPS6212948U JP S6212948 U JPS6212948 U JP S6212948U JP 1985105045 U JP1985105045 U JP 1985105045U JP 10504585 U JP10504585 U JP 10504585U JP S6212948 U JPS6212948 U JP S6212948U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor device
- semiconductor elements
- spacer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Wire Bonding (AREA)
Description
第1図は本考案の一実施例の断面図、第2図は
本考案の他の実施例の断面図、第3図は従来の半
導体装置の断面図である。 1……回路基板、11……両面回路基板、2a
,2b,4a,4b,24a,24b……配線パ
ターン、3,13,23……半導体素子、5……
スペーサ、6,25……樹脂枠、7,17……封
止樹脂、8……スペーサ兼樹脂枠、9……チツプ
部品。
本考案の他の実施例の断面図、第3図は従来の半
導体装置の断面図である。 1……回路基板、11……両面回路基板、2a
,2b,4a,4b,24a,24b……配線パ
ターン、3,13,23……半導体素子、5……
スペーサ、6,25……樹脂枠、7,17……封
止樹脂、8……スペーサ兼樹脂枠、9……チツプ
部品。
Claims (1)
- 回路基板上に取付けられた複数の半導体素子を
有する半導体装置において、前記半導体素子の少
くとも一つは、前記回路基板面との間に所定の間
隔をとるためのスペーサを介して取付けられてい
ることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985105045U JPS6212948U (ja) | 1985-07-09 | 1985-07-09 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985105045U JPS6212948U (ja) | 1985-07-09 | 1985-07-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6212948U true JPS6212948U (ja) | 1987-01-26 |
Family
ID=30979100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985105045U Pending JPS6212948U (ja) | 1985-07-09 | 1985-07-09 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6212948U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08330509A (ja) * | 1995-05-31 | 1996-12-13 | Nec Corp | 電子回路装置およびその製造方法 |
-
1985
- 1985-07-09 JP JP1985105045U patent/JPS6212948U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08330509A (ja) * | 1995-05-31 | 1996-12-13 | Nec Corp | 電子回路装置およびその製造方法 |