JPS61102074U - - Google Patents

Info

Publication number
JPS61102074U
JPS61102074U JP1984187596U JP18759684U JPS61102074U JP S61102074 U JPS61102074 U JP S61102074U JP 1984187596 U JP1984187596 U JP 1984187596U JP 18759684 U JP18759684 U JP 18759684U JP S61102074 U JPS61102074 U JP S61102074U
Authority
JP
Japan
Prior art keywords
semiconductor element
hole
board
element fixed
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1984187596U
Other languages
English (en)
Other versions
JPH0249731Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984187596U priority Critical patent/JPH0249731Y2/ja
Publication of JPS61102074U publication Critical patent/JPS61102074U/ja
Application granted granted Critical
Publication of JPH0249731Y2 publication Critical patent/JPH0249731Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】
第１図ａは本考案の一実施例の封止樹脂を透視
して示した一面側の平面図、同図ｂは断面図、同
図ｃは裏面側の封止樹脂を透視して示した平面図
、第２図ａは従来の半導体装置の一面側の平面図
、同図ｂは断面図、同図ｃは裏面側の平面図であ
る。 １……両面印刷配線基板、２，３……導電路、
４……第１の半導体素子、５……第２の半導体素
子、６，７……金属細線、８，９……封止樹脂、
１０……基板の穴。

Claims (1)

    【実用新案登録請求の範囲】
  1. 両面印刷配線基板と、この基板にあけられた穴
    を塞ぐようにして前記基板の一面側に固着された
    第１の半導体素子と、前記穴に露出した前記第１
    の半導体素子の底面に、前記穴に埋没するように
    して固着されて第２の半導体素子とを備えたこと
    を特徴とする半導体装置。
JP1984187596U 1984-12-11 1984-12-11 Expired JPH0249731Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984187596U JPH0249731Y2 (ja) 1984-12-11 1984-12-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984187596U JPH0249731Y2 (ja) 1984-12-11 1984-12-11

Publications (2)

Publication Number Publication Date
JPS61102074U true JPS61102074U (ja) 1986-06-28
JPH0249731Y2 JPH0249731Y2 (ja) 1990-12-27

Family

ID=30745058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984187596U Expired JPH0249731Y2 (ja) 1984-12-11 1984-12-11

Country Status (1)

Country Link
JP (1) JPH0249731Y2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002015272A1 (en) * 2000-08-14 2002-02-21 Niigata Seimitsu Co., Ltd. Tuner device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002015272A1 (en) * 2000-08-14 2002-02-21 Niigata Seimitsu Co., Ltd. Tuner device

Also Published As

Publication number Publication date
JPH0249731Y2 (ja) 1990-12-27

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