JP2007519217A5 - - Google Patents

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Publication number
JP2007519217A5
JP2007519217A5 JP2006517180A JP2006517180A JP2007519217A5 JP 2007519217 A5 JP2007519217 A5 JP 2007519217A5 JP 2006517180 A JP2006517180 A JP 2006517180A JP 2006517180 A JP2006517180 A JP 2006517180A JP 2007519217 A5 JP2007519217 A5 JP 2007519217A5
Authority
JP
Japan
Prior art keywords
gate
layer
forming
sidewall
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006517180A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007519217A (ja
Filing date
Publication date
Priority claimed from US10/601,401 external-priority patent/US6913959B2/en
Application filed filed Critical
Publication of JP2007519217A publication Critical patent/JP2007519217A/ja
Publication of JP2007519217A5 publication Critical patent/JP2007519217A5/ja
Pending legal-status Critical Current

Links

JP2006517180A 2003-06-23 2004-06-05 半導体デバイスおよびその製造方法 Pending JP2007519217A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/601,401 US6913959B2 (en) 2003-06-23 2003-06-23 Method of manufacturing a semiconductor device having a MESA structure
PCT/US2004/017727 WO2005001908A2 (en) 2003-06-23 2004-06-05 Strained semiconductor device and method of manufacture

Publications (2)

Publication Number Publication Date
JP2007519217A JP2007519217A (ja) 2007-07-12
JP2007519217A5 true JP2007519217A5 (enExample) 2009-06-04

Family

ID=33552165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006517180A Pending JP2007519217A (ja) 2003-06-23 2004-06-05 半導体デバイスおよびその製造方法

Country Status (8)

Country Link
US (1) US6913959B2 (enExample)
JP (1) JP2007519217A (enExample)
KR (1) KR101065046B1 (enExample)
CN (1) CN100521231C (enExample)
DE (1) DE112004001117B4 (enExample)
GB (1) GB2418533B (enExample)
TW (1) TWI341546B (enExample)
WO (1) WO2005001908A2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100725112B1 (ko) * 2005-04-27 2007-06-04 한국과학기술원 백―바이어스를 이용하여 ｓｏｉ 기판에 형성된 플래시 블록을 소거하기 위한 플래시 메모리 소자의 제조 방법, 그 소거 방법 및 그 구조
JP4988217B2 (ja) * 2006-02-03 2012-08-01 株式会社日立製作所 Ｍｅｍｓ構造体の製造方法
US9184263B2 (en) * 2013-12-30 2015-11-10 Globalfoundries Inc. Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
US10170332B2 (en) * 2014-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET thermal protection methods and related structures
US10014410B2 (en) 2014-12-02 2018-07-03 Renesas Electronics Corporation Method for producing semiconductor device and semiconductor device
US20170366965A1 (en) * 2016-06-21 2017-12-21 Chiun Mai Communication Systems, Inc. Communication device, communication system and method therefor

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Publication number Priority date Publication date Assignee Title
DE69213539T2 (de) * 1991-04-26 1997-02-20 Canon Kk Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor
US5397904A (en) * 1992-07-02 1995-03-14 Cornell Research Foundation, Inc. Transistor microstructure
DE4340967C1 (de) * 1993-12-01 1994-10-27 Siemens Ag Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit mindestens einem MOS-Transistor
JP3078720B2 (ja) * 1994-11-02 2000-08-21 三菱電機株式会社 半導体装置およびその製造方法
DE19544721C1 (de) * 1995-11-30 1997-04-30 Siemens Ag Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit mindestens einem MOS-Transistor
JP3472401B2 (ja) * 1996-01-17 2003-12-02 三菱電機株式会社 半導体装置の製造方法
DE19711482C2 (de) * 1997-03-19 1999-01-07 Siemens Ag Verfahren zur Herstellung eines vertikalen MOS-Transistors
US6118161A (en) * 1997-04-30 2000-09-12 Texas Instruments Incorporated Self-aligned trenched-channel lateral-current-flow transistor
JPH1131659A (ja) * 1997-07-10 1999-02-02 Toshiba Corp 半導体装置の製造方法
US6200866B1 (en) * 1998-02-23 2001-03-13 Sharp Laboratories Of America, Inc. Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET
KR100280106B1 (ko) * 1998-04-16 2001-03-02 윤종용 트렌치 격리 형성 방법
US6080612A (en) * 1998-05-20 2000-06-27 Sharp Laboratories Of America, Inc. Method of forming an ultra-thin SOI electrostatic discharge protection device
US6339002B1 (en) * 1999-02-10 2002-01-15 International Business Machines Corporation Method utilizing CMP to fabricate double gate MOSFETS with conductive sidewall contacts
US6770689B1 (en) * 1999-03-19 2004-08-03 Sakura Color Products Corp. Aqueous glittering ink
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
JP2002151688A (ja) * 2000-08-28 2002-05-24 Mitsubishi Electric Corp Ｍｏｓ型半導体装置およびその製造方法
US6495401B1 (en) * 2000-10-12 2002-12-17 Sharp Laboratories Of America, Inc. Method of forming an ultra-thin SOI MOS transistor
KR100346845B1 (ko) * 2000-12-16 2002-08-03 삼성전자 주식회사 반도체 장치의 얕은 트렌치 아이솔레이션 형성방법
EP1244142A1 (en) * 2001-03-23 2002-09-25 Universite Catholique De Louvain Fabrication method of SOI semiconductor devices
US6635923B2 (en) 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
KR100428768B1 (ko) * 2001-08-29 2004-04-30 삼성전자주식회사 트렌치 소자 분리형 반도체 장치 및 그 형성 방법
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6611029B1 (en) 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6872606B2 (en) * 2003-04-03 2005-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with raised segment

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