Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
  • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
  • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
  • H10D30/6743—Silicon
  • H10D30/6744—Monocrystalline silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

Definitions

• the present invention relates, in general, to a semiconductor device and, more particularly, to carrier mobility in the semiconductor device and to a method for manufacturing the semiconductor device.
• IGFETs Insulated Gate Field Effect Transistors
• short channel effects can be mitigated by adjusting the electric field in the channel region to minimize the peak lateral electric field of the drain depletion region.
• One technique for lowering the lateral electric field is to include source and drain extension regions.
• Another technique suitable for increasing carrier mobility and mitigating short channel effects is to manufacture the devices on a Silicon-On-Insulator (SOI) substrate.
• SOI Silicon-On-Insulator
• Mobility can be further increased by straining the semiconductor devices.
• a drawback in manufacturing strained semiconductor devices has been the inability to develop large scale manufacturing processes capable of producing semiconductor devices that are under substantially the same amount of strain. Accordingly, what is needed is a semiconductor device having a predetermined amount of strain and a method for manufacturing the semiconductor device.
• the present invention satisfies the foregoing need by providing a semiconductor device having a strained channel region and a method for manufacturing the semiconductor device.
• the present invention includes forming a mesa structure from a semiconductor substrate, wherein the mesa structure has a first surface and first and second sidewalls.
• a gate structure having a gate surface and first and second sides is formed over the mesa structure, wherein first and second portions of the gate structure are disposed on the first and second sidewalls, respectively. Portions of the semiconductor substrate adjacent the first and second sides of the gate structure are doped.
• the present invention includes a method for manufacturing a strained semiconductor device suitable for use in an integrated circuit.
• a semiconductor-on-insulator mesa isolation structure having a top surface and first and second sidewalls is provided.
• a gate dielectric material is formed on the top surface and the first and second sidewalls and a gate is formed on the gate dielectric material, wherein the gate and the gate dielectric material cooperate to form a gate structure having a top surface and gate sidewalls.
• a semiconductor material is formed on portions of the top surface of the mesa isolation structure adjacent to the first and second sidewalls.
• Suicide is formed from the semiconductor material and from the gate, wherein the silicide from the gate strains the semiconductor-on-insulator mesa isolation structure.
• the present invention comprises a method for straining a semiconductor device.
• a semiconductor substrate comprising a first layer of semiconductor material is disposed over a layer of dielectric material, wherein the semiconductor substrate has a top surface and isolation sidewalls.
• a gate structure having a gate surface, first and second opposing gate sidewalls, and third and fourth opposing sides is formed on the semiconductor substrate.
• Silicide is formed from the gate surface and the first and second opposing sidewalls of the gate structure, wherein the silicide strains the semiconductor material of the semiconductor substrate.
• the present invention includes a strained semiconductor device suitable for use in an integrated circuit.
• the strained semiconductor device comprises a semiconductor-on-insulator substrate in a mesa isolation configuration.
• a gate structure having a gate surface, first and second opposing sidewalls, and third and fourth opposing sidewalls is disposed on the semiconductor-on-insulator substrate.
• First and second doped regions are adjacent the third and fourth sidewalls, respectively, of the gate structure.
• First and second silicide regions are disposed on the first and second doped regions, respectively.
• a gate silicide is disposed on the gate, wherein the gate silicide strains a channel region of the semiconductor device.
• FIG. 1 is a perspective view of a portion of a semiconductor device at a beginning stage of manufacture in accordance with an embodiment of the present invention
• FIG. 2 is a cross-sectional side view of the device of FIG. 1 taken along section line 2-2
• FIG. 3 is a cross-sectional side view of the semiconductor device of FIG. 2 further along in processing
• FIG. 4 is a cross-sectional side view of the semiconductor device of FIG. 3 further along in processing
• FIG. 5 is a cross-sectional side view of the semiconductor device of FIG.
• FIG. 6 is a cross-sectional side view of the semiconductor device of FIGS. 4 and 5 further along in processing
• FIG. 7 is a cross-sectional side view of the semiconductor device of FIG. 6 further along in processing
• FIG. 8 is a cross-sectional side view of the semiconductor device of FIG. 7 further along in processing
• FIG. 9 is a cross-sectional side view of the semiconductor device of FIG. 8 further along in processing
• FIG. 10 is a cross-sectional side view of the semiconductor device of FIG. 9 further along in processing
• FIG. 11 is a cross-sectional side view of the semiconductor device of FIG. 10 taken along section line 11-11.
• the present invention provides an integrated circuit that includes a strained semiconductor device or transistors and a method for manufacturing the strained semiconductor device.
• the semiconductor device is strained to increase the mobility of the electrons and holes in its channel region.
• the combination of a mesa isolation structure and a suicided gate structure increases the hole mobility by causing the channel region to be under a compressive stress.
• the combination of underetching the buried oxide of the mesa structure and wrapping a gate dielectric and a gate material around the underetched mesa structure increases the electron and hole mobiUties by causing the channel region to be under tensile stress.
• the silicide is preferably nickel silicide.
• the stress can be further increased by annealing the silicide at an elevated temperature.
• the tensile stress of a nickel silicide gate is approximately 800 MegaPascals (MPa) when annealed at a temperature of 360 °C and approximately 1.25 GigaPascals (GPa) when annealed at a temperature of 400 °C.
• the channel region is maintained under tensile stress by manufacturing the gate to have a width of less than approximately 250 nm.
• FIG. 1 is a perspective view of a portion of a semiconductor device 10 during manufacture in accordance with an embodiment of the present invention. What is shown in FIG.
• SOI substrate 12 is a Semiconductor-On- Insulator (SOI) substrate 12 patterned to include a mesa isolation structure 14 having a substrate surface 20 and sidewalls 16 ' and 18.
• SOI substrate 12 comprises a layer of semiconductor material 22 disposed on a layer of dielectric material 24 which is disposed on a body of semiconductor material 26.
• layer of semiconductor material 22 is undoped silicon having a thickness ranging from that of a monolayer of silicon to approximately 25 nanometers (nm) and dielectric layer 24 has a thickness ranging between approximately 50 nanometers and approximately 500 nm. More preferably, silicon layer 22 has a thickness of less than 10 nm and dielectric layer 24 has a thickness of about 200 nm.
• Substrate surface 22 is also referred to as a top surface of the substrate or an active surface. Techniques for forming mesa isolation structures are known to those skilled in the art. Referring now to FIG. 2, patterned SOI substrate 12 taken along section line 2-2 of FIG. 1 is shown. More particularly, FIG. 2 is a cross-sectional side view showing substrate surface 20, silicon layer 22, silicon dioxide layer 24, and silicon layer 26. Referring now to FIG. 3, a layer of dielectric material 28 is formed on substrate surface 20 and a dielectric material 30 is formed on dielectric material 28. By way of example, dielectric material 28 is silicon dioxide layer and dielectric material 30 is silicon nitride. Silicon dioxide layer 28 cooperates with silicon nitride layer 30 to form a gate dielectric material 32.
• Silicon dioxide layer 28 and silicon nitride layer 30 may be formed by techniques known to those skilled in the art including thermal oxidation, chemical vapor deposition, and the like.
• gate dielectric material 32 has a thickness ranging from approximately 0.8 nm to approximately 2.0 nm. Even more preferably, gate dielectric material 32 has a thickness of approximately 1.3 nm. It should be understood that gate dielectric material 32 is not limited to being two layers of dielectric material or a layer of silicon nitride disposed on a layer of silicon dioxide.
• gate dielectric material 32 may be comprised of a material having a high dielectric constant (K), e.g., greater than 3.9, a single layer of oxide, or a combination thereof.
• K dielectric constant
• a layer of polysilicon 34 is formed on gate dielectric material 32 using, for example, a chemical vapor deposition technique.
• a suitable range of thicknesses for polysilicon layer 34 is between approximately 1 nm and approximately 2 nm.
• a layer of photoresist is deposited on polysilicon layer 34 and patterned to form etch mask 36.
• polysilicon layer 34 is etched using an etch chemistry that preferentially etches polysilicon, i.e., an etch chemistry selective to photoresist etch mask 36.
• polysilicon layer 34 is etched using an anisotropic Reactive Ion Etch (RIE) and an etchant species that is selective to photoresist.
• RIE anisotropic Reactive Ion Etch
• gate dielectric material 32 i.e., silicon dioxide layer 28 and silicon nitride layer 30, may be anisotropically etched after etching polysilicon layer 34. Methods for etching polysilicon and gate dielectric material are well known to those skilled in the art. Etch mask 36 is removed. The remaining portion 38 of polysilicon layer 34 serves as the gate for semiconductor device 10. The portion 40 of gate dielectric material 32 between gate 38 and substrate 22 serves as a gate dielectric. Gate 38 and gate dielectric 40 cooperate to form a gate structure 42. Gate structure 42 has a gate surface 44 and opposing sidewalls 46 and 47. Briefly referring to FIG. 5, a cross-sectional view taken along section line 5-5 of FIG. 4 is shown. What is shown in FIG.
• silicon layer 22 is silicon dioxide layer 24, and silicon layer 26 of mesa isolation structure 14.
• sidewalls 16 and 18 extend under silicon layer 22 because portions of silicon dioxide 24 layer have been etched during the manufacture of semiconductor device 10.
• silicon dioxide layer 24 may be etched during the cleaning steps performed in preparation for forming polysilicon layer 34. This etching, also referred to as underetching, can be controlled such that a predetermined amount of silicon dioxide layer 24 is underetched.
• the amount of silicon dioxide layer 24 that is etched from each side i.e., from sidewalls 16 and 18, ranges between approximately 10 nm and approximately 30 nm. Even more preferably, the amount of silicon dioxide layer 24 that is etched from each side is approximately 20 nm.
• gate dielectric material 32 wraps around opposing sides 48 and 49 of silicon layer 22.
• polysilicon layer 34 wraps around the portions of gate dielectric 40 that are adjacent opposing sides 48 and 49.
• a layer of silicon dioxide 50 having a thickness ranging between approximately 2.5 nm and approximately 10 nm is formed on gate 38 and on silicon nitride layer 30.
• a layer of silicon nitride 52 having a thickness ranging between approximately 5 nm and approximately 50 nm is formed on silicon dioxide layer 50.
• silicon dioxide layer 50 has a thickness of 5 nm and silicon nitride layer 52 has a thickness of 30 nm.
• silicon nitride layer 52 and silicon dioxide layer 50 are etched using anisotropic reactive ion etching. After the anisotropic etching, a portion 54 of silicon dioxide layer 50 and a portion 56 of silicon nitride layer 52 remain over gate structure 42 and the portions of silicon layer 22 adjacent gate structure 42. It should be noted that if gate dielectric material 32 was not anisotropically etched after the formation of gate 38 as described with reference to FIG. 4, gate dielectric material 32 may be anisotropically etched after anisotropically etching silicon nitride layer 52 and silicon dioxide layer 50. A layer of silicon 58 having a surface 60 and a thickness ranging between approximately 15 nm and approximately 45 nm is grown on the exposed portions of silicon layer 22.
• silicon layer 58 is grown using a technique of selective epitaxial growth. It should be understood that silicon layer 58 is not limited to being silicon, but can be any suitable semiconductor material such as, for example, silicon germanium or germanium.
• An impurity material of N type conductivity such as, for example, arsenic or phosphorus, is implanted into silicon layer 58 to form doped regions 62 and 64 that serve as source and drain extension regions, respectively.
• source extension region 62 extends under gate structure 42 from gate side 46 and drain extension region 64 extends under gate structure 42 from gate side 47. Extension regions 62 and 64 may extend into dielectric layer 24.
• extension regions 62 and 64 have a concentration ranging from approximately lxlO 18 atoms per centimeter cubed (atoms/cm 3 ) to approximately 5xl0 20 atoms/cm 3 .
• extension regions 62 and 64 are formed by using a tilt angle implant having a tilt angle that ranges between approximately 7 degrees and approximately 45 degrees, where the angle is formed between surface 60 and an imaginary line extending perpendicularly from surface 60.
• Suitable implant parameters for forming source and drain extension regions 62 and 64 include an implant dose ranging between approximately 10 12 ions per centimeter squared (ions/cm 2 ) and approximately 10 ions/cm and an implant energy ranging between approximately 1 kilo electron volt (keV) and approximately 20 keV.
• semiconductor device 10 is annealed.
• source and drain extension regions 62 and 64, respectively are formed using an angled or tilt angle implant, it should be understood that the implant may implant other portions of silicon layers 58 and 72 than those under gate structure 42.
• a source/drain implant is performed to form a source region 72 and a drain region 74.
• the source/drain implant may also dope gate structure 42.
• a suitable set of parameters for the source/drain implant includes implanting an N type impurity material such as, for example, arsenic at a dose ranging between approximately lxlO 14 ions/cm 2 and approximately lxlO 16 ions/cm 2 and using an implant energy ranging between approximately 20 keV and approximately 50 keV.
• the doped semiconductor material is annealed by heating to a temperature between approximately 800 degrees Celsius (°C) and 1,100 °C.
• a layer of refractory metal 76 is conformally deposited on silicon surface 60 and portion 56 of silicon nitride layer 52.
• the metal of refractory metal layer 76 is nickel having a thickness ranging between approximately 50 A and approximately 150 A.
• the refractory metal is heated to a temperature ranging between 350 °C and 500 °C.
• the heat treatment causes the nickel to react with the silicon to form nickel silicide (NiSi) in all regions in which the nickel is in contact with silicon.
• a nickel silicide region 82 is formed in source region 72 and a nickel silicide region 84 is formed in drain region 74.
• the portions of the nickel adjacent portion 56 of nitride layer 52 remain unreacted. After formation of nickel silicide regions 82 and 84, any unreacted nickel silicide is removed. It should be understood that the type of silicide is not a limitation of the present invention.
• Suitable suicides include titanium silicide (TiSi), platinum silicide (PtSi), cobalt silicide (CoSi 2 ), and the like.
• silicon is consumed during the formation of silicide and the amount of silicon consumed is a function of the type of silicide being formed.
• a layer of dielectric material 88 having a thickness ranging between approximately 500 A and approximately 2,500 A is formed on dielectric layer 86.
• dielectric material 86 is silicon oxynitride having a thickness of approximately 500 A and dielectric layer 88 is oxide formed by decomposition of tetraethylorthosilicate (TEOS) having a thickness of approximately 1,500 A.
• TEOS layer 88 is planarized using, for example, a Chemical Mechanical Polishing (CMP) technique having a high selectivity to polysilicon.
• CMP Chemical Mechanical Polishing
• a layer of refractory metal 90 is conformally deposited on silicon surface 44, TEOS layer 88, the exposed portions of silicon oxynitride layer 86 and the exposed portions of silicon dioxide layer 54 and silicon nitride layer 56.
• the metal of refractory metal layer 90 is nickel having a thickness of approximately 700 A.
• the refractory metal is heated to a temperature ranging between approximately 350 °C and 500 °C.
• the heat treatment causes the nickel to react with the silicon to form nickel silicide (NiSi) in all regions in which the nickel is in contact with silicon.
• a nickel silicide region 92 is formed from gate 38.
• the portions of the nickel disposed on non-silicon regions, i.e., TEOS layer 88, the exposed portions of SiON layer 86, and exposed portions of silicon dioxide layer 54 and silicon nitride layer 56 remain unreacted.
• any unreacted nickel silicide is removed.
• the type of silicide is not a limitation of the present invention.
• other suitable suicides include titanium silicide (TiSi), platinum silicide (PtSi), cobalt silicide (CoSi 2 ), and the like.
• silicon is consumed during the formation of silicide and the amount of silicon consumed is a function of the type of silicide being formed.
• FIG. 11 a cross-sectional side view of semiconductor device 10 along section line
• FIG. 11 is illustrated. What is shown in FIG. 11 is silicon layer 22 disposed on dielectric layer 24, which is disposed on body of semiconductor material 26.
• Gate dielectric 40 which is comprised of silicon dioxide layer 28 and silicon nitride layer 30, wraps around opposing sides 48 and 49 of silicon layer 22.
• nickel silicide region 92 of gate 38 wraps around the portions of gate dielectric 40 that are adjacent opposing sides 48 and 49.
• the semiconductor device can include one of these techniques or a combination of more than one of these techniques to provide stress.
• either the electron mobility, the hole mobility or the mobility of both the electrons and the holes can be optimized.
• the increased mobility results in increased device performance.
• NMOS and PMOS transistors manufactured in accordance with an embodiment of the present invention have CV/I delays as small as 0.2 picoseconds (ps) and 0.3 ps, respectively.
• Another advantage of the present invention is that the strain is defined at the last higher temperature processing step which helps prevent subsequent relaxation.
• the high mobility increases the drive current of the device, while the quantization effects in such an ultra-thin semiconductor-on-insulator device increases its threshold voltage, thereby improving the offset current.

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• Engineering & Computer Science (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
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• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Thin Film Transistor (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Element Separation (AREA)
• Electrodes Of Semiconductors (AREA)

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• 2003
  • 2003-06-23 US US10/601,401 patent/US6913959B2/en not_active Expired - Fee Related
• 2004
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  • 2004-06-05 CN CNB2004800176215A patent/CN100521231C/zh not_active Expired - Fee Related
  • 2004-06-05 JP JP2006517180A patent/JP2007519217A/ja active Pending
  • 2004-06-05 WO PCT/US2004/017727 patent/WO2005001908A2/en not_active Ceased
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