JP2006173432A5 - - Google Patents
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- Publication number
- JP2006173432A5 JP2006173432A5 JP2004365581A JP2004365581A JP2006173432A5 JP 2006173432 A5 JP2006173432 A5 JP 2006173432A5 JP 2004365581 A JP2004365581 A JP 2004365581A JP 2004365581 A JP2004365581 A JP 2004365581A JP 2006173432 A5 JP2006173432 A5 JP 2006173432A5
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- forming
- active region
- diffusion layer
- stress control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 13
- 238000009792 diffusion process Methods 0.000 claims 11
- 239000000758 substrate Substances 0.000 claims 8
- 238000005530 etching Methods 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 claims 2
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004365581A JP5002891B2 (ja) | 2004-12-17 | 2004-12-17 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004365581A JP5002891B2 (ja) | 2004-12-17 | 2004-12-17 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006173432A JP2006173432A (ja) | 2006-06-29 |
| JP2006173432A5 true JP2006173432A5 (enExample) | 2008-01-17 |
| JP5002891B2 JP5002891B2 (ja) | 2012-08-15 |
Family
ID=36673833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004365581A Expired - Fee Related JP5002891B2 (ja) | 2004-12-17 | 2004-12-17 | 半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5002891B2 (enExample) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7101744B1 (en) * | 2005-03-01 | 2006-09-05 | International Business Machines Corporation | Method for forming self-aligned, dual silicon nitride liner for CMOS devices |
| US7569888B2 (en) * | 2005-08-10 | 2009-08-04 | Toshiba America Electronic Components, Inc. | Semiconductor device with close stress liner film and method of manufacturing the same |
| US7709317B2 (en) * | 2005-11-14 | 2010-05-04 | International Business Machines Corporation | Method to increase strain enhancement with spacerless FET and dual liner process |
| JP4899085B2 (ja) | 2006-03-03 | 2012-03-21 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
| US7521307B2 (en) * | 2006-04-28 | 2009-04-21 | International Business Machines Corporation | CMOS structures and methods using self-aligned dual stressed layers |
| US7585720B2 (en) * | 2006-07-05 | 2009-09-08 | Toshiba America Electronic Components, Inc. | Dual stress liner device and method |
| JP5114892B2 (ja) * | 2006-08-25 | 2013-01-09 | ソニー株式会社 | 半導体装置 |
| US7462522B2 (en) * | 2006-08-30 | 2008-12-09 | International Business Machines Corporation | Method and structure for improving device performance variation in dual stress liner technology |
| JP2008071851A (ja) * | 2006-09-13 | 2008-03-27 | Sony Corp | 半導体装置および半導体装置の製造方法 |
| KR100809335B1 (ko) | 2006-09-28 | 2008-03-05 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
| JP2008091536A (ja) | 2006-09-29 | 2008-04-17 | Toshiba Corp | 半導体装置及びその製造方法 |
| JP2008103607A (ja) * | 2006-10-20 | 2008-05-01 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| US7585773B2 (en) * | 2006-11-03 | 2009-09-08 | International Business Machines Corporation | Non-conformal stress liner for enhanced MOSFET performance |
| US7476610B2 (en) * | 2006-11-10 | 2009-01-13 | Lam Research Corporation | Removable spacer |
| US20080116521A1 (en) | 2006-11-16 | 2008-05-22 | Samsung Electronics Co., Ltd | CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same |
| JP5132943B2 (ja) * | 2007-01-24 | 2013-01-30 | パナソニック株式会社 | 半導体装置 |
| JP4504392B2 (ja) | 2007-03-15 | 2010-07-14 | 株式会社東芝 | 半導体装置 |
| US7534678B2 (en) | 2007-03-27 | 2009-05-19 | Samsung Electronics Co., Ltd. | Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby |
| JP5299268B2 (ja) * | 2007-03-30 | 2013-09-25 | 富士通セミコンダクター株式会社 | 半導体集積回路装置およびその製造方法 |
| US7902082B2 (en) | 2007-09-20 | 2011-03-08 | Samsung Electronics Co., Ltd. | Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers |
| US7923365B2 (en) | 2007-10-17 | 2011-04-12 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon |
| JP2009130009A (ja) | 2007-11-21 | 2009-06-11 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| JP2010212388A (ja) | 2009-03-10 | 2010-09-24 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
| CN103178011A (zh) * | 2011-12-22 | 2013-06-26 | 中芯国际集成电路制造(上海)有限公司 | Cmos及其形成方法 |
| JP5712984B2 (ja) * | 2012-08-27 | 2015-05-07 | ソニー株式会社 | 半導体装置 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4173672B2 (ja) * | 2002-03-19 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
| JP4406200B2 (ja) * | 2002-12-06 | 2010-01-27 | 株式会社東芝 | 半導体装置 |
-
2004
- 2004-12-17 JP JP2004365581A patent/JP5002891B2/ja not_active Expired - Fee Related
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