JP5002891B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP5002891B2
JP5002891B2 JP2004365581A JP2004365581A JP5002891B2 JP 5002891 B2 JP5002891 B2 JP 5002891B2 JP 2004365581 A JP2004365581 A JP 2004365581A JP 2004365581 A JP2004365581 A JP 2004365581A JP 5002891 B2 JP5002891 B2 JP 5002891B2
Authority
JP
Japan
Prior art keywords
gate electrode
film
region
gate
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004365581A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006173432A (ja
JP2006173432A5 (enExample
Inventor
セルゲイ ピディン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to JP2004365581A priority Critical patent/JP5002891B2/ja
Publication of JP2006173432A publication Critical patent/JP2006173432A/ja
Publication of JP2006173432A5 publication Critical patent/JP2006173432A5/ja
Application granted granted Critical
Publication of JP5002891B2 publication Critical patent/JP5002891B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2004365581A 2004-12-17 2004-12-17 半導体装置の製造方法 Expired - Fee Related JP5002891B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004365581A JP5002891B2 (ja) 2004-12-17 2004-12-17 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004365581A JP5002891B2 (ja) 2004-12-17 2004-12-17 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2006173432A JP2006173432A (ja) 2006-06-29
JP2006173432A5 JP2006173432A5 (enExample) 2008-01-17
JP5002891B2 true JP5002891B2 (ja) 2012-08-15

Family

ID=36673833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004365581A Expired - Fee Related JP5002891B2 (ja) 2004-12-17 2004-12-17 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP5002891B2 (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7101744B1 (en) * 2005-03-01 2006-09-05 International Business Machines Corporation Method for forming self-aligned, dual silicon nitride liner for CMOS devices
US7569888B2 (en) * 2005-08-10 2009-08-04 Toshiba America Electronic Components, Inc. Semiconductor device with close stress liner film and method of manufacturing the same
US7709317B2 (en) * 2005-11-14 2010-05-04 International Business Machines Corporation Method to increase strain enhancement with spacerless FET and dual liner process
JP4899085B2 (ja) 2006-03-03 2012-03-21 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7521307B2 (en) * 2006-04-28 2009-04-21 International Business Machines Corporation CMOS structures and methods using self-aligned dual stressed layers
US7585720B2 (en) 2006-07-05 2009-09-08 Toshiba America Electronic Components, Inc. Dual stress liner device and method
JP5114892B2 (ja) * 2006-08-25 2013-01-09 ソニー株式会社 半導体装置
US7462522B2 (en) * 2006-08-30 2008-12-09 International Business Machines Corporation Method and structure for improving device performance variation in dual stress liner technology
JP2008071851A (ja) * 2006-09-13 2008-03-27 Sony Corp 半導体装置および半導体装置の製造方法
KR100809335B1 (ko) 2006-09-28 2008-03-05 삼성전자주식회사 반도체 소자 및 이의 제조 방법
JP2008091536A (ja) 2006-09-29 2008-04-17 Toshiba Corp 半導体装置及びその製造方法
JP2008103607A (ja) * 2006-10-20 2008-05-01 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7585773B2 (en) * 2006-11-03 2009-09-08 International Business Machines Corporation Non-conformal stress liner for enhanced MOSFET performance
US7476610B2 (en) * 2006-11-10 2009-01-13 Lam Research Corporation Removable spacer
US20080116521A1 (en) 2006-11-16 2008-05-22 Samsung Electronics Co., Ltd CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same
JP5132943B2 (ja) * 2007-01-24 2013-01-30 パナソニック株式会社 半導体装置
JP4504392B2 (ja) 2007-03-15 2010-07-14 株式会社東芝 半導体装置
US7534678B2 (en) 2007-03-27 2009-05-19 Samsung Electronics Co., Ltd. Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby
CN101641778B (zh) 2007-03-30 2014-12-17 富士通半导体股份有限公司 半导体集成电路装置
US7902082B2 (en) 2007-09-20 2011-03-08 Samsung Electronics Co., Ltd. Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers
US7923365B2 (en) 2007-10-17 2011-04-12 Samsung Electronics Co., Ltd. Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon
JP2009130009A (ja) 2007-11-21 2009-06-11 Renesas Technology Corp 半導体装置およびその製造方法
JP2010212388A (ja) 2009-03-10 2010-09-24 Renesas Electronics Corp 半導体装置およびその製造方法
CN103178011A (zh) * 2011-12-22 2013-06-26 中芯国际集成电路制造(上海)有限公司 Cmos及其形成方法
JP5712984B2 (ja) * 2012-08-27 2015-05-07 ソニー株式会社 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4173672B2 (ja) * 2002-03-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP4406200B2 (ja) * 2002-12-06 2010-01-27 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
JP2006173432A (ja) 2006-06-29

Similar Documents

Publication Publication Date Title
JP5002891B2 (ja) 半導体装置の製造方法
US7262472B2 (en) Semiconductor device having stress and its manufacture method
US8994116B2 (en) Hybrid gate process for fabricating FinFET device
JP4384988B2 (ja) 歪みＦｉｎＦＥＴＣＭＯＳデバイス構造
CN113690141B (zh) 制造半导体器件的方法和半导体器件
CN102637739B (zh) 具有张应力增加的绝缘膜的半导体器件及其制造方法
TWI437707B (zh) 半導體裝置及其製造方法
JP4982958B2 (ja) 半導体装置とその製造方法
CN103247672B (zh) 半导体器件及其制造方法
TWI878746B (zh) 金屬閘極鰭片電極結構及其形成方法
KR20210098832A (ko) 문턱 전압을 조정하기 위한 신규한 게이트 구조물
JP2010267814A (ja) 半導体装置及びその製造方法
JP2009026997A (ja) 半導体装置およびその製造方法
TWI854640B (zh) 奈米結構場效電晶體及其製造方法
TW202240894A (zh) 半導體裝置及其製造方法
CN114649268A (zh) 半导体器件及方法
TWI860699B (zh) 半導體裝置以及其形成之方法
KR20220050019A (ko) 반도체 디바이스의 콘택 플러그 구조물 및 그 형성 방법
CN113488387A (zh) 多层掩模层及其形成方法
US12426324B2 (en) Gates structures of nanostructure field-effect transistors (nano-FETs) including a plurality of semiconductor based capping materials and methods of forming the same
JP2009033173A (ja) 半導体素子およびその製造方法
TWI789779B (zh) 電晶體及形成源極/汲極區域的方法
JP3518059B2 (ja) Ｍｉｓ型トランジスタの製造方法
TW202238837A (zh) 半導體裝置的製造方法
TWI442511B (zh) 半導體裝置中之分層形成

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071122

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071122

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20080731

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100208

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100223

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100421

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110524

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110719

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20111220

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120316

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20120326

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120424

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120507

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150601

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5002891

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees