JP2007507092A5 - - Google Patents

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Publication number
JP2007507092A5
JP2007507092A5 JP2006526936A JP2006526936A JP2007507092A5 JP 2007507092 A5 JP2007507092 A5 JP 2007507092A5 JP 2006526936 A JP2006526936 A JP 2006526936A JP 2006526936 A JP2006526936 A JP 2006526936A JP 2007507092 A5 JP2007507092 A5 JP 2007507092A5
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JP
Japan
Prior art keywords
forming
current electrode
semiconductor substrate
layer
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006526936A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007507092A (ja
JP5068074B2 (ja
Filing date
Publication date
Priority claimed from US10/668,714 external-priority patent/US6964911B2/en
Application filed filed Critical
Publication of JP2007507092A publication Critical patent/JP2007507092A/ja
Publication of JP2007507092A5 publication Critical patent/JP2007507092A5/ja
Application granted granted Critical
Publication of JP5068074B2 publication Critical patent/JP5068074B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2006526936A 2003-09-23 2004-09-10 分離領域を有する半導体デバイスを形成するための方法 Expired - Fee Related JP5068074B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/668,714 US6964911B2 (en) 2003-09-23 2003-09-23 Method for forming a semiconductor device having isolation regions
US10/668,714 2003-09-23
PCT/US2004/029381 WO2005034186A2 (en) 2003-09-23 2004-09-10 Method for forming a semiconductor device having isolation regions

Publications (3)

Publication Number Publication Date
JP2007507092A JP2007507092A (ja) 2007-03-22
JP2007507092A5 true JP2007507092A5 (enExample) 2007-10-18
JP5068074B2 JP5068074B2 (ja) 2012-11-07

Family

ID=34313551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006526936A Expired - Fee Related JP5068074B2 (ja) 2003-09-23 2004-09-10 分離領域を有する半導体デバイスを形成するための方法

Country Status (7)

Country Link
US (1) US6964911B2 (enExample)
EP (1) EP1668691A2 (enExample)
JP (1) JP5068074B2 (enExample)
KR (1) KR101120770B1 (enExample)
CN (1) CN1846304B (enExample)
TW (1) TWI364813B (enExample)
WO (1) WO2005034186A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040242015A1 (en) * 2003-03-04 2004-12-02 Kyoung-Chul Kim Etching compositions for silicon germanium and etching methods using the same
KR100583725B1 (ko) * 2003-11-07 2006-05-25 삼성전자주식회사 부분적으로 절연된 전계효과 트랜지스터를 구비하는반도체 장치 및 그 제조 방법
KR100598098B1 (ko) * 2004-02-06 2006-07-07 삼성전자주식회사 매몰 절연 영역을 갖는 모오스 전계 효과 트랜지스터 및그 제조 방법
US7256077B2 (en) * 2004-05-21 2007-08-14 Freescale Semiconductor, Inc. Method for removing a semiconductor layer
KR100555569B1 (ko) * 2004-08-06 2006-03-03 삼성전자주식회사 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법
WO2006030505A1 (ja) * 2004-09-16 2006-03-23 Fujitsu Limited Ｍｏｓ型電界効果トランジスタ及びその製造方法
US20070194353A1 (en) * 2005-08-31 2007-08-23 Snyder John P Metal source/drain Schottky barrier silicon-on-nothing MOSFET device and method thereof
US7326601B2 (en) * 2005-09-26 2008-02-05 Advanced Micro Devices, Inc. Methods for fabrication of a stressed MOS device
JP2007165677A (ja) * 2005-12-15 2007-06-28 Seiko Epson Corp 半導体基板の製造方法及び半導体装置
JP2007201003A (ja) * 2006-01-24 2007-08-09 Seiko Epson Corp 半導体基板の製造方法及び半導体装置の製造方法、半導体装置
JP2007207960A (ja) * 2006-02-01 2007-08-16 Seiko Epson Corp 半導体基板、半導体基板の製造方法及び半導体装置
FR2901058A1 (fr) * 2006-08-29 2007-11-16 St Microelectronics Crolles 2 Dispositif a fonction dissymetrique et procede de realisation correspondant.
US7521314B2 (en) * 2007-04-20 2009-04-21 Freescale Semiconductor, Inc. Method for selective removal of a layer
US8866254B2 (en) * 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US20120146175A1 (en) * 2010-12-09 2012-06-14 Nicolas Loubet Insulating region for a semiconductor substrate
US9196522B2 (en) 2013-10-16 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with buried insulator layer and method for forming

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077773B2 (ja) * 1989-03-01 1995-01-30 工業技術院長 半導体装置の製造方法
JPH0521465A (ja) * 1991-07-10 1993-01-29 Fujitsu Ltd 半導体装置及びその製造方法
FR2749977B1 (fr) * 1996-06-14 1998-10-09 Commissariat Energie Atomique Transistor mos a puits quantique et procedes de fabrication de celui-ci
US6043126A (en) * 1996-10-25 2000-03-28 International Rectifier Corporation Process for manufacture of MOS gated device with self aligned cells
US6015917A (en) * 1998-01-23 2000-01-18 Advanced Technology Materials, Inc. Tantalum amide precursors for deposition of tantalum nitride on a substrate
FR2799307B1 (fr) * 1999-10-01 2002-02-15 France Telecom Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication
US6352903B1 (en) * 2000-06-28 2002-03-05 International Business Machines Corporation Junction isolation
FR2812764B1 (fr) * 2000-08-02 2003-01-24 St Microelectronics Sa Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu
FR2821483B1 (fr) * 2001-02-28 2004-07-09 St Microelectronics Sa Procede de fabrication d'un transistor a grille isolee et a architecture du type substrat sur isolant, et transistor correspondant
US6551937B2 (en) * 2001-08-23 2003-04-22 Institute Of Microelectronics Process for device using partial SOI
CN1253942C (zh) * 2002-02-20 2006-04-26 台湾积体电路制造股份有限公司 可避免产生漏电流的mos管结构及具有该结构的cmos影像管
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置

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