JP5068074B2 - 分離領域を有する半導体デバイスを形成するための方法 - Google Patents
分離領域を有する半導体デバイスを形成するための方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 134
- 238000002955 isolation Methods 0.000 title claims description 52
- 238000000034 method Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 description 22
- 125000006850 spacer group Chemical group 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000008901 benefit Effects 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000000149 penetrating effect Effects 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000009417 prefabrication Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Description
本発明は例示であり、添付の図面によって制限されない。なお、添付の図面では、類似の参照番号は類似の構成要素を指している。
図1は半導体デバイス10の断面を示しており、半導体デバイス10内に分離領域14が形成され、半導体デバイス10上に第1の半導体層16及び第2の半導体層18が形成されている。好ましい実施形態では、半導体デバイス10はシリコンであるが、半導体デバイス10には、シリコンゲルマニウム、ガリウムヒ素等、及び上記の材料の組み合わせを用いることができる。分離領域14は、従来の方法を用いて形成される、浅いトレンチ分離(STI)領域にすることができる。図1に示される実施形態では、分離領域14は、半導体基板12の上側表面と同一平面を成す。別の実施形態では、分離領域14は半導体基板12の上側表面よりも高い。
有することが望ましい。第2の半導体層18には任意の半導体材料を用いることができるが、結晶性であることが好ましい。
、半導体デバイス10の複数の部分において、ゲート電極22並びに窒化物スペーサ24及び誘電体スペーサ26によって支持され、それは図3には示されないが、図4に示される。図4は、紙面に対して垂直な(すなわち紙面に対して出入りする)方向の図3の断面図である。したがって、図3及び図4の構造は互いに対して垂直である。
できる。ドライ酸化、ウエット酸化又は2つの組み合わせを実行して、電流電極誘電体分離構造36を形成することができる。
つの分離領域を有する半導体デバイスを形成するための方法が提供されてきたことは理解されたい。一実施形態では、その半導体デバイスは分離されたトランジスタである。電流電極誘電体分離構造36は、半導体基板12を通る、電流電極40間の漏れ経路を防ぐか、又は最小限に抑える。隙間28内にある第2の誘電体層30、窒化物層32及び第3の誘電体層34は、チャネル内の電流の漏れを防ぐか、又は最小限に抑える。
Claims (3)
- 半導体基板上に第1の半導体層、第2の半導体層、第1の誘電体層、及び制御電極層を形成する工程と、
前記制御電極層をパターニングして制御電極構造を形成する工程と、
前記制御電極構造に側壁を設ける工程と、
前記制御電極構造と前記側壁をマスクとして用いることによって、前記第1の誘電体層、前記第2の半導体層、及び前記第1の半導体層をエッチングする工程と、
前記第1の半導体層を前記半導体基板及び前記第2の半導体層に対して選択的にエッチングすることによって、前記制御電極構造を有するデバイス構造においてチャネル構造の役割を果たす前記第2の半導体層を前記半導体基板から空間によって離隔する工程と、
前記チャネル構造と前記半導体基板との間にチャネル分離層を堆積する工程と、
前記チャネル構造から前記チャネル構造に流れる電流と平行な方向に配置される電流電極誘電体分離構造を形成する工程と、
前記電流電極誘電体分離構造上に電流電極構造を堆積する工程とを備える、分離されたトランジスタの製造方法。 - 前記第1の半導体層を形成する工程は、シリコンゲルマニウムを形成する工程からなり、
前記第2の半導体層を形成する工程は、シリコンを形成する工程からなり、
前記第1の誘電体層を形成する工程は、二酸化シリコンを形成する工程からなる、請求項1に記載の分離されたトランジスタの製造方法。 - 基板上に第1の半導体層、第2の半導体層、第1の誘電体層、及び制御電極層を形成する工程と、
前記制御電極層をパターニングして制御電極構造を形成する工程と、
前記制御電極構造に側壁を設ける工程と、
前記制御電極構造と前記側壁をマスクとして用いることによって、前記第1の誘電体層、前記第2の半導体層、及び前記第1の半導体層をエッチングする工程と、
前記第1の半導体層を前記基板及び前記第2の半導体層に対して選択的にエッチングすることによって、前記制御電極構造を有するデバイス構造においてチャネル構造の役割を果たす前記第2の半導体層を前記基板から空間によって離隔する工程と、
前記チャネル構造の下に設けられた前記空間にチャネル分離構造を形成する工程と、
前記チャネル構造から前記チャネル構造に流れる電流と平行な方向に配置される第1及び第2の電流電極領域のそれぞれにおいて前記基板内に電流電極分離構造を形成する工程であって、前記チャネル分離構造及び前記電流電極分離構造は隣接するように形成される、電流電極分離構造形成工程と、
前記電流電極分離構造のそれぞれの上に電流電極を前記チャネル構造からエピタキシャル成長させる工程とからなる、分離されたトランジスタの製造方法。
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Application Number | Priority Date | Filing Date | Title |
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US10/668,714 | 2003-09-23 | ||
US10/668,714 US6964911B2 (en) | 2003-09-23 | 2003-09-23 | Method for forming a semiconductor device having isolation regions |
PCT/US2004/029381 WO2005034186A2 (en) | 2003-09-23 | 2004-09-10 | Method for forming a semiconductor device having isolation regions |
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JP2007507092A JP2007507092A (ja) | 2007-03-22 |
JP2007507092A5 JP2007507092A5 (ja) | 2007-10-18 |
JP5068074B2 true JP5068074B2 (ja) | 2012-11-07 |
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US (1) | US6964911B2 (ja) |
EP (1) | EP1668691A2 (ja) |
JP (1) | JP5068074B2 (ja) |
KR (1) | KR101120770B1 (ja) |
CN (1) | CN1846304B (ja) |
TW (1) | TWI364813B (ja) |
WO (1) | WO2005034186A2 (ja) |
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US20040242015A1 (en) * | 2003-03-04 | 2004-12-02 | Kyoung-Chul Kim | Etching compositions for silicon germanium and etching methods using the same |
KR100583725B1 (ko) * | 2003-11-07 | 2006-05-25 | 삼성전자주식회사 | 부분적으로 절연된 전계효과 트랜지스터를 구비하는반도체 장치 및 그 제조 방법 |
KR100598098B1 (ko) * | 2004-02-06 | 2006-07-07 | 삼성전자주식회사 | 매몰 절연 영역을 갖는 모오스 전계 효과 트랜지스터 및그 제조 방법 |
US7256077B2 (en) * | 2004-05-21 | 2007-08-14 | Freescale Semiconductor, Inc. | Method for removing a semiconductor layer |
KR100555569B1 (ko) * | 2004-08-06 | 2006-03-03 | 삼성전자주식회사 | 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법 |
JP4888118B2 (ja) * | 2004-09-16 | 2012-02-29 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法及び半導体装置 |
US20070194353A1 (en) * | 2005-08-31 | 2007-08-23 | Snyder John P | Metal source/drain Schottky barrier silicon-on-nothing MOSFET device and method thereof |
US7326601B2 (en) * | 2005-09-26 | 2008-02-05 | Advanced Micro Devices, Inc. | Methods for fabrication of a stressed MOS device |
JP2007165677A (ja) * | 2005-12-15 | 2007-06-28 | Seiko Epson Corp | 半導体基板の製造方法及び半導体装置 |
JP2007201003A (ja) * | 2006-01-24 | 2007-08-09 | Seiko Epson Corp | 半導体基板の製造方法及び半導体装置の製造方法、半導体装置 |
JP2007207960A (ja) * | 2006-02-01 | 2007-08-16 | Seiko Epson Corp | 半導体基板、半導体基板の製造方法及び半導体装置 |
FR2901058A1 (fr) * | 2006-08-29 | 2007-11-16 | St Microelectronics Crolles 2 | Dispositif a fonction dissymetrique et procede de realisation correspondant. |
US7521314B2 (en) * | 2007-04-20 | 2009-04-21 | Freescale Semiconductor, Inc. | Method for selective removal of a layer |
US8866254B2 (en) * | 2008-02-19 | 2014-10-21 | Micron Technology, Inc. | Devices including fin transistors robust to gate shorts and methods of making the same |
US20120146175A1 (en) * | 2010-12-09 | 2012-06-14 | Nicolas Loubet | Insulating region for a semiconductor substrate |
US9196522B2 (en) | 2013-10-16 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with buried insulator layer and method for forming |
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FR2799307B1 (fr) * | 1999-10-01 | 2002-02-15 | France Telecom | Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication |
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FR2812764B1 (fr) * | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu |
FR2821483B1 (fr) * | 2001-02-28 | 2004-07-09 | St Microelectronics Sa | Procede de fabrication d'un transistor a grille isolee et a architecture du type substrat sur isolant, et transistor correspondant |
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- 2004-09-10 WO PCT/US2004/029381 patent/WO2005034186A2/en active Application Filing
- 2004-09-10 EP EP04809709A patent/EP1668691A2/en not_active Withdrawn
- 2004-09-10 CN CN2004800250641A patent/CN1846304B/zh not_active Expired - Fee Related
- 2004-09-10 KR KR1020067005642A patent/KR101120770B1/ko not_active IP Right Cessation
- 2004-09-10 JP JP2006526936A patent/JP5068074B2/ja not_active Expired - Fee Related
- 2004-09-22 TW TW093128719A patent/TWI364813B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN1846304B (zh) | 2012-01-11 |
US6964911B2 (en) | 2005-11-15 |
WO2005034186A2 (en) | 2005-04-14 |
JP2007507092A (ja) | 2007-03-22 |
KR20060121883A (ko) | 2006-11-29 |
WO2005034186A3 (en) | 2005-11-03 |
US20050064669A1 (en) | 2005-03-24 |
TWI364813B (en) | 2012-05-21 |
CN1846304A (zh) | 2006-10-11 |
KR101120770B1 (ko) | 2012-03-23 |
TW200520146A (en) | 2005-06-16 |
EP1668691A2 (en) | 2006-06-14 |
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