TW200520146A - Method for forming a semiconductor device having isolation regions - Google Patents
Method for forming a semiconductor device having isolation regionsInfo
- Publication number
- TW200520146A TW200520146A TW093128719A TW93128719A TW200520146A TW 200520146 A TW200520146 A TW 200520146A TW 093128719 A TW093128719 A TW 093128719A TW 93128719 A TW93128719 A TW 93128719A TW 200520146 A TW200520146 A TW 200520146A
- Authority
- TW
- Taiwan
- Prior art keywords
- forming
- semiconductor device
- current
- isolation regions
- isolation
- Prior art date
Links
- 238000002955 isolation Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000007423 decrease Effects 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Abstract
A method for forming a semiconductor device (10) having isolation structures decreases leakage current. A channel isolation structure (32,30, 34) decreases leakage current through a channel structure. In addition, current electrode dielectric insulation structures (36) are formed under current electrode regions to prevent leakage between the current electrodes (40).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/668,714 US6964911B2 (en) | 2003-09-23 | 2003-09-23 | Method for forming a semiconductor device having isolation regions |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200520146A true TW200520146A (en) | 2005-06-16 |
TWI364813B TWI364813B (en) | 2012-05-21 |
Family
ID=34313551
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093128719A TWI364813B (en) | 2003-09-23 | 2004-09-22 | Method for forming a semiconductor device having isolation regions |
Country Status (7)
Country | Link |
---|---|
US (1) | US6964911B2 (en) |
EP (1) | EP1668691A2 (en) |
JP (1) | JP5068074B2 (en) |
KR (1) | KR101120770B1 (en) |
CN (1) | CN1846304B (en) |
TW (1) | TWI364813B (en) |
WO (1) | WO2005034186A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI450334B (en) * | 2007-04-20 | 2014-08-21 | Freescale Semiconductor Inc | Method for selective removal of a layer |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040242015A1 (en) * | 2003-03-04 | 2004-12-02 | Kyoung-Chul Kim | Etching compositions for silicon germanium and etching methods using the same |
KR100583725B1 (en) * | 2003-11-07 | 2006-05-25 | 삼성전자주식회사 | Semiconductor Device Having Partially Insulated Field Effect Transistor PiFET And Method Of Fabricating The Same |
KR100598098B1 (en) * | 2004-02-06 | 2006-07-07 | 삼성전자주식회사 | Metal-Oxide-Semiconductor Having Buried Insulation Region And Methods Of Fabricating The Same |
US7256077B2 (en) * | 2004-05-21 | 2007-08-14 | Freescale Semiconductor, Inc. | Method for removing a semiconductor layer |
KR100555569B1 (en) * | 2004-08-06 | 2006-03-03 | 삼성전자주식회사 | Semiconductor device having the channel area restricted by insulating film and method of fabrication using the same |
JP4888118B2 (en) * | 2004-09-16 | 2012-02-29 | 富士通セミコンダクター株式会社 | Semiconductor device manufacturing method and semiconductor device |
CN101297408A (en) * | 2005-08-31 | 2008-10-29 | 斯平内克半导体股份有限公司 | Metal source/drain schottky barrier silicon-on-nothing MOSFET device and method thereof |
US7326601B2 (en) * | 2005-09-26 | 2008-02-05 | Advanced Micro Devices, Inc. | Methods for fabrication of a stressed MOS device |
JP2007165677A (en) * | 2005-12-15 | 2007-06-28 | Seiko Epson Corp | Method of manufacturing semiconductor substrate and semiconductor device |
JP2007201003A (en) * | 2006-01-24 | 2007-08-09 | Seiko Epson Corp | Method of manufacturing semiconductor substrate, method of manufacturing semiconductor device, and semiconductor device |
JP2007207960A (en) * | 2006-02-01 | 2007-08-16 | Seiko Epson Corp | Semiconductor substrate and device, and its manufacturing method |
FR2901058A1 (en) * | 2006-08-29 | 2007-11-16 | St Microelectronics Crolles 2 | Semiconductor device e.g. double-gate transistor, has cavity formed on substrate and filled with non exposed resin forming gate, and with resin exposed by beams, where exposed resin is isolated from rest of substrate by non exposed resin |
US8866254B2 (en) * | 2008-02-19 | 2014-10-21 | Micron Technology, Inc. | Devices including fin transistors robust to gate shorts and methods of making the same |
US20120146175A1 (en) * | 2010-12-09 | 2012-06-14 | Nicolas Loubet | Insulating region for a semiconductor substrate |
US9196522B2 (en) | 2013-10-16 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with buried insulator layer and method for forming |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH077773B2 (en) * | 1989-03-01 | 1995-01-30 | 工業技術院長 | Method for manufacturing semiconductor device |
JPH0521465A (en) * | 1991-07-10 | 1993-01-29 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
FR2749977B1 (en) * | 1996-06-14 | 1998-10-09 | Commissariat Energie Atomique | QUANTUM WELL MOS TRANSISTOR AND METHODS OF MANUFACTURE THEREOF |
US6043126A (en) * | 1996-10-25 | 2000-03-28 | International Rectifier Corporation | Process for manufacture of MOS gated device with self aligned cells |
US6015917A (en) * | 1998-01-23 | 2000-01-18 | Advanced Technology Materials, Inc. | Tantalum amide precursors for deposition of tantalum nitride on a substrate |
FR2799307B1 (en) * | 1999-10-01 | 2002-02-15 | France Telecom | SEMICONDUCTOR DEVICE COMBINING THE ADVANTAGES OF MASSIVE ARCHITECTURES AND ITSELF, MANUFACTURING METHOD |
US6352903B1 (en) * | 2000-06-28 | 2002-03-05 | International Business Machines Corporation | Junction isolation |
FR2812764B1 (en) * | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | METHOD FOR MANUFACTURING SUBSTRATE OF SUBSTRATE-SELF-INSULATION OR SUBSTRATE-ON-VACUUM AND DEVICE OBTAINED |
FR2821483B1 (en) * | 2001-02-28 | 2004-07-09 | St Microelectronics Sa | METHOD FOR MANUFACTURING A TRANSISTOR WITH INSULATED GRID AND ARCHITECTURE OF THE SUBSTRATE TYPE ON INSULATION, AND CORRESPONDING TRANSISTOR |
US6551937B2 (en) * | 2001-08-23 | 2003-04-22 | Institute Of Microelectronics | Process for device using partial SOI |
CN1253942C (en) * | 2002-02-20 | 2006-04-26 | 台湾积体电路制造股份有限公司 | MOS transistor structure for eliminating leakage current and CMOS image transistor |
JP4546021B2 (en) * | 2002-10-02 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | Insulated gate field effect transistor and semiconductor device |
-
2003
- 2003-09-23 US US10/668,714 patent/US6964911B2/en not_active Expired - Lifetime
-
2004
- 2004-09-10 WO PCT/US2004/029381 patent/WO2005034186A2/en active Application Filing
- 2004-09-10 EP EP04809709A patent/EP1668691A2/en not_active Withdrawn
- 2004-09-10 KR KR1020067005642A patent/KR101120770B1/en not_active IP Right Cessation
- 2004-09-10 CN CN2004800250641A patent/CN1846304B/en not_active Expired - Fee Related
- 2004-09-10 JP JP2006526936A patent/JP5068074B2/en not_active Expired - Fee Related
- 2004-09-22 TW TW093128719A patent/TWI364813B/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI450334B (en) * | 2007-04-20 | 2014-08-21 | Freescale Semiconductor Inc | Method for selective removal of a layer |
Also Published As
Publication number | Publication date |
---|---|
WO2005034186A3 (en) | 2005-11-03 |
EP1668691A2 (en) | 2006-06-14 |
TWI364813B (en) | 2012-05-21 |
CN1846304A (en) | 2006-10-11 |
KR101120770B1 (en) | 2012-03-23 |
WO2005034186A2 (en) | 2005-04-14 |
KR20060121883A (en) | 2006-11-29 |
CN1846304B (en) | 2012-01-11 |
US20050064669A1 (en) | 2005-03-24 |
US6964911B2 (en) | 2005-11-15 |
JP2007507092A (en) | 2007-03-22 |
JP5068074B2 (en) | 2012-11-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |