TWI364813B - Method for forming a semiconductor device having isolation regions - Google Patents
Method for forming a semiconductor device having isolation regions Download PDFInfo
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- TWI364813B TWI364813B TW093128719A TW93128719A TWI364813B TW I364813 B TWI364813 B TW I364813B TW 093128719 A TW093128719 A TW 093128719A TW 93128719 A TW93128719 A TW 93128719A TW I364813 B TWI364813 B TW I364813B
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- forming
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- semiconductor substrate
- dielectric
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- 239000004065 semiconductor Substances 0.000 title claims description 83
- 238000002955 isolation Methods 0.000 title claims description 37
- 238000000034 method Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims description 31
- VGRFVJMYCCLWPQ-UHFFFAOYSA-N germanium Chemical compound [Ge].[Ge] VGRFVJMYCCLWPQ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 claims 3
- 230000001590 oxidative effect Effects 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims 1
- 210000000078 claw Anatomy 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 239000002689 soil Substances 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 description 5
- 239000006117 anti-reflective coating Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000238631 Hexapoda Species 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- RBFDCQDDCJFGIK-UHFFFAOYSA-N arsenic germanium Chemical compound [Ge].[As] RBFDCQDDCJFGIK-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 229940119177 germanium dioxide Drugs 0.000 description 1
- GPMBECJIPQBCKI-UHFFFAOYSA-N germanium telluride Chemical compound [Te]=[Ge]=[Te] GPMBECJIPQBCKI-UHFFFAOYSA-N 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Description
1364813 以及一第一半導體層18,在該半導體裝置1〇上形成。在一 較佳之具體實施例中,該半導體裝置1〇係為矽,但是該半 導體裝置10可以是鍺化矽、砷化鍺等等或上述之結合。該 等隔離區域Μ可以是使用傳統方法形成之淺溝渠隔離(sti) 區域。在圖1所顯示之具體實施例中,該等隔離區域14係 為與該半導體基板12之頂端表面共平面。在另一具體實施 例中,該等隔離區域14高於該半導體基板12之頂端表面。 在提供一半導體基板12以及形成該等隔離區域14之後, 形成該第一半導體層16,在一具體實施例中,係藉由蟲晶 地生長一鍺化矽(SiGe)或矽(Si)層。或者,可以沉積一非 晶矽層以及經由加熱重新晶體化,形成一晶體結構於該第 一半導體層16。在另一具體實施例中,該半導體基板a之 頂端部分可以濃度高地植入,例如以鍺以及經由加熱重新 晶化,形成該第一半導體層16。如將在下面變得更明顯, 想要的是該第一半導體層丨6係為晶體,為了假如由磊晶生 長所行程,覆蓋之第二半導體層丨8係為一晶體層。 該第二半導體層18在該第一半導體層16上形成。在一具 體實施例中,該第二半導體層18係為磊晶地生長單晶矽 (Si),從該第一半導體層(16)生長,在該具體實施例中為 SiGe ^如將在下面變得更明顯,該第二半導體層18將作為 一通道區域於該半導體裝置,並且,因為想要的是,該第 二半導體層18具有一晶體結構,達成在該通道區域之所需 電氣特性。該第二半導體層18可以是任何半導體材料且較 佳為晶體。 96I17.doc 1364813 板12,以及在泫半導體基板12中形成凹處27。該等凹處u 可能形成,因為使用圖案化該第二半導體層18以及該第一 半導體層16之蝕刻化學特性可能不足以選擇性地於該半導 體基板12所使用之材料。 在蝕刻該第一介電層20、該第二半導體層18、以及該第 一半導體層16之後,使用一濕或電漿蝕刻移除該第一半導 體層16之部分,形成—缺口或空隙28。該化學特性係對於 該第二半導體層18、該半導體基板12以及該第一介電層2〇 和該等介電間隔物26有選擇性的。例如,假如該第一半導 體層16係為矽化鍺,該第二半導體層18以及該半導體基板 12係為矽,而該第一介電層2〇以及該等介電間隔物%係為 二氧化矽時,可以使用稀釋11]?、氮酸和水,蝕刻該第一半 導體層16。在圖3所顯示之具體實施例中,基本上移除全 部孩第一半導體層16。然而,假如該閘極長度大於或相等 於接近0.6微米時,一部分之該第一半導體層16(該第一半 導體層16之剩餘部份)可能保留在該閘極電極22之下。該 第一半導體層16之剩餘部份將接近在該缺口 28之中心,因 為該化學物不能夠移除該第一半導體層16之全部。換句話 說,假如該閘極長度夠長的話,該缺口 28將由未移除之該 第半導體層16之一部分所分割。然而,在所顯示之該具 體實施例中,移除整個該第一半導體層丨6。 當移除該第一半導體層16以形成該缺口 28時,在該缺口 28上之該等層由該閘極電極22和在該半導體裝置1〇之部分 中之該等氮化物間隔物24以及該等介電間隔物26所支撐, 96I17.doc 1364813 圖3未顯示,但是顯示在圖4中。圖4係為以垂直該頁之方 向,圖3之剖面檢視圖(即是,進出該頁)。因此,圖3和4中 之結構彼此垂直。 如圖4所顯示,該第一介電層20包圍該第二半導體層18 且已經圍繞該第一半導體層16。換句話說,該第一介電層 20將該第二半導體層18與該閘極電極22隔離。當移除該第 一半導體層16時,該第一介電層20可能圍繞該缺口 28。或 者,當形成該缺口28時,可以移除圍繞該第一半導體層16 之該第一介電層20。該閘極電極22延伸超過該第一介電層 20至該等隔離區域14。此外,該等氮化物間隔物24以及該 等介電間隔物26,如圖4所顯示,也在該等隔離區域14上 終結。 圖5顯示在填充該缺口 28以形成一隧道下方層29之後, 圖3之半導體裝置10。在移除該第一半導體層16之至少一 部分之後,至少一第二介電層30以及一第三介電層34在該 缺口 28内形成。該第二介電層30以及該第三介電層34可以 藉由快速熱氧化(RTO)而形成,產生在該第二半導體層18 之底部表面以及該第二介電層30和該半導體基板12之頂端 以及該第三介電層30之間之高品質介面。在該RTO之後, 可以沉積一高溫氧化物(HTO),以加厚該第二介電層30以 及該第三介電層30至所需厚度。因為在形成該第二介電層 30和該第三介電層34之該等方法期間,該半導體裝置10並 不被遮罩,任何暴露表面將被氧化。因此,如圖5所顯 示,該第二介電層30與該閘極電極22之一部分、該等介電 96117.doc 1364813 半導體基板12上先前產生之氧化物,例如該第三介電層34 之一部分上形成。因此,假如存在的話,可以氧化該等凹 處27。可以執行一乾氧化、濕氧化以及兩者之結合,形成 該等電流電極介電隔離結構36。 在一具體實施例中,該等電流電極介電隔離結構36厚度 接近50至1000埃(50-100奈米),或較佳地接近50-500埃(5_ 50奈米)或較佳地接近100-300埃(10-30奈米)。無論如何, 當該等源極和汲極形成時,該等電流電極介電隔離結構36 不應該完全地覆蓋該第二半導體層18之側牆,因為該第二 半導體層18將隨後地使用於磊晶生長電流電極。 在一具體實施例中,該等電流電極介電隔離結構36也可 係為氮化物,因此係為氧氮化物之區域。假如該半導體基 板12係為矽,該等電流電極介電隔離結構3 6可以是二氧化 矽,或假如氮化的化,為矽氧氮化物。氧化之溫度較佳在 700至1100攝氏溫度之間。在圖6所顯示之具體實施例中, 該等電流電極介電隔離結構36將在該半導體基板12内形成 且將與該隔離區域14和該第三介電層34接觸。在該等電流 電極介電隔離結構36之形成期間,為了防止該閘極電極22 之頂端氧化,可以存在一反反射塗覆(ARC)。當蝕刻該閘 極電極22時,該ARC已經形成,且不能移除直到該等電流 電極介電隔離結構36形成之後。 在形成該等電流電極介電隔離結構36之後,維持在該隧 道下層29之該氮化物層32之部分使用蝕刻方法而移除,在 一具體實施例中,對於該第二介電層30所使用之材料有選 96117.doc U64813 利盈、其他優點及問題之解法古 鮮决万法係可於特定具體實施 例而描述在上。然而,利益、並 、 其他優點及問題之解決方法 以及產生任何利益、其他優點及問題之解決方法發生之任 何元件或被判斷並不被视為任何或全部中請專利範圍之重 要、需要或基本特點或元件。如在此使用,該名詞"包括"、 L包含"、或任何變化意圖包括一非獨排性包括,例如包括 ;串之元件之過程、方法、物品、或裝置並不包括僅有這 些元件而是可以包括未明顯列出來或這樣之過程、方法、 物品或裝置所自然具有的之其他元件。 【圖式簡單說明】 本發明藉由範例之方式說明且並不被該等隨附圖式所限 制’其中相同參考指示相同元件。 圖1顯不根據本發明之一具體實施例之具有半導體層在 一半導體基板上形成之半導體裝置之一部分之剖面圖; 圖2顯示根據本發明之一具體實施例,在形成一介電 層、一閘極電極以及間隔物之後之圖1之半導體裝置; 圖3顯不根據本發明之一具體實施例’在移除一磊晶層 之後,圖2之該半導體裝置; 圖3之該半導體裝 圖4顯示根據本發明之一具體實施例 置之剖面邵分之另一部分和檢视圖; 在形成絕緣層之 圖5顯TF根據本發明之一具體實施例 後,圖3之該半導體裝置; 圖6顯不根據本發明之一具體實施例 介电隔離結構之後,圖5之該半導體装置; 在形成電流電極 96117.doc -15-
Claims (1)
- 第093128719號專利申請案 中文申請專利範圍替換本('101年1月) 丨。丨年丨月阳修(更)正替換頁 十、申請專利範圍: ^ 一=製造一隔離電晶體之方法,包括: 提供—半導體基板,其具有一裝置結構在其上,該裝 構包括一通道結構以及一在該通道結構上之控;;電 上、。構’該通道結構係懸置於該半導體基板上及懸置於 該控制電極結構下; ^ 、 在該通道結構以及該半導體基板之間沉積—通道隔離 層; 、f成電/爪電極介電隔離結構,其橫向地配置於該通 道結構;以及 j該電流電極介電隔離結構上沉積一電流電極結構。 如μ求項1之方法’其中該提供該半導體基板和裝置結 構包括: 提供該半導體基板; 形成一第一合成物之一第一層; 在°亥第—層上形成一第二合成物之一第二層,該第二 層用於提供該通道結構; 在該第一層上形成一介電層;以及 在該介電層上形成該控制電極結構之至少一部分。 3.如叫求項2之方法,其中該提供該半導體基板和裝置結 構尚包括: 在從該控制電極結構’橫向地配置之複數個電流電極 區域上钱刻該介電層和該等第-和第二層;以及 ㈣該第-層以實質上從該第二層下移除該第一層, 96117-1010109.doc Μ年,月?日修(灸〉正垮夜1364813 在該装置結構之一通道區域下提供一空隙。 4.如請求項2之方法,其中: 形成該第一合成物之該第一層包括形成矽化鍺; 形成該第二合成物之該第二層包括形成矽;以及 形成該介電層包括形成二氧化矽。 5·如請求項1之方法,其中該通道隔離層包括三個子層, 以及該沉積該通道隔離層包括: 實質上在該裝置結構四周形成一第一介電層,以及在 該半導體基板和在該通道結構下形成一第二介電層,該 等第一和第二介電層具有一第一钱刻特性;以及 實質上在該第一介電層四周和該通道結構下之該第二 介電層上形成一第三介電層,該等第三介電層具有一第 二钮刻特性β 6.如請求項1之方法,其中該形成該電流電極介電隔離結 構包括: 讓該半導體基板遭受一包含氧之環境;以及 至少在該電流電極結構,氧化該半導體基板之頂端表 面,以在該半導體基板上生長—氧化物隔離結構,該電 流電極介電隔離結構包括該氧化物隔離結構。 一種製造一半導體裝置之方法,該方法包括: 形成一晶體結構,該晶體結構藉由連接至一半導體基 板之一支撐結構而懸置於該半導體基板上. 土 在該半導體基板内形成-第一介電隔離結構; 在該半導體基板内形成—第二介電隔離結構; 961I7-I0l0109.doc _ __ °丨年丨月7日修(更)正替換頁 緊鄰於該等第一釦坌_入而 罘和第一介電隔離結構和在該半導體基 板之間形成一第三A電隔離結構; " 在該第—介電隔離結構上沉積一第一電流電極結 以及 ’ 在該第二介電隔離結構上沉積一第二電流電極結構。 8_ 一種製造一隔離電晶體之方法,包括: 提供一基板; 在一通道結構下形成一通道隔離結構; 在橫向地配置於該通道結構之第一電流電極區域和第 二電流電極區域之每一者處’在該基板中形成一 电後電 極隔離結構,該通道隔離結構以及該等電流電極隔離、结 構被形成為相互毗鄰;以及 在每個該等電流電極隔離結構上’磊晶地自該通道妹 構生長一電流電極。 9.如請求項8之方法,其中該形成該等電流電極隔離結構 包括氧化該基板之至少一部分。 96117-1010109.doc
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FR2812764B1 (fr) * | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu |
FR2821483B1 (fr) * | 2001-02-28 | 2004-07-09 | St Microelectronics Sa | Procede de fabrication d'un transistor a grille isolee et a architecture du type substrat sur isolant, et transistor correspondant |
US6551937B2 (en) * | 2001-08-23 | 2003-04-22 | Institute Of Microelectronics | Process for device using partial SOI |
CN1253942C (zh) * | 2002-02-20 | 2006-04-26 | 台湾积体电路制造股份有限公司 | 可避免产生漏电流的mos管结构及具有该结构的cmos影像管 |
JP4546021B2 (ja) * | 2002-10-02 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | 絶縁ゲート型電界効果型トランジスタ及び半導体装置 |
-
2003
- 2003-09-23 US US10/668,714 patent/US6964911B2/en not_active Expired - Lifetime
-
2004
- 2004-09-10 KR KR1020067005642A patent/KR101120770B1/ko not_active IP Right Cessation
- 2004-09-10 CN CN2004800250641A patent/CN1846304B/zh not_active Expired - Fee Related
- 2004-09-10 WO PCT/US2004/029381 patent/WO2005034186A2/en active Application Filing
- 2004-09-10 JP JP2006526936A patent/JP5068074B2/ja not_active Expired - Fee Related
- 2004-09-10 EP EP04809709A patent/EP1668691A2/en not_active Withdrawn
- 2004-09-22 TW TW093128719A patent/TWI364813B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US6964911B2 (en) | 2005-11-15 |
TW200520146A (en) | 2005-06-16 |
EP1668691A2 (en) | 2006-06-14 |
WO2005034186A2 (en) | 2005-04-14 |
WO2005034186A3 (en) | 2005-11-03 |
JP2007507092A (ja) | 2007-03-22 |
CN1846304B (zh) | 2012-01-11 |
CN1846304A (zh) | 2006-10-11 |
JP5068074B2 (ja) | 2012-11-07 |
KR20060121883A (ko) | 2006-11-29 |
US20050064669A1 (en) | 2005-03-24 |
KR101120770B1 (ko) | 2012-03-23 |
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