JP2007507092A - 分離領域を有する半導体デバイスを形成するための方法 - Google Patents
分離領域を有する半導体デバイスを形成するための方法 Download PDFInfo
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- 238000002955 isolation Methods 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 17
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- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 5
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- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 5
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
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- 239000001301 oxygen Substances 0.000 claims 1
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- 150000004767 nitrides Chemical class 0.000 description 22
- 125000006850 spacer group Chemical group 0.000 description 10
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
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- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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Abstract
Description
本発明は例示であり、添付の図面によって制限されない。なお、添付の図面では、類似の参照番号は類似の構成要素を指している。
図1は半導体デバイス10の断面を示しており、半導体デバイス10内に分離領域14が形成され、半導体デバイス10上に第1の半導体層16及び第2の半導体層18が形成されている。好ましい実施形態では、半導体デバイス10はシリコンであるが、半導体デバイス10には、シリコンゲルマニウム、ガリウムヒ素等、及び上記の材料の組み合わせを用いることができる。分離領域14は、従来の方法を用いて形成される、浅いトレンチ分離(STI)領域にすることができる。図1に示される実施形態では、分離領域14は、半導体基板12の上側表面と同一平面を成す。別の実施形態では、分離領域14は半導体基板12の上側表面よりも高い。
有することが望ましい。第2の半導体層18には任意の半導体材料を用いることができるが、結晶性であることが好ましい。
、半導体デバイス10の複数の部分において、ゲート電極22並びに窒化物スペーサ24及び誘電体スペーサ26によって支持され、それは図3には示されないが、図4に示される。図4は、紙面に対して垂直な(すなわち紙面に対して出入りする)方向の図3の断面図である。したがって、図3及び図4の構造は互いに対して垂直である。
できる。ドライ酸化、ウエット酸化又は2つの組み合わせを実行して、電流電極誘電体分離構造36を形成することができる。
つの分離領域を有する半導体デバイスを形成するための方法が提供されてきたことは理解されたい。一実施形態では、その半導体デバイスは分離されたトランジスタである。電流電極誘電体分離構造36は、半導体基板12を通る、電流電極40間の漏れ経路を防ぐか、又は最小限に抑える。隙間28内にある第2の誘電体層30、窒化物層32及び第3の誘電体層34は、チャネル内の電流の漏れを防ぐか、又は最小限に抑える。
Claims (10)
- チャネル構造、及び該チャネル構造の上に重なる制御電極構造を備え、前記チャネル構造は前記半導体基板から離隔してその上方にあり、前記制御電極構造の下にある、デバイス構造を有した半導体基板を配設する工程と、
前記チャネル構造と前記半導体基板との間にチャネル分離層を堆積する工程と、
前記チャネル構造の横方向に配置される電流電極誘電体分離構造を形成する工程と、
前記電流電極誘電体分離構造上に電流電極構造を堆積する工程とを備える、分離されたトランジスタの製造方法。 - 前記半導体基板及び前記デバイス構造を配設する前記工程は、
前記半導体基板を配設する工程と、
第1の組成の第1の層を形成する工程と、
前記チャネル構造を設けるための第2の組成の第2の層を前記第1の層上に形成する工程と、
前記第2の層上に誘電体層を形成する工程と、
前記誘電体層上に前記制御電極構造の少なくとも一部を形成する工程とからなる、請求項1に記載の分離されたトランジスタの製造方法。 - 前記半導体基板及び前記デバイス構造を前記配設する工程は、
前記制御電極構造から横方向に配置される複数の電流電極領域上にある前記誘電体層、並びに前記第1の層及び前記第2の層をエッチングする工程と、
前記第1の層をエッチングすることによって、前記第2の層の下から前記第1の層を概ね除去し、前記デバイス構造のチャネル領域の下にある空所を設ける、エッチング工程とをさらに備える、請求項2に記載の分離されたトランジスタの製造方法。 - 前記第1の組成の前記第1の層を形成する工程は、シリコンゲルマニウムを形成する工程からなり、
前記第2の組成の前記第2の層を形成する工程は、シリコンを形成する工程からなり、
前記誘電体層を形成する工程は、二酸化シリコンを形成する工程からなる、請求項2に記載の分離されたトランジスタの製造方法。 - 前記チャネル分離層は3つの副層を含み、前記チャネル分離層を前記堆積する工程は、
前記デバイス構造の概ね周囲に第1の誘電体層を形成し、及び前記半導体基板上及び前記チャネル構造下に第2の誘電体層を形成する工程であって、前記第1の誘電体層及び前記第2の誘電体層は第1のエッチング特性を有する、第1及び第2の誘電体層形成工程と、
前記第1の誘電体層の概ね周囲に、且つ前記チャネル構造下にある前記第2の誘電体層上に第2のエッチング特性を有する第3の誘電体層を形成する工程とからなる、請求項1に記載の分離されたトランジスタの製造方法。 - 前記電流電極誘電体分離構造を前記形成する工程は、
前記半導体基板を酸素含有環境に晒す工程と、
少なくとも前記電流電極構造において前記半導体基板の上側表面を酸化することによって前記半導体基板上に酸化物分離構造を成長させる、酸化工程であって、前記電流電極誘電体分離構造は前記酸化物分離構造を含む、酸化工程とからなる、請求項1に記載の分離された分離されたトランジスタの製造方法。 - 半導体基板内に第1の誘電体分離構造を形成する工程と、
前記半導体基板内に第2の誘電体分離構造を形成する工程と、
前記第1及び前記第2の誘電体分離構造に当接し、且つ前記半導体基板と、該半導体基板に結合される支持構造によって該半導体基板の上方に離隔した状態で支持される結晶性構造との間に第3の誘電体分離構造を形成する工程と、
前記第1の誘電体分離構造上に第1の電流電極構造を堆積する工程と、
前記第2の誘電体分離構造上に第2の電流電極構造を堆積する工程とからなる、半導体デバイスの製造方法。 - 基板を配設する工程と、
チャネル構造の下にチャネル分離構造を形成する工程と、
前記チャネル構造に対して横方向に配置される第1及び第2の電流電極領域のそれぞれにおいて前記基板内に電流電極分離構造を形成する工程であって、前記チャネル分離構造及び前記電流電極分離構造は隣接するように形成される、電流電極分離構造形成工程と、
前記電流電極分離構造のそれぞれの上に電流電極をエピタキシャル成長させる工程とからなる、分離されたトランジスタの製造方法。 - 前記電流電極分離構造形成工程は、前記基板の少なくとも一部を酸化することからなる、請求項8に記載の分離されたトランジスタの製造方法。
- 前記基板上に前記第1及び第2の誘電体層を形成する工程は、概ね同時に実行される、請求項8に記載の分離されたトランジスタの製造方法。
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US10/668,714 US6964911B2 (en) | 2003-09-23 | 2003-09-23 | Method for forming a semiconductor device having isolation regions |
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PCT/US2004/029381 WO2005034186A2 (en) | 2003-09-23 | 2004-09-10 | Method for forming a semiconductor device having isolation regions |
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JP2007201003A (ja) * | 2006-01-24 | 2007-08-09 | Seiko Epson Corp | 半導体基板の製造方法及び半導体装置の製造方法、半導体装置 |
JP2007207960A (ja) * | 2006-02-01 | 2007-08-16 | Seiko Epson Corp | 半導体基板、半導体基板の製造方法及び半導体装置 |
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US20040242015A1 (en) * | 2003-03-04 | 2004-12-02 | Kyoung-Chul Kim | Etching compositions for silicon germanium and etching methods using the same |
KR100583725B1 (ko) * | 2003-11-07 | 2006-05-25 | 삼성전자주식회사 | 부분적으로 절연된 전계효과 트랜지스터를 구비하는반도체 장치 및 그 제조 방법 |
KR100598098B1 (ko) * | 2004-02-06 | 2006-07-07 | 삼성전자주식회사 | 매몰 절연 영역을 갖는 모오스 전계 효과 트랜지스터 및그 제조 방법 |
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KR100555569B1 (ko) * | 2004-08-06 | 2006-03-03 | 삼성전자주식회사 | 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법 |
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JP2007165677A (ja) * | 2005-12-15 | 2007-06-28 | Seiko Epson Corp | 半導体基板の製造方法及び半導体装置 |
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- 2004-09-10 WO PCT/US2004/029381 patent/WO2005034186A2/en active Application Filing
- 2004-09-10 KR KR1020067005642A patent/KR101120770B1/ko not_active IP Right Cessation
- 2004-09-10 JP JP2006526936A patent/JP5068074B2/ja not_active Expired - Fee Related
- 2004-09-10 CN CN2004800250641A patent/CN1846304B/zh not_active Expired - Fee Related
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JP2007207960A (ja) * | 2006-02-01 | 2007-08-16 | Seiko Epson Corp | 半導体基板、半導体基板の製造方法及び半導体装置 |
Also Published As
Publication number | Publication date |
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KR101120770B1 (ko) | 2012-03-23 |
TWI364813B (en) | 2012-05-21 |
EP1668691A2 (en) | 2006-06-14 |
US6964911B2 (en) | 2005-11-15 |
US20050064669A1 (en) | 2005-03-24 |
KR20060121883A (ko) | 2006-11-29 |
CN1846304A (zh) | 2006-10-11 |
WO2005034186A3 (en) | 2005-11-03 |
TW200520146A (en) | 2005-06-16 |
CN1846304B (zh) | 2012-01-11 |
JP5068074B2 (ja) | 2012-11-07 |
WO2005034186A2 (en) | 2005-04-14 |
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