JP2007513455A5 - - Google Patents

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Publication number
JP2007513455A5
JP2007513455A5 JP2006542728A JP2006542728A JP2007513455A5 JP 2007513455 A5 JP2007513455 A5 JP 2007513455A5 JP 2006542728 A JP2006542728 A JP 2006542728A JP 2006542728 A JP2006542728 A JP 2006542728A JP 2007513455 A5 JP2007513455 A5 JP 2007513455A5
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Japan
Prior art keywords
nand string
integrated circuit
memory
bit line
devices
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JP2006542728A
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Japanese (ja)
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JP2007513455A (ja
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Priority claimed from US10/729,865 external-priority patent/US20050128807A1/en
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Publication of JP2007513455A publication Critical patent/JP2007513455A/ja
Publication of JP2007513455A5 publication Critical patent/JP2007513455A5/ja
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JP2006542728A 2003-12-05 2004-12-02 複数の直列選択デバイスを組込んだｎａｎｄメモリアレイおよびその動作方法 Withdrawn JP2007513455A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/729,865 US20050128807A1 (en) 2003-12-05 2003-12-05 Nand memory array incorporating multiple series selection devices and method for operation of same
PCT/US2004/040283 WO2005057586A2 (en) 2003-12-05 2004-12-02 Nand memory array incorporating multiple series selection devices and method for operation of same

Publications (2)

Publication Number Publication Date
JP2007513455A JP2007513455A (ja) 2007-05-24
JP2007513455A5 true JP2007513455A5 (enExample) 2008-01-31

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JP2006542728A Withdrawn JP2007513455A (ja) 2003-12-05 2004-12-02 複数の直列選択デバイスを組込んだｎａｎｄメモリアレイおよびその動作方法

Country Status (6)

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US (1) US20050128807A1 (enExample)
EP (1) EP1695356A2 (enExample)
JP (1) JP2007513455A (enExample)
KR (1) KR20070003818A (enExample)
CN (1) CN1906700A (enExample)
WO (1) WO2005057586A2 (enExample)

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