JP2008527585A5 - - Google Patents

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Publication number
JP2008527585A5
JP2008527585A5 JP2007549434A JP2007549434A JP2008527585A5 JP 2008527585 A5 JP2008527585 A5 JP 2008527585A5 JP 2007549434 A JP2007549434 A JP 2007549434A JP 2007549434 A JP2007549434 A JP 2007549434A JP 2008527585 A5 JP2008527585 A5 JP 2008527585A5
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Japan
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level
circuit
integrated circuit
bias
coupled
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JP2007549434A
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JP5032336B2 (ja
JP2008527585A (ja
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Priority claimed from US11/026,470 external-priority patent/US7286439B2/en
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JP2007549434A 2004-12-30 2005-12-16 複数ヘッドデコーダの複数のレベルを使用した高密度メモリアレイの階層復号化のための機器および方法 Expired - Fee Related JP5032336B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/026,470 2004-12-30
US11/026,470 US7286439B2 (en) 2004-12-30 2004-12-30 Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders
PCT/US2005/045564 WO2006073735A1 (en) 2004-12-30 2005-12-16 Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders

Publications (3)

Publication Number Publication Date
JP2008527585A JP2008527585A (ja) 2008-07-24
JP2008527585A5 true JP2008527585A5 (enExample) 2009-02-12
JP5032336B2 JP5032336B2 (ja) 2012-09-26

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JP2007549434A Expired - Fee Related JP5032336B2 (ja) 2004-12-30 2005-12-16 複数ヘッドデコーダの複数のレベルを使用した高密度メモリアレイの階層復号化のための機器および方法

Country Status (6)

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US (2) US7286439B2 (enExample)
EP (2) EP2450902B1 (enExample)
JP (1) JP5032336B2 (enExample)
KR (1) KR101194353B1 (enExample)
CN (2) CN101138047B (enExample)
WO (1) WO2006073735A1 (enExample)

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