JP2009545835A5 - - Google Patents

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Publication number
JP2009545835A5
JP2009545835A5 JP2009523020A JP2009523020A JP2009545835A5 JP 2009545835 A5 JP2009545835 A5 JP 2009545835A5 JP 2009523020 A JP2009523020 A JP 2009523020A JP 2009523020 A JP2009523020 A JP 2009523020A JP 2009545835 A5 JP2009545835 A5 JP 2009545835A5
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JP
Japan
Prior art keywords
bit line
mode
voltage
line
word line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009523020A
Other languages
English (en)
Japanese (ja)
Other versions
JP5252233B2 (ja
JP2009545835A (ja
Filing date
Publication date
Priority claimed from US11/461,339 external-priority patent/US7554832B2/en
Priority claimed from US11/461,364 external-priority patent/US7463546B2/en
Application filed filed Critical
Priority claimed from PCT/US2007/074883 external-priority patent/WO2008016932A2/en
Publication of JP2009545835A publication Critical patent/JP2009545835A/ja
Publication of JP2009545835A5 publication Critical patent/JP2009545835A5/ja
Application granted granted Critical
Publication of JP5252233B2 publication Critical patent/JP5252233B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009523020A 2006-07-31 2007-07-31 極性が反転可能なワード線およびビット線デコーダを組込んだ受動素子メモリアレイのための方法および装置 Active JP5252233B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/461,339 US7554832B2 (en) 2006-07-31 2006-07-31 Passive element memory array incorporating reversible polarity word line and bit line decoders
US11/461,364 2006-07-31
US11/461,339 2006-07-31
US11/461,364 US7463546B2 (en) 2006-07-31 2006-07-31 Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders
PCT/US2007/074883 WO2008016932A2 (en) 2006-07-31 2007-07-31 Method and apparatus for passive element memory array incorporating reversible polarity word line and bit line decoders

Publications (3)

Publication Number Publication Date
JP2009545835A JP2009545835A (ja) 2009-12-24
JP2009545835A5 true JP2009545835A5 (enExample) 2010-09-16
JP5252233B2 JP5252233B2 (ja) 2013-07-31

Family

ID=38997814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009523020A Active JP5252233B2 (ja) 2006-07-31 2007-07-31 極性が反転可能なワード線およびビット線デコーダを組込んだ受動素子メモリアレイのための方法および装置

Country Status (5)

Country Link
EP (1) EP2062262B1 (enExample)
JP (1) JP5252233B2 (enExample)
KR (1) KR101478193B1 (enExample)
TW (1) TWI345785B (enExample)
WO (1) WO2008016932A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5322533B2 (ja) * 2008-08-13 2013-10-23 株式会社東芝 不揮発性半導体記憶装置、及びその製造方法
US9202533B2 (en) 2013-10-09 2015-12-01 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device changing the number of selected bits and/or the number of selected bays at data write operation
US9390792B2 (en) 2013-12-23 2016-07-12 Micron Technology, Inc. Apparatuses, memories, and methods for address decoding and selecting an access line
KR102480013B1 (ko) * 2018-11-26 2022-12-22 삼성전자 주식회사 누설 전류를 보상하는 메모리 장치 및 이의 동작 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5379250A (en) 1993-08-20 1995-01-03 Micron Semiconductor, Inc. Zener programmable read only memory
US6483736B2 (en) * 1998-11-16 2002-11-19 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6314014B1 (en) * 1999-12-16 2001-11-06 Ovonyx, Inc. Programmable resistance memory arrays with reference cells
US6631085B2 (en) * 2000-04-28 2003-10-07 Matrix Semiconductor, Inc. Three-dimensional memory array incorporating serial chain diode stack
US6618295B2 (en) * 2001-03-21 2003-09-09 Matrix Semiconductor, Inc. Method and apparatus for biasing selected and unselected array lines when writing a memory array
US6917539B2 (en) 2002-08-02 2005-07-12 Unity Semiconductor Corporation High-density NVRAM
JP2004071023A (ja) * 2002-08-05 2004-03-04 Elpida Memory Inc 半導体記憶装置
US6847047B2 (en) * 2002-11-04 2005-01-25 Advanced Micro Devices, Inc. Methods that facilitate control of memory arrays utilizing zener diode-like devices
JP2007536680A (ja) * 2004-05-03 2007-12-13 ユニティ・セミコンダクター・コーポレーション 不揮発性プログラマブルメモリ
JP4524455B2 (ja) * 2004-11-26 2010-08-18 ルネサスエレクトロニクス株式会社 半導体装置
US7286439B2 (en) * 2004-12-30 2007-10-23 Sandisk 3D Llc Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders

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