KR101478193B1 - 가역 극성 워드 라인과 비트 라인 디코더를 결합한 패시브 엘리먼트 메모리 어레이용 방법과 장치 - Google Patents

가역 극성 워드 라인과 비트 라인 디코더를 결합한 패시브 엘리먼트 메모리 어레이용 방법과 장치 Download PDF

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KR101478193B1
KR101478193B1 KR20097004221A KR20097004221A KR101478193B1 KR 101478193 B1 KR101478193 B1 KR 101478193B1 KR 20097004221 A KR20097004221 A KR 20097004221A KR 20097004221 A KR20097004221 A KR 20097004221A KR 101478193 B1 KR101478193 B1 KR 101478193B1
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South Korea
Prior art keywords
bit line
mode
line
lines
voltage
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Expired - Fee Related
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KR20097004221A
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English (en)
Korean (ko)
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KR20090057231A (ko
Inventor
루카 쥐. 파솔리
크리스토퍼 제이. 페티
로이 이. 쉐얼라인
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쌘디스크 3디 엘엘씨
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Priority claimed from US11/461,339 external-priority patent/US7554832B2/en
Priority claimed from US11/461,364 external-priority patent/US7463546B2/en
Application filed by 쌘디스크 3디 엘엘씨 filed Critical 쌘디스크 3디 엘엘씨
Publication of KR20090057231A publication Critical patent/KR20090057231A/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
KR20097004221A 2006-07-31 2007-07-31 가역 극성 워드 라인과 비트 라인 디코더를 결합한 패시브 엘리먼트 메모리 어레이용 방법과 장치 Expired - Fee Related KR101478193B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/461,339 US7554832B2 (en) 2006-07-31 2006-07-31 Passive element memory array incorporating reversible polarity word line and bit line decoders
US11/461,364 2006-07-31
US11/461,339 2006-07-31
US11/461,364 US7463546B2 (en) 2006-07-31 2006-07-31 Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders
PCT/US2007/074883 WO2008016932A2 (en) 2006-07-31 2007-07-31 Method and apparatus for passive element memory array incorporating reversible polarity word line and bit line decoders

Publications (2)

Publication Number Publication Date
KR20090057231A KR20090057231A (ko) 2009-06-04
KR101478193B1 true KR101478193B1 (ko) 2015-01-02

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KR20097004221A Expired - Fee Related KR101478193B1 (ko) 2006-07-31 2007-07-31 가역 극성 워드 라인과 비트 라인 디코더를 결합한 패시브 엘리먼트 메모리 어레이용 방법과 장치

Country Status (5)

Country Link
EP (1) EP2062262B1 (enExample)
JP (1) JP5252233B2 (enExample)
KR (1) KR101478193B1 (enExample)
TW (1) TWI345785B (enExample)
WO (1) WO2008016932A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111223509A (zh) * 2018-11-26 2020-06-02 三星电子株式会社 具有对漏电流的补偿的存储器装置及其操作方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5322533B2 (ja) * 2008-08-13 2013-10-23 株式会社東芝 不揮発性半導体記憶装置、及びその製造方法
US9202533B2 (en) 2013-10-09 2015-12-01 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device changing the number of selected bits and/or the number of selected bays at data write operation
US9390792B2 (en) 2013-12-23 2016-07-12 Micron Technology, Inc. Apparatuses, memories, and methods for address decoding and selecting an access line

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040160819A1 (en) * 2002-08-02 2004-08-19 Unity Semiconductor Corporation High-density NVRAM

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US5379250A (en) 1993-08-20 1995-01-03 Micron Semiconductor, Inc. Zener programmable read only memory
US6483736B2 (en) * 1998-11-16 2002-11-19 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6314014B1 (en) * 1999-12-16 2001-11-06 Ovonyx, Inc. Programmable resistance memory arrays with reference cells
US6631085B2 (en) * 2000-04-28 2003-10-07 Matrix Semiconductor, Inc. Three-dimensional memory array incorporating serial chain diode stack
US6618295B2 (en) * 2001-03-21 2003-09-09 Matrix Semiconductor, Inc. Method and apparatus for biasing selected and unselected array lines when writing a memory array
JP2004071023A (ja) * 2002-08-05 2004-03-04 Elpida Memory Inc 半導体記憶装置
US6847047B2 (en) * 2002-11-04 2005-01-25 Advanced Micro Devices, Inc. Methods that facilitate control of memory arrays utilizing zener diode-like devices
JP2007536680A (ja) * 2004-05-03 2007-12-13 ユニティ・セミコンダクター・コーポレーション 不揮発性プログラマブルメモリ
JP4524455B2 (ja) * 2004-11-26 2010-08-18 ルネサスエレクトロニクス株式会社 半導体装置
US7286439B2 (en) * 2004-12-30 2007-10-23 Sandisk 3D Llc Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040160819A1 (en) * 2002-08-02 2004-08-19 Unity Semiconductor Corporation High-density NVRAM

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Chen et al.,‘An Access-Transistor-Free(0T/1R) Non-Volatile Resistance Random Access Memory(RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device’, IEEE IEDM 2003, 8-10 Dec. 2003
Chen et al.,'An Access-Transistor-Free(0T/1R) Non-Volatile Resistance Random Access Memory(RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device', IEEE IEDM 2003, 8-10 Dec. 2003 *
W.W. Zhuang et al.,‘Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory(RRAM)’, IEEE IEDM 2002, Pages 193-196, San Francisco, CA, USA, 8-11 Dec. 2002.
W.W. Zhuang et al.,'Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory(RRAM)', IEEE IEDM 2002, Pages 193-196, San Francisco, CA, USA, 8-11 Dec. 2002. *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111223509A (zh) * 2018-11-26 2020-06-02 三星电子株式会社 具有对漏电流的补偿的存储器装置及其操作方法
KR20200062463A (ko) * 2018-11-26 2020-06-04 삼성전자주식회사 누설 전류를 보상하는 메모리 장치 및 이의 동작 방법
KR102480013B1 (ko) 2018-11-26 2022-12-22 삼성전자 주식회사 누설 전류를 보상하는 메모리 장치 및 이의 동작 방법

Also Published As

Publication number Publication date
KR20090057231A (ko) 2009-06-04
EP2062262A4 (en) 2009-09-02
EP2062262B1 (en) 2014-05-07
TWI345785B (en) 2011-07-21
JP5252233B2 (ja) 2013-07-31
WO2008016932A3 (en) 2008-09-18
EP2062262A2 (en) 2009-05-27
JP2009545835A (ja) 2009-12-24
WO2008016932A2 (en) 2008-02-07
TW200814067A (en) 2008-03-16

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